ARM: dts: imx: Add Engicam 1.5 MX6 support

Hello,
the 'EDIMM Starter Kit 1.5 MIPI Evaluation" board, whose support has been
introduced by commit:
commit 3fe08835773121870b1de7d0cac9a4ade796661e ("ARM: dts: imx6q: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support")

is actually based on 1.5 version of the "i.Core 1.5 MX6" CPU module which differs from the original "i.Core MX6" for a few details, including the one that has sparkled this activity: the ethernet PHY interface clock provider.

Instead of fixing the PHY clock provider in the imx6q-icore-mipi.dts file, I preferred adding a new .dtsi for the 1.5 version of the module, to gather differences between version in a single place. Then I've referenced the new one in the dts file.

As a result, the ethernet interface is now working on the EDIMM 1.5 MIPI evaluation kit.

Thanks
j

v1 -> v2:
- Add Fabio's Reviewed-by tags
- Adjust commit message in [2/2]

Jacopo Mondi (2):
ARM: dts: imx6qdl: Add Engicam i.Core 1.5 MX6
ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6

 arch/arm/boot/dts/imx6q-icore-mipi.dts   |  4 ++--
 arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi | 34 ++++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi

--
2.7.4

From: Jacopo Mondi <[email protected]>

The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock provider for the ethernet's PHY interface. Adjust the FEC ptp clock to reference CLK_ENET_REF clock source, and set SION bit of MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin.

The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single place differences between version '1.0' and '1.5' of the module.

---
 arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi | 34 ++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi

new file mode 100644
index 0000000..d91d46b
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jacopo Mondi <[email protected]>
+ */
+
+#include "imx6qdl-icore.dtsi"
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
+		>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+	clocks = <&clks IMX6QDL_CLK_ENET>,
+		 <&clks IMX6QDL_CLK_ENET>,
+		 <&clks IMX6QDL_CLK_ENET_REF>;
+	phy-mode = "rmii";
+	status = "okay";
+};

2.7.4

From: Jacopo Mondi <[email protected]>

The "EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation" is based on the 1.5 version of the i.Core MX6 cpu module. The 1.5 version differs from the original one for a few details, including the ethernet PHY interface clock provider.

With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver

While before using the 1.5 version, ethernet failed to startup do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY

---
 arch/arm/boot/dts/imx6q-icore-mipi.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 95b2efd..1f15882 100644
@@ -8,10 +8,10 @@
 /dts-v1/;
 
 #include "imx6q.dtsi"
-#include "imx6qdl-icore.dtsi"
+#include "imx6qdl-icore-1.5.dtsi"
 
 / {
-	model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
+	model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit";
 	compatible = "engicam,imx6-icore", "fsl,imx6q";
 };
 

2.7.4

Applied both, thanks.