arm64: dts: add support for SolidRun Clearfog GT 8K
Subsystems (2)
PATCH 1/1 arm64: dts: add support for SolidRun Clearfog GT 8K
The SolidRun Clearfog GT-8K is based on Marvell Armada 8040 SoC.
https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k
The following devices were tested with this DT on top of kernel v4.19-rc1:
* 1GB Ethernet WAN
* 4 ports 1GB Ethernet switch (2.5GB uplink)
* USB3 type A port
* SD card and eMMC
* 2 LEDs
* 2 push buttons
--- arch/arm64/boot/dts/marvell/Makefile | 1 + .../marvell/armada-8040-clearfog-gt-8k.dts | 417 ++++++++++++++++++ 2 files changed, 418 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
arch/arm64/boot/dts/marvell/Makefile +1 -0
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +417 -0
417 lines not on this page · raw message
Signature · 1 line
2.18.0
Andrew Lunn
maintainerPATCH 1/1 arm64: dts: add support for SolidRun Clearfog GT 8K
On Wed, Aug 29, 2018 at 03:13:09PM +0300, Baruch Siach wrote:
Hi Baruch
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 74
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +7
-0+ leds { + compatible = "gpio-leds"; + pinctrl-0 = <&cp0_led0_pins + &cp0_led1_pins>; + pinctrl-names = "default"; + led0 { + label = "led0";
There is a naming convention of LEDs. Documentation/leds/leds-class.txt:
LED Device Naming
=================
Is currently of the form:
"devicename:colour:function"
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 96
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +7
-0+ button_0 { + /* The rear button */ + label = "Rear Button"; + gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_0>; + };
Is there any label on the PCB or case about what this button is used for? It would be nice to have something less generic than BTN_0.
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 103
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +7
-0+ + button_1 { + /* The wps button */ + label = "WPS Button"; + gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_1>;
linux,code = <KEY_WPS_BUTTON>;
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 226
Quoted 4 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +4
-0+ cp0_tpm_irq_pins: tpm-irq-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + };
I didn't realise the board had a TPM. I don't see any mention on SolidRun's website. What TPM is it?
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 314
Quoted 7 lines
+&cp1_mdio {
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +6
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cp1_ge_mdio_pins>; + status = "okay"; + + ge_phy: ethernet-phy at 0 { + marvell,reg-init = <3 16 0 0x1017>;
This marvell,reg-init is rather black magic. It would be good to document what this does.
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 357
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +5
-0+ port at 5 { + reg = <5>; + label = "cpu"; + ethernet = <&cp1_eth2>; + };
No fixed-link? It correctly defaults to 2.5G? I've never tested that.
Andrew
PATCH 1/1 arm64: dts: add support for SolidRun Clearfog GT 8K
Hi Andrew,
Thanks for reviewing.
Quoted 18 lines · Andrew Lunn
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 74
Quoted 7 lines · Baruch Siach
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +7
-0+ leds { + compatible = "gpio-leds"; + pinctrl-0 = <&cp0_led0_pins + &cp0_led1_pins>; + pinctrl-names = "default"; + led0 { + label = "led0";There is a naming convention of LEDs.
Documentation/leds/leds-class.txt:LED Device Naming
=================Is currently of the form:
"devicename:colour:function"
Quoted 10 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 96
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +7
-0+ button_0 { + /* The rear button */ + label = "Rear Button"; + gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_0>; + };Is there any label on the PCB or case about what this button is used for? It would be nice to have something less generic than
BTN_0.
The schematics say "AP Reset Switch". So it is probably meant to be a software controlled "back to default" button. Is there a suitable linux,code for that?
Quoted 10 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 103
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +7
-0+ + button_1 { + /* The wps button */ + label = "WPS Button"; + gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = <BTN_1>;linux,code = <
KEY_WPS_BUTTON>;
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 226
Quoted 4 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +4
-0+ cp0_tpm_irq_pins: tpm-irq-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + };I didn't realise the board had a TPM. I don't see any mention on SolidRun's website. What TPM is it?
It is not assembled here so I could not test. The schematics say SLB9670.
Quoted 10 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 314
Quoted 7 lines
+&cp1_mdio {
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +6
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cp1_ge_mdio_pins>; + status = "okay"; + + ge_phy: ethernet-phy at 0 { + marvell,reg-init = <3 16 0 0x1017>;This marvell,reg-init is rather black magic. It would be good to document what this does.
OK. I'll look in up.
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 357
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +5
-0+ port at 5 { + reg = <5>; + label = "cpu"; + ethernet = <&cp1_eth2>; + };No fixed-link? It correctly defaults to 2.5G? I've never tested that.
Seems to work here. There is also a patch from Rabeeh (which I did not apply while testing) to make it the default:
I plan to upstream this patch.
baruch
Signature · 3 lines
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -Andrew Lunn
maintainerPATCH 1/1 arm64: dts: add support for SolidRun Clearfog GT 8K
Quoted 3 lines
The schematics say "AP Reset Switch". So it is probably meant to be a software controlled "back to default" button. Is there a suitable linux,code for that?
There is a reset code.
Quoted 1 line
It is not assembled here so I could not test. The schematics say SLB9670.
I think the standard SPI TPM TIS driver should work for that. But if it is not populated, you cannot test it.
Quoted 9 lines
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 357
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +5
-0+ port at 5 { + reg = <5>; + label = "cpu"; + ethernet = <&cp1_eth2>; + };No fixed-link? It correctly defaults to 2.5G? I've never tested that.
Seems to work here
It would be good to test it really is using 2.5G, not 1G.
. There is also a patch from Rabeeh (which I did not
Quoted 3 lines
apply while testing) to make it the default:
Which is why i don't think it actually is using 2.5G.
This patch will need a little rework, but it basically O.K. Change mv88e6x41 to mv88e6341. We use the family name in function names.
Andrew
PATCH 1/1 arm64: dts: add support for SolidRun Clearfog GT 8K
Hi Andrew,
Quoted 5 lines · Andrew Lunn
Quoted 3 lines
The schematics say "AP Reset Switch". So it is probably meant to be a software controlled "back to default" button. Is there a suitable linux,code for that?
There is a reset code.
I can't find it. The only match for RESET in include/uapi/linux/input-event-codes.h is KEY_ZOOMRESET, which is most likely not what you meant.
Quoted 15 lines
Quoted 1 line
It is not assembled here so I could not test. The schematics say SLB9670.
I think the standard SPI TPM TIS driver should work for that. But if it is not populated, you cannot test it.
Quoted 9 lines
Quoted 7 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts line 357
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts new file +5
-0+ port at 5 { + reg = <5>; + label = "cpu"; + ethernet = <&cp1_eth2>; + };No fixed-link? It correctly defaults to 2.5G? I've never tested that.
Seems to work here
Quoted 8 lines
It would be good to test it really is using 2.5G, not 1G.
Quoted 4 lines
There is also a patch from Rabeeh (which I did not apply while testing) to make it the default:
Which is why i don't think it actually is using 2.5G.
I see this from phylink_mac_config():
[ 511.043783] mvpp2 f4000000.ethernet eth2: phylink_mac_config: mode=fixed/2500base-x/2.5Gbps/Full adv=00000,00008200 pause=10 link=1 an=1
Is that enough for a test?
Quoted 2 lines
This patch will need a little rework, but it basically O.K. Change mv88e6x41 to mv88e6341. We use the family name in function names.
Thanks again for reviewing this not-yet-posted patch.
baruch
Signature · 3 lines
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -Andrew Lunn
maintainerPATCH 1/1 arm64: dts: add support for SolidRun Clearfog GT 8K
Quoted 5 lines
I see this from
phylink_mac_config():[ 511.043783] mvpp2 f4000000.ethernet eth2: phylink_mac_config: mode=fixed/2500base-x/2.5Gbps/Full adv=00000,00008200 pause=10 link=1 an=1Is that enough for a test?
That shows you what the mvpp2 is being asked to do. But not what the switch is doing. It could be the two SERDES interfaces are doing auto-neg, and ended up at 1G.
Try actually pushing traffic over the switch. Two iperf instances, out two ports. Do you get 1Gbps for each stream or 500Mbps?
In the end, it does not matter. We want the CPU port of the switch to default to its maximum speed. So you should not need a fixed-link. But until the patch is applied, i don't think it will do > 1Gbps.
Andrew