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LP1/LP2 suspend-resume CPU clock fixes for Tegra30

PATCH In review Dmitry Osipenko 1 participant 4 messages Aug 30, 2018 – Oct 15, 2018

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#0 lore raw

cover LP1/LP2 suspend-resume CPU clock fixes for Tegra30

Hello,

This patch-series fixes CPU hanging after suspend-resume / LP2 cpuidle on Tegra30. The bug really appears during stress-testing, like frequent suspending under variable load + the upcoming Tegra30 CPUFREQ driver.

Dmitry Osipenko (2):
ARM: tegra: Switch CPU to PLLP before powergating on Tegra30
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30

 arch/arm/mach-tegra/sleep-tegra30.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
Signature · 1 line
2.18.0
#1 lore raw

PATCH 1/2 ARM: tegra: Switch CPU to PLLP before powergating on Tegra30

PLLX is getting turned by the HW logic when CPU enters powergated state and there is no enough time for PLLX to re-lock on exiting the low-power state, this causes memory errors coming from misbehaving CPU and eventual hanging of the system.

---
 arch/arm/mach-tegra/sleep-tegra30.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-tegra/sleep-tegra30.S +1 -1
index dd4a67dabd91..d572d4b860be 100644
@@ -298,8 +298,8 @@ ENDPROC(tegra30_sleep_cpu_secondary_finish)
  * Switches the CPU to enter sleep.
  */
 ENTRY(tegra30_tear_down_cpu)
+	bl	tegra_switch_cpu_to_pllp
 	mov32	r6, TEGRA_FLOW_CTRL_BASE
-
 	b	tegra30_enter_sleep
 ENDPROC(tegra30_tear_down_cpu)
 
Signature · 1 line
2.18.0
#2 lore raw

PATCH 2/2 ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30

In reply to Dmitry Osipenko

The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX could be even disabled if CPU entered suspend on PLLP, it the case if CPUFREQ driver is active. The actual PLLX configuration and burst policy shall be restored by the clock driver.

---
 arch/arm/mach-tegra/sleep-tegra30.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-tegra/sleep-tegra30.S +2 -2
index d572d4b860be..127fc78365fe 100644
@@ -396,8 +396,8 @@ _pll_m_c_x_done:
 	str	r4, [r0, #CLK_RESET_SCLK_BURST]
 
 	cmp	r10, #TEGRA30
-	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX
-	movteq	r4, #:upper16:((1 << 28) | (0x8))
+	movweq	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
+	movteq	r4, #:upper16:((1 << 28) | (0x4))
 	movwne	r4, #:lower16:((1 << 28) | (0xe))
 	movtne	r4, #:upper16:((1 << 28) | (0xe))
 	str	r4, [r0, #CLK_RESET_CCLK_BURST]
Signature · 1 line
2.18.0
#3 lore raw
In reply to Dmitry Osipenko
Quoted 6 lines · Dmitry Osipenko

Hello,

This patch-series fixes CPU hanging after suspend-resume / LP2 cpuidle on Tegra30. The bug really appears during stress-testing, like frequent suspending under variable load + the upcoming Tegra30 CPUFREQ driver.

Quoted 7 lines

Dmitry Osipenko (2):
ARM: tegra: Switch CPU to PLLP before powergating on Tegra30
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30

 arch/arm/mach-tegra/sleep-tegra30.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

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