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clk: tegra: Return the exact clock rate from clk_round_rate

PATCH Applied Robert Yang 4 participants 5 messages Sep 25, 2018 – Dec 10, 2018

Subsystems (3)
Common clk Tegra architecture support Tegra clock driver
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Robert Yang

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#0 lore raw

PATCH v2 1/1 clk: tegra: Return the exact clock rate from clk_round_rate

The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.

Signed-off-by Robert Yang <[email protected]>

---
Changes in V2:
- Move input divider (m == 0) check into the cfg constraints check condition. Forgo adding WARN_ON and avoid using 0 input divider all together.

 drivers/clk/tegra/clk-pll.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
drivers/clk/tegra/clk-pll.c +4 -3
index 17a058c3bbc1..2a800a9c56e6 100644
@@ -589,12 +589,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 	cfg->n = cfg->output_rate / cfreq;
 	cfg->cpcon = OUT_OF_TABLE_CPCON;
 
-	if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
-	    (1 << p_div) > divp_max(pll)
-	    || cfg->output_rate > pll->params->vco_max) {
+	if (cfg->m == 0 || cfg->m > divm_max(pll) ||
+	    cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
+	    cfg->output_rate > pll->params->vco_max) {
 		return -EINVAL;
 	}
 
+	cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
 	cfg->output_rate >>= p_div;
 
 	if (pll->params->pdiv_tohw) {
Signature · 1 line
2.17.1
maintainer
#1 lore raw

Quoting Robert Yang (2018-09-25 14:49:40)

Quoted 6 lines

The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.

Signed-off-by Robert Yang <[email protected]>

---

I'm waiting for someone from Nvidia/Tegra background to review this change.

Reviewed-by Tested-by
#2 lore raw
Quoted 11 lines · Stephen Boyd

Quoting Robert Yang (2018-09-25 14:49:40)

Quoted 6 lines

The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.

Signed-off-by Robert Yang <[email protected]>

---

I'm waiting for someone from Nvidia/Tegra background to review this change.

Apparently Peter is taking a pause. I think Thierry's ACK to V1 should be still valid here.

Also, if this helps:

Reviewed-by Dmitry Osipenko <[email protected]>
Tested-by Dmitry Osipenko <[email protected]>
Acked-by on v2 1/1
#3 lore raw
In reply to Robert Yang
Quoted 5 lines · Robert Yang

The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.

Signed-off-by Robert Yang <[email protected]>
Quoted 8 lines

---
Changes in V2:
- Move input divider (m == 0) check into the cfg constraints check condition. Forgo adding WARN_ON and avoid using 0 input divider all together.

 drivers/clk/tegra/clk-pll.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
Acked-by Thierry Reding <[email protected]>
maintainer Applied
#4 lore raw
In reply to Robert Yang

Quoting Robert Yang (2018-09-25 14:49:40)

Quoted 6 lines

The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.

Signed-off-by Robert Yang <[email protected]>

---

Applied to clk-next