MIPS: Lexra LX5280 CPU + Realtek RTL8186 SoC support

Hi,

Changelog:

v2:
- Patch 5 in v1 added irqchip, timer and arch code for the SoC all in one patch. Split this patch into 3 patches:
- Patch 3 for irqchip (depends on MACH_RTL8186 in Kconfig)
- Patch 5 for timer (depends on MACH_RTL8186 in Kconfig)
- Patch 7 for SoC code in arch/mips (adds MACH_RTL8186 in mips and selects irqchip+timer drivers)
Also, reorder the patches in a way that each DT binding patch comes before
the respective driver patch.

- No code changes from v1

------

This RFC patch series adds all the necessary code to successfully boot Linux on the Realtek RTL8186 SoC.

Boot log with the v1 series applied (+one DT patch that adds partitions) is available here:
https://gist.github.com/yashac3/483decfa8db014edfb055ba5a1f9996e

Network drivers and other misc drivers are not included in this patch set, but are being worked on.

This patch series includes:
- Patch 1: Lexra LX5280 CPU support (MIPS)

- Patch 2: Device tree bindings for the RTL8186 interrupt controller
- Patch 3: RTL8186 interrupt controller driver

- Patch 4: Device tree bindings for the RTL8186 timer
- Patch 5: RTL8186 timer driver

- Patch 6: Device tree bindings for Realtek MIPS SoCs
- Patch 7: RTL8186 SoC support (MIPS, device tree)

What's still missing:
1) Upstream toolchain support for the Lexra LX5280 CPU. (Still WIP) GCC and binutils patches are available at [1][2]. Buildroot with these patches applied is available at [3].

The toolchain work is still WIP and I'm planning to send it for review when it will be ready.

Still, feel free to comment on this work too.

2) Reading the TLB size from device tree:
(The reason there's no DT bindings for the LX5280 in this series)

As there's no way to get the TLB size from the hardware, is must be passed in the DT.

Currently in arch/mips, the FDT is not available in the cpu_probe() stage, where the 'tlbsize' field of the cpu data is set.

Any ideas/suggestions on how to solve that?

This patch series is on top of v4.18 + 5 prerequisite patches that are in mips-next for 4.20. [4][5].

This patch series is also available at:
https://github.com/yashac3/linux-rtl8186/commits/rtl8186-porting-for-upstream-4.18-v2

Please review.

Thanks,
Yasha

[1] https://github.com/yashac3/gcc/commits/lx5280-gcc-8_2_0
[2] https://github.com/yashac3/binutils-gdb/commits/lx5280-porting-master
[3] https://github.com/yashac3/buildroot/commits/lx5280_master
[4] https://www.linux-mips.org/archives/linux-mips/2018-09/msg00769.html
[5] https://www.linux-mips.org/archives/linux-mips/2018-09/msg00775.html

Yasha Cherikovsky (7):
MIPS: Add support for the Lexra LX5280 CPU
dt-binding: interrupt-controller: Document RTL8186 SoC DT bindings irqchip/rtl8186: Add RTL8186 interrupt controller driver
dt-binding: timer: Document RTL8186 SoC DT bindings clocksource/drivers/rtl8186: Add RTL8186 timer driver
dt-binding: mips: Document Realtek SoC DT bindings
MIPS: Add Realtek RTL8186 SoC support

 .../interrupt-controller/realtek,rtl8186-intc |  18 ++
 .../devicetree/bindings/mips/realtek.txt      |   9 +
 .../bindings/timer/realtek,rtl8186-timer.txt  |  17 ++
 arch/mips/Kbuild.platforms                    |   1 +
 arch/mips/Kconfig                             |  47 +++-
 arch/mips/Makefile                            |   1 +
 arch/mips/boot/compressed/uart-16550.c        |   5 +
 arch/mips/boot/dts/Makefile                   |   1 +
 arch/mips/boot/dts/realtek/Makefile           |   4 +
 arch/mips/boot/dts/realtek/rtl8186.dtsi       |  86 ++++++
 .../dts/realtek/rtl8186_edimax_br_6204wg.dts  |  45 ++++
 arch/mips/configs/rtl8186_defconfig           | 112 ++++++++
 arch/mips/include/asm/cpu-features.h          |   3 +
 arch/mips/include/asm/cpu-type.h              |   4 +
 arch/mips/include/asm/cpu.h                   |   9 +
 arch/mips/include/asm/isadep.h                |   3 +-
 arch/mips/include/asm/mach-rtl8186/rtl8186.h  |  37 +++
 arch/mips/include/asm/mipsregs.h              |  10 +
 arch/mips/include/asm/module.h                |   2 +
 arch/mips/include/asm/pgtable-32.h            |   7 +-
 arch/mips/include/asm/pgtable-bits.h          |   9 +-
 arch/mips/include/asm/pgtable.h               |   6 +-
 arch/mips/include/asm/stackframe.h            |   9 +-
 arch/mips/include/asm/traps.h                 |   2 +
 arch/mips/kernel/Makefile                     |   2 +
 arch/mips/kernel/cpu-probe.c                  |   6 +
 arch/mips/kernel/entry.S                      |   3 +-
 arch/mips/kernel/genex.S                      |   6 +-
 arch/mips/kernel/idle.c                       |  10 +
 arch/mips/kernel/process.c                    |   3 +-
 arch/mips/kernel/traps.c                      |  42 +++
 arch/mips/lib/Makefile                        |   1 +
 arch/mips/mm/Makefile                         |   1 +
 arch/mips/mm/c-lx5280.c                       | 251 ++++++++++++++++++
 arch/mips/mm/cache.c                          |   6 +
 arch/mips/mm/fault.c                          |   4 +
 arch/mips/mm/tlbex.c                          |   1 +
 arch/mips/rtl8186/Makefile                    |   2 +
 arch/mips/rtl8186/Platform                    |   7 +
 arch/mips/rtl8186/irq.c                       |   8 +
 arch/mips/rtl8186/prom.c                      |  15 ++
 arch/mips/rtl8186/setup.c                     |  80 ++++++
 arch/mips/rtl8186/time.c                      |  10 +
 drivers/clocksource/Kconfig                   |   9 +
 drivers/clocksource/Makefile                  |   1 +
 drivers/clocksource/timer-rtl8186.c           | 220 +++++++++++++++
 drivers/irqchip/Kconfig                       |   5 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-rtl8186.c                 | 107 ++++++++
 49 files changed, 1225 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtl8186-intc
 create mode 100644 Documentation/devicetree/bindings/mips/realtek.txt
 create mode 100644 Documentation/devicetree/bindings/timer/realtek,rtl8186-timer.txt
 create mode 100644 arch/mips/boot/dts/realtek/Makefile
 create mode 100644 arch/mips/boot/dts/realtek/rtl8186.dtsi
 create mode 100644 arch/mips/boot/dts/realtek/rtl8186_edimax_br_6204wg.dts
 create mode 100644 arch/mips/configs/rtl8186_defconfig
 create mode 100644 arch/mips/include/asm/mach-rtl8186/rtl8186.h
 create mode 100644 arch/mips/mm/c-lx5280.c
 create mode 100644 arch/mips/rtl8186/Makefile
 create mode 100644 arch/mips/rtl8186/Platform
 create mode 100644 arch/mips/rtl8186/irq.c
 create mode 100644 arch/mips/rtl8186/prom.c
 create mode 100644 arch/mips/rtl8186/setup.c
 create mode 100644 arch/mips/rtl8186/time.c
 create mode 100644 drivers/clocksource/timer-rtl8186.c
 create mode 100644 drivers/irqchip/irq-rtl8186.c

2.19.0

The Lexra LX5280 CPU [1][2] implements the MIPS-I ISA, without unaligned load/store instructions (lwl, lwr, swl, swr). The programming model of this CPU is very similar
to the R3000 programming model, with a few differences.

The Realtek RTL8186 SoC has this CPU, so this patch is required for future RTL8186 SoC support.

The LX5280 CPU has no documented TLB unit (only SMMU, a simple MMU unit which is not enough for usual Linux).
However, the RTL8186 SoC does include a TLB unit with the CPU (programmed like R3000 TLB).

So this patch adds support *only* for LX5280s that have a TLB unit.

This patch includes:
- Adding Kconfig entries for LX5280
- Adding CPU_LX5280 to the cpu_type_enum
- Passing -march=lx5280 to the compiler
- Using existing R3000 code/behavior where possible
- Wait instruction support (for better idle power consuption)
- RDHWR instruction emulation from the page fault handler (more details in a code comment)

[1] https://www.linux-mips.org/wiki/Lexra
[2] https://wikidevi.com/wiki/Lexra_LX5280

---
 arch/mips/Kconfig                    |  30 +++-
 arch/mips/Makefile                   |   1 +
 arch/mips/include/asm/cpu-features.h |   3 +
 arch/mips/include/asm/cpu-type.h     |   4 +
 arch/mips/include/asm/cpu.h          |   9 +
 arch/mips/include/asm/isadep.h       |   3 +-
 arch/mips/include/asm/mipsregs.h     |  10 ++
 arch/mips/include/asm/module.h       |   2 +
 arch/mips/include/asm/pgtable-32.h   |   7 +-
 arch/mips/include/asm/pgtable-bits.h |   9 +-
 arch/mips/include/asm/pgtable.h      |   6 +-
 arch/mips/include/asm/stackframe.h   |   9 +-
 arch/mips/include/asm/traps.h        |   2 +
 arch/mips/kernel/Makefile            |   2 +
 arch/mips/kernel/cpu-probe.c         |   6 +
 arch/mips/kernel/entry.S             |   3 +-
 arch/mips/kernel/genex.S             |   6 +-
 arch/mips/kernel/idle.c              |  10 ++
 arch/mips/kernel/process.c           |   3 +-
 arch/mips/kernel/traps.c             |  42 +++++
 arch/mips/lib/Makefile               |   1 +
 arch/mips/mm/Makefile                |   1 +
 arch/mips/mm/c-lx5280.c              | 251 +++++++++++++++++++++++++++
 arch/mips/mm/cache.c                 |   6 +
 arch/mips/mm/fault.c                 |   4 +
 arch/mips/mm/tlbex.c                 |   1 +
 26 files changed, 408 insertions(+), 23 deletions(-)
 create mode 100644 arch/mips/mm/c-lx5280.c

index a6b0391996ea..bbeabd6b0a80 100644
@@ -1558,6 +1558,17 @@ config CPU_R3000
 	  might be a safe bet.  If the resulting kernel does not work,
 	  try to recompile with R3000.
 
+config CPU_LX5280
+	bool "LX5280"
+	depends on SYS_HAS_CPU_LX5280
+	select CPU_SUPPORTS_32BIT_KERNEL
+	help
+	  Choose this option to build a kernel for the Lexra LX5280 CPU.
+	  Lexra LX5280 implements the MIPS-I instruction set, without
+	  unaligned load and store instructions (lwl, lwr, swl, swr).
+	  Only LX5280 CPUs with a TLB unit are supported.
+
+
 config CPU_TX39XX
 	bool "R39XX"
 	depends on SYS_HAS_CPU_TX39XX

@@ -1939,6 +1950,9 @@ config SYS_HAS_CPU_R3000
 config SYS_HAS_CPU_TX39XX
 	bool
 
+config SYS_HAS_CPU_LX5280
+	bool
+
 config SYS_HAS_CPU_VR41XX
 	bool
 

@@ -2169,7 +2183,7 @@ config PAGE_SIZE_8KB
 
 config PAGE_SIZE_16KB
 	bool "16kB"
-	depends on !CPU_R3000 && !CPU_TX39XX
+	depends on !CPU_R3000 && !CPU_TX39XX && !CPU_LX5280
 	help
 	  Using 16kB page size will result in higher performance kernel at
 	  the price of higher memory consumption.  This option is available on

@@ -2188,7 +2202,7 @@ config PAGE_SIZE_32KB
 
 config PAGE_SIZE_64KB
 	bool "64kB"
-	depends on !CPU_R3000 && !CPU_TX39XX
+	depends on !CPU_R3000 && !CPU_TX39XX && !CPU_LX5280
 	help
 	  Using 64kB page size will result in higher performance kernel at
 	  the price of higher memory consumption.  This option is available on

@@ -2256,15 +2270,15 @@ config CPU_HAS_PREFETCH
 
 config CPU_GENERIC_DUMP_TLB
 	bool
-	default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
+	default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX || CPU_LX5280)
 
 config CPU_R4K_FPU
 	bool
-	default y if !(CPU_R3000 || CPU_TX39XX)
+	default y if !(CPU_R3000 || CPU_TX39XX || CPU_LX5280)
 
 config CPU_R4K_CACHE_TLB
 	bool
-	default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
+	default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON || CPU_LX5280)
 
 config MIPS_MT_SMP
 	bool "MIPS MT SMP support (1 TC on each available VPE)"

@@ -2501,7 +2515,7 @@ config CPU_MIPSR2_IRQ_EI
 
 config CPU_HAS_SYNC
 	bool
-	depends on !CPU_R3000
+	depends on !(CPU_R3000 || CPU_LX5280)
 	default y
 
 #

@@ -2519,14 +2533,14 @@ config CPU_R4400_WORKAROUNDS
 
 config MIPS_ASID_SHIFT
 	int
-	default 6 if CPU_R3000 || CPU_TX39XX
+	default 6 if CPU_R3000 || CPU_TX39XX || CPU_LX5280
 	default 4 if CPU_R8000
 	default 0
 
 config MIPS_ASID_BITS
 	int
 	default 0 if MIPS_ASID_BITS_VARIABLE
-	default 6 if CPU_R3000 || CPU_TX39XX
+	default 6 if CPU_R3000 || CPU_TX39XX || CPU_LX5280
 	default 8
 
 config MIPS_ASID_BITS_VARIABLE

index e2122cca4ae2..293403f38ffe 100644
@@ -151,6 +151,7 @@ cflags-y += -fno-stack-check
 #
 cflags-$(CONFIG_CPU_R3000)	+= -march=r3000
 cflags-$(CONFIG_CPU_TX39XX)	+= -march=r3900
+cflags-$(CONFIG_CPU_LX5280)	+= -march=lx5280
 cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap

index 9cdb4e4ce258..118e0ff4b54a 100644
@@ -75,6 +75,9 @@
 #ifndef cpu_has_octeon_cache
 #define cpu_has_octeon_cache	0
 #endif
+#ifndef cpu_has_lx5280_cache
+#define cpu_has_lx5280_cache	(cpu_data[0].options & MIPS_CPU_LX5280_CACHE)
+#endif
 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
 #ifndef cpu_has_fpu
 #define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)

index a45af3de075d..bd837232196d 100644
@@ -105,6 +105,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 	case CPU_TX3927:
 #endif
 
+#ifdef CONFIG_SYS_HAS_CPU_LX5280
+	case CPU_LX5280:
+#endif
+
 #ifdef CONFIG_SYS_HAS_CPU_VR41XX
 	case CPU_VR41XX:
 	case CPU_VR4111:

index 5b9d02ef4f60..970a263b52d9 100644
@@ -90,6 +90,7 @@
 #define PRID_IMP_R5432		0x5400
 #define PRID_IMP_R5500		0x5500
 #define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */
+#define PRID_IMP_LX5280		0xC600
 
 #define PRID_IMP_UNKNOWN	0xff00
 

@@ -306,6 +307,11 @@ enum cpu_type_enum {
 	 */
 	CPU_TX3912, CPU_TX3922, CPU_TX3927,
 
+	/*
+	 * Lexra processors
+	 */
+	CPU_LX5280,
+
 	/*
 	 * MIPS32 class processors
 	 */

@@ -420,6 +426,9 @@ enum cpu_type_enum {
 				MBIT_ULL(55)	/* CPU shares FTLB entries with another */
 #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
 				MBIT_ULL(56)	/* CPU has perf counters implemented per TC (MIPSMT ASE) */
+#define MIPS_CPU_LX5280_CACHE \
+				MBIT_ULL(57)
+
 
 /*
  * CPU ASE encodings

index d1683202399b..e725bec9a8ab 100644
@@ -10,7 +10,8 @@
 #ifndef __ASM_ISADEP_H
 #define __ASM_ISADEP_H
 
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 /*
  * R2000 or R3000
  */

index ae461d91cd1f..d3d025d08f3d 100644
@@ -81,6 +81,7 @@
 #define CP0_WATCHLO $18
 #define CP0_WATCHHI $19
 #define CP0_XCONTEXT $20
+#define CP0_LX5280_CCTL $20
 #define CP0_FRAMEMASK $21
 #define CP0_DIAGNOSTIC $22
 #define CP0_DEBUG $23

@@ -562,6 +563,12 @@
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 
+/* Bits specific to the Lexra LX5280 CPU. */
+#define LX5280_CCTL_DINVAL		(_ULCAST_(1) << 0)
+#define LX5280_CCTL_IINVAL		(_ULCAST_(1) << 1)
+#define LX5280_CCTL_IMEMFILL		(_ULCAST_(1) << 4)
+#define LX5280_CCTL_IMEMOFF		(_ULCAST_(1) << 5)
+
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */

@@ -1725,6 +1732,9 @@ do {									\
 #define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
 #define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
 
+#define read_c0_lx5280_cctl()	__read_ulong_c0_register($20, 0)
+#define write_c0_lx5280_cctl(val)	__write_ulong_c0_register($20, 0, val)
+
 #define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 

index 6dc0b21b8acd..8547620e20b1 100644
@@ -137,6 +137,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "XLR "
 #elif defined CONFIG_CPU_XLP
 #define MODULE_PROC_FAMILY "XLP "
+#elif defined CONFIG_CPU_LX5280
+#define MODULE_PROC_FAMILY "LX5280 "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif

index 74afe8c76bdd..54000c0dc56e 100644
@@ -175,7 +175,8 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 #define pte_unmap(pte) ((void)(pte))
 
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 
 /* Swap entries must have VALID bit cleared. */
 #define __swp_type(x)			(((x).val >> 10) & 0x1f)

@@ -220,6 +221,8 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
 
 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
 
-#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
+#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	* defined(CONFIG_CPU_LX5280)
+	*/
 
 #endif /* _ASM_PGTABLE_32_H */

index f88a48cd68b2..75bb141f308d 100644
@@ -80,7 +80,8 @@ enum pgtable_bits {
 	_PAGE_MODIFIED_SHIFT,
 };
 
-#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 
 /* Page table bits used for r3k systems */
 enum pgtable_bits {

@@ -146,7 +147,8 @@ enum pgtable_bits {
 #define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
 #define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
 #define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 # define _CACHE_UNCACHED	(1 << _CACHE_UNCACHED_SHIFT)
 # define _CACHE_MASK		_CACHE_UNCACHED
 # define _PFN_SHIFT		PAGE_SHIFT

@@ -204,7 +206,8 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 /*
  * Cache attributes
  */
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 
 #define _CACHE_CACHABLE_NONCOHERENT 0
 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED

index 129e0328367f..688ac35441ab 100644
@@ -197,7 +197,8 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
 static inline void set_pte(pte_t *ptep, pte_t pteval)
 {
 	*ptep = pteval;
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) && \
+	!defined(CONFIG_CPU_LX5280)
 	if (pte_val(pteval) & _PAGE_GLOBAL) {
 		pte_t *buddy = ptep_buddy(ptep);
 		/*

@@ -256,7 +257,8 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
 	htw_stop();
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) && \
+	!defined(CONFIG_CPU_LX5280)
 	/* Preserve global status for the pair */
 	if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
 		set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));

index 2161357cc68f..698e635f7afc 100644
@@ -42,7 +42,8 @@
 	cfi_restore \reg \offset \docfi
 	.endm
 
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 #define STATMASK 0x3f
 #else
 #define STATMASK 0x1f

@@ -349,7 +350,8 @@
 		cfi_ld	sp, PT_R29, \docfi
 		.endm
 
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 
 		.macro	RESTORE_SOME docfi=0
 		.set	push

@@ -477,7 +479,8 @@
 		.macro	KMODE
 		mfc0	t0, CP0_STATUS
 		li	t1, ST0_CU0 | (STATMASK & ~1)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 		andi	t2, t0, ST0_IEP
 		srl	t2, 2
 		or	t0, t2

index f41cf3ee82a7..e611a3d0ac99 100644
@@ -39,4 +39,6 @@ extern int register_nmi_notifier(struct notifier_block *nb);
 	register_nmi_notifier(&fn##_nb);				\
 })
 
+int simulate_rdhwr_in_page_fault(struct pt_regs *regs);
+
 #endif /* _ASM_TRAPS_H */

index f10e1e15e1c6..7fe3f3d4d4b4 100644
@@ -39,12 +39,14 @@ obj-$(CONFIG_FUNCTION_TRACER)	+= mcount.o ftrace.o
 sw-y				:= r4k_switch.o
 sw-$(CONFIG_CPU_R3000)		:= r2300_switch.o
 sw-$(CONFIG_CPU_TX39XX)		:= r2300_switch.o
+sw-$(CONFIG_CPU_LX5280)		:= r2300_switch.o
 sw-$(CONFIG_CPU_CAVIUM_OCTEON)	:= octeon_switch.o
 obj-y				+= $(sw-y)
 
 obj-$(CONFIG_CPU_R4K_FPU)	+= r4k_fpu.o
 obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o
 obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o
+obj-$(CONFIG_CPU_LX5280)	+= r2300_fpu.o
 
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_SMP_UP)		+= smp-up.o

index b2509c19cfb5..d7e39635fbe7 100644
@@ -1516,6 +1516,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 			break;
 		}
 
+		break;
+	case PRID_IMP_LX5280:
+		c->cputype = CPU_LX5280;
+		__cpu_name[cpu] = "Lexra LX5280";
+		c->options = MIPS_CPU_TLB | MIPS_CPU_LX5280_CACHE;
+		c->tlbsize = 16; // TODO Lexra: RTL8186 only. use dt?
 		break;
 	}
 }

index d7de8adcfcc8..ab4cb33020c5 100644
@@ -102,7 +102,8 @@ restore_partial:		# restore partial frame
 	SAVE_AT
 	SAVE_TEMP
 	LONG_L	v0, PT_STATUS(sp)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 	and	v0, ST0_IEP
 #else
 	and	v0, ST0_IE

index 37b9383eacd3..7d789e20e6ea 100644
@@ -165,7 +165,8 @@ NESTED(handle_int, PT_SIZE, sp)
 	.set	push
 	.set	noat
 	mfc0	k0, CP0_STATUS
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 	and	k0, ST0_IEP
 	bnez	k0, 1f
 

@@ -584,7 +585,8 @@ isrdhwr:
 	get_saved_sp	/* k1 := current_thread_info */
 	.set	noreorder
 	MFC0	k0, CP0_EPC
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 	ori	k1, _THREAD_MASK
 	xori	k1, _THREAD_MASK
 	LONG_L	v1, TI_TP_VALUE(k1)

index 7c246b69c545..336d1498a175 100644
@@ -115,6 +115,13 @@ static void au1k_wait(void)
 	: : "r" (au1k_wait), "r" (c0status));
 }
 
+static void lx5280_wait(void)
+{
+	/* Execute LX5280 'sleep' instruction */
+	asm volatile(".word 0x42000038");
+	local_irq_enable();
+}
+
 static int __initdata nowait;
 
 static int __init wait_disable(char *s)

@@ -249,6 +256,9 @@ void __init check_wait(void)
 		   cpu_wait = r4k_wait;
 		 */
 		break;
+	case CPU_LX5280:
+		cpu_wait = lx5280_wait;
+		break;
 	default:
 		break;
 	}

index 9670e70139fd..2f92f203dcd0 100644
@@ -138,7 +138,8 @@ int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
 		p->thread.reg17 = kthread_arg;
 		p->thread.reg29 = childksp;
 		p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) || \
+	defined(CONFIG_CPU_LX5280)
 		status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
 			 ((status & (ST0_KUC | ST0_IEC)) << 2);
 #else

index 6537e022ef62..7d44d11ed9bc 100644
@@ -14,6 +14,7 @@ lib-$(CONFIG_GENERIC_CSUM)	:= $(filter-out csum_partial.o, $(lib-y))
 obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o
 obj-$(CONFIG_CPU_R3000)		+= r3k_dump_tlb.o
 obj-$(CONFIG_CPU_TX39XX)	+= r3k_dump_tlb.o
+obj-$(CONFIG_CPU_LX5280)	+= r3k_dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
 obj-y += bswapsi.o bswapdi.o multi3.o

index c463bdad45c7..1b3e55c26012 100644
@@ -20,6 +20,7 @@ obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
 
 obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R3000)		+= c-r3k.o tlb-r3k.o
+obj-$(CONFIG_CPU_LX5280) 	+= c-lx5280.o tlb-r3k.o
 obj-$(CONFIG_CPU_R8000)		+= c-r4k.o cex-gen.o tlb-r8k.o
 obj-$(CONFIG_CPU_SB1)		+= c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)	+= c-tx39.o tlb-r3k.o

index 0d3c656feba0..873e62cfc821 100644
@@ -234,6 +234,12 @@ void cpu_cache_init(void)
 		octeon_cache_init();
 	}
 
+	if (cpu_has_lx5280_cache) {
+		extern void __weak lx5280_cache_init(void);
+
+		lx5280_cache_init();
+	}
+
 	setup_protection_map();
 }
 

index 5f71f2b903b7..159fd009f5bd 100644
@@ -26,6 +26,7 @@
 #include <asm/mmu_context.h>
 #include <asm/ptrace.h>
 #include <asm/highmem.h>		/* For VMALLOC_END */
+#include <asm/traps.h>
 #include <linux/kdebug.h>
 
 int show_unhandled_signals = 1;

@@ -204,6 +205,9 @@ static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write,
 bad_area_nosemaphore:
 	/* User mode accesses just cause a SIGSEGV */
 	if (user_mode(regs)) {
+		if (!simulate_rdhwr_in_page_fault(regs))
+			return;
+
 		tsk->thread.cp0_badvaddr = address;
 		tsk->thread.error_code = write;
 		if (show_unhandled_signals &&

index 79b9f2ad3ff5..95e745795724 100644
@@ -2616,6 +2616,7 @@ void build_tlb_refill_handler(void)
 	case CPU_TX3912:
 	case CPU_TX3922:
 	case CPU_TX3927:
+	case CPU_LX5280:
 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
 		if (cpu_has_local_ebase)
 			build_r3000_tlb_refill_handler();

2.19.0

I think you actually need to emulate these missing instructions for user
programs, so that the 32-bit MIPS psABI is supported and standard software can run unmodified. There'll be a performance hit and software will best be recompiled for the limited instruction set provided by actual hardware, however rebuilding is not always possible or feasible (also handcoded assembly may require actual reimplementation here and there).

The details are lacking I am afraid and I think it would be good to have
them provided for long-term support to be feasible.

First, the MIPS architecture does not have a single "page fault"
exception. There are three MMU exception codes defined: Mod, TLBL and TLBS, and also two vectors, either the TLB Refill or the General Exception. So please be specific which of those are taken by the LX5280 with the RDHWR instruction.

Second, please explain why this MMU exception happens, i.e. does the CPU
decode the SPECIAL3 major opcode as an I-Type memory access instruction, and then faults on `GPR[0] + offset' pointing to an unmapped page?

If documentation is publicly available this information can be inferred
from, then please provide a reference; otherwise please just describe the observed behaviour as you know it.

Maciej

This patch adds device tree binding doc for the
Realtek RTL8186 SoC interrupt controller.

---
 .../interrupt-controller/realtek,rtl8186-intc  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtl8186-intc

new file mode 100644
index 000000000000..21956d210021
@@ -0,0 +1,18 @@
+Realtek RTL8186 SoC interrupt controller
+
+Required properties:
+
+- compatible : should be "realtek,rtl8186-intc"
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+- reg : Specifies base physical address and size of the registers.
+
+Example:
+
+intc: interrupt-controller@1d010000 {
+	compatible = "realtek,rtl8186-intc";
+	interrupt-controller;
+	#interrupt-cells = <1>;
+	reg = <0x1d010000 0x8>;
+};

2.19.0

.txt

With that,

Thanks, will fix for v3.

The Realtek RTL8186 SoC is a MIPS based SoC
used in some home routers [1][2].

This adds a driver to handle the interrupt controller on this SoC.

[1] https://www.linux-mips.org/wiki/Realtek_SOC#Realtek_RTL8186
[2] https://wikidevi.com/wiki/Realtek_RTL8186

---
 drivers/irqchip/Kconfig       |   5 ++
 drivers/irqchip/Makefile      |   1 +
 drivers/irqchip/irq-rtl8186.c | 107 ++++++++++++++++++++++++++++++++++
 3 files changed, 113 insertions(+)
 create mode 100644 drivers/irqchip/irq-rtl8186.c

index e9233db16e03..83099905a871 100644
@@ -371,4 +371,9 @@ config QCOM_PDC
 	  Power Domain Controller driver to manage and configure wakeup
 	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
 
+config RTL8186_IRQ
+	bool
+	depends on MACH_RTL8186
+	select IRQ_DOMAIN
+
 endmenu

index 15f268f646bf..2e0bb859a8f4 100644
@@ -87,3 +87,4 @@ obj-$(CONFIG_MESON_IRQ_GPIO)		+= irq-meson-gpio.o
 obj-$(CONFIG_GOLDFISH_PIC) 		+= irq-goldfish-pic.o
 obj-$(CONFIG_NDS32)			+= irq-ativic32.o
 obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
+obj-$(CONFIG_RTL8186_IRQ)		+= irq-rtl8186.o

2.19.0

Please let me know how you want this to be merged once the rest of the series has been reviewed.

Thanks,

	M.

Jazz is not dead. It just smells funny...

This patch adds device tree binding doc for the
Realtek RTL8186 SoC timer controller.

---
 .../bindings/timer/realtek,rtl8186-timer.txt    | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/realtek,rtl8186-timer.txt

new file mode 100644
index 000000000000..eaa6292c16e0
@@ -0,0 +1,17 @@
+Realtek RTL8186 SoC timer
+
+Required properties:
+
+- compatible : Should be "realtek,rtl8186-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt number of the timer.
+- clocks: phandle to the source clock (usually a 22 MHz fixed clock)
+
+Example:
+
+timer {
+	compatible = "realtek,rtl8186-timer";
+	reg = <0x1d010050 0x30>;
+	interrupts = <0>;
+	clocks = <&sysclk>;
+};

2.19.0

The Realtek RTL8186 SoC is a MIPS based SoC
used in some home routers [1][2].

This adds a driver to handle the built-in timers
on this SoC.

Timers 0 and 1 are 24bit timers.
Timers 2 and 3 are 32bit timers.

Use Timer2 as clocksource and Timer3 for clockevents. Timer2 is also used for sched_clock.

[1] https://www.linux-mips.org/wiki/Realtek_SOC#Realtek_RTL8186
[2] https://wikidevi.com/wiki/Realtek_RTL8186

---
 drivers/clocksource/Kconfig         |   9 ++
 drivers/clocksource/Makefile        |   1 +
 drivers/clocksource/timer-rtl8186.c | 220 ++++++++++++++++++++++++++++
 3 files changed, 230 insertions(+)
 create mode 100644 drivers/clocksource/timer-rtl8186.c

index dec0dd88ec15..da87f73d0631 100644
@@ -609,4 +609,13 @@ config ATCPIT100_TIMER
 	help
 	  This option enables support for the Andestech ATCPIT100 timers.
 
+config RTL8186_TIMER
+	bool "RTL8186 timer driver"
+	depends on MACH_RTL8186
+	depends on COMMON_CLK
+	select TIMER_OF
+	select CLKSRC_MMIO
+	help
+	  Enables support for the RTL8186 timer driver.
+
 endmenu

index 00caf37e52f9..734e8566e1b6 100644
@@ -78,3 +78,4 @@ obj-$(CONFIG_H8300_TPU)			+= h8300_tpu.o
 obj-$(CONFIG_CLKSRC_ST_LPC)		+= clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP)		+= numachip.o
 obj-$(CONFIG_ATCPIT100_TIMER)		+= timer-atcpit100.o
+obj-$(CONFIG_RTL8186_TIMER)		+= timer-rtl8186.o

2.19.0

Hi Yasha,

except the few details below, the driver looks good to me.

 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

This patch adds device tree binding doc for Realtek MIPS SoCs.

It includes a compatible string for the Realtek RTL8186 SoC.

---
 Documentation/devicetree/bindings/mips/realtek.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/realtek.txt

new file mode 100644
index 000000000000..09d19758168a
@@ -0,0 +1,9 @@
+Realtek MIPS SoC device tree bindings
+
+1. SoCs
+
+Each device tree must specify a compatible value for the Realtek SoC
+it uses in the compatible property of the root node. The compatible
+value must be one of the following values:
+
+  realtek,rtl8186-soc

2.19.0

The Realtek RTL8186 SoC is a MIPS based SoC
used in some home routers [1][2].

The hardware includes Lexra LX5280 CPU with a TLB, two Ethernet controllers, a WLAN controller and more.

With this patch, it is possible to successfully boot the kernel and load userspace on the Edimax BR-6204Wg router.
Network drivers support will come in future patches.

This patch includes:
- New MIPS rtl8186 platform (mostly DT based)
- defconfig file
- MIPS zboot UART support
- Device tree files for the RTL8186 SoC and Edimax BR-6204Wg router

[1] https://www.linux-mips.org/wiki/Realtek_SOC#Realtek_RTL8186
[2] https://wikidevi.com/wiki/Realtek_RTL8186

---
 arch/mips/Kbuild.platforms                    |   1 +
 arch/mips/Kconfig                             |  17 +++
 arch/mips/boot/compressed/uart-16550.c        |   5 +
 arch/mips/boot/dts/Makefile                   |   1 +
 arch/mips/boot/dts/realtek/Makefile           |   4 +
 arch/mips/boot/dts/realtek/rtl8186.dtsi       |  86 ++++++++++++++
 .../dts/realtek/rtl8186_edimax_br_6204wg.dts  |  45 +++++++
 arch/mips/configs/rtl8186_defconfig           | 112 ++++++++++++++++++
 arch/mips/include/asm/mach-rtl8186/rtl8186.h  |  37 ++++++
 arch/mips/rtl8186/Makefile                    |   2 +
 arch/mips/rtl8186/Platform                    |   7 ++
 arch/mips/rtl8186/irq.c                       |   8 ++
 arch/mips/rtl8186/prom.c                      |  15 +++
 arch/mips/rtl8186/setup.c                     |  80 +++++++++++++
 arch/mips/rtl8186/time.c                      |  10 ++
 15 files changed, 430 insertions(+)
 create mode 100644 arch/mips/boot/dts/realtek/Makefile
 create mode 100644 arch/mips/boot/dts/realtek/rtl8186.dtsi
 create mode 100644 arch/mips/boot/dts/realtek/rtl8186_edimax_br_6204wg.dts
 create mode 100644 arch/mips/configs/rtl8186_defconfig
 create mode 100644 arch/mips/include/asm/mach-rtl8186/rtl8186.h
 create mode 100644 arch/mips/rtl8186/Makefile
 create mode 100644 arch/mips/rtl8186/Platform
 create mode 100644 arch/mips/rtl8186/irq.c
 create mode 100644 arch/mips/rtl8186/prom.c
 create mode 100644 arch/mips/rtl8186/setup.c
 create mode 100644 arch/mips/rtl8186/time.c

index ac7ad54f984f..2793741f05e5 100644
@@ -27,6 +27,7 @@ platforms += pmcs-msp71xx
 platforms += pnx833x
 platforms += ralink
 platforms += rb532
+platforms += rtl8186
 platforms += sgi-ip22
 platforms += sgi-ip27
 platforms += sgi-ip32

index bbeabd6b0a80..2f2ef09a1961 100644
@@ -344,6 +344,23 @@ config MACH_DECSTATION
 
 	  otherwise choose R3000.
 
+config MACH_RTL8186
+	bool "Realtek RTL8186 SoC"
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_HAS_CPU_LX5280
+	select DMA_NONCOHERENT
+	select SYS_SUPPORTS_ZBOOT_UART16550
+	select SYS_HAS_EARLY_PRINTK
+	select USE_GENERIC_EARLY_PRINTK_8250
+	select USE_OF
+	select COMMON_CLK
+	select RTL8186_IRQ
+	select RTL8186_TIMER
+	select BUILTIN_DTB
+	help
+	  Realtek RTL8186 SoC support.
+
 config MACH_JAZZ
 	bool "Jazz family of machines"
 	select ARCH_MIGHT_HAVE_PC_PARPORT

index aee8d7b8f091..99314df48718 100644
@@ -35,6 +35,11 @@
 #define IOTYPE unsigned int
 #endif
 
+#ifdef CONFIG_MACH_RTL8186
+#define UART0_BASE 0xbd0100c3
+#define PORT(offset) (UART0_BASE + (4 * offset))
+#endif
+
 #ifndef IOTYPE
 #define IOTYPE char
 #endif

index 1e79cab8e269..50dc192bbde5 100644
@@ -11,6 +11,7 @@ subdir-y	+= ni
 subdir-y	+= pic32
 subdir-y	+= qca
 subdir-y	+= ralink
+subdir-y	+= realtek
 subdir-y	+= xilfpga
 
 obj-$(CONFIG_BUILTIN_DTB)	:= $(addsuffix /, $(subdir-y))

new file mode 100644
index 000000000000..654c3a8da574
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_MACH_RTL8186)	+= rtl8186_edimax_br_6204wg.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .o, $(dtb-y))

new file mode 100644
index 000000000000..d699b25c7854
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_RTL8186_H
+#define __ASM_RTL8186_H
+
+#include <linux/compiler.h>
+
+#define RTL8186_REG_BASE ((void __iomem *)0xbd010000)
+#define RTL8186_REGISTER(offset) (RTL8186_REG_BASE + offset)
+
+/* Watchdog registers */
+#define RTL8186_CDBR        RTL8186_REGISTER(0x58)
+#define RTL8186_WDTCNR      RTL8186_REGISTER(0x5C)
+
+/* UART addresses */
+#define RTL8186_UART0_BASE  RTL8186_REGISTER(0xC3)
+#define RTL8186_UART1_BASE  RTL8186_REGISTER(0xE3)
+
+/* GPIO registers */
+#define RTL8186_GPABDATA    RTL8186_REGISTER(0x120)
+#define RTL8186_GPABDIR     RTL8186_REGISTER(0x124)
+#define RTL8186_GPABIMR     RTL8186_REGISTER(0x128)
+#define RTL8186_GPABISR     RTL8186_REGISTER(0x12C)
+#define RTL8186_GPCDDATA    RTL8186_REGISTER(0x130)
+#define RTL8186_GPCDDIR     RTL8186_REGISTER(0x134)
+#define RTL8186_GPCDIMR     RTL8186_REGISTER(0x138)
+#define RTL8186_GPCDISR     RTL8186_REGISTER(0x13C)
+#define RTL8186_GPEFDATA    RTL8186_REGISTER(0x140)
+#define RTL8186_GPEFDIR     RTL8186_REGISTER(0x144)
+#define RTL8186_GPEFIMR     RTL8186_REGISTER(0x148)
+#define RTL8186_GPEFISR     RTL8186_REGISTER(0x14C)
+#define RTL8186_GPGDATA     RTL8186_REGISTER(0x150)
+#define RTL8186_GPGDIR      RTL8186_REGISTER(0x154)
+#define RTL8186_GPGIMR      RTL8186_REGISTER(0x158)
+#define RTL8186_GPGISR      RTL8186_REGISTER(0x15C)
+
+
+#endif /* __ASM_RTL8186_H */

new file mode 100644
index 000000000000..010f38349aa6
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0
+obj-y := prom.o setup.o irq.o time.o

new file mode 100644
index 000000000000..5c23cfbffc62
@@ -0,0 +1,7 @@
+#
+# RTL8186
+#
+platform-$(CONFIG_MACH_RTL8186) += rtl8186/
+cflags-$(CONFIG_MACH_RTL8186)   += -I$(srctree)/arch/mips/include/asm/mach-rtl8186
+load-$(CONFIG_MACH_RTL8186)     += 0xffffffff80010000
+zload-$(CONFIG_MACH_RTL8186)    += 0xffffffff80800000

new file mode 100644
index 000000000000..f158bfe25bca
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/init.h>
+#include <linux/irqchip.h>
+
+void __init arch_init_irq(void)
+{
+	irqchip_init();
+}

new file mode 100644
index 000000000000..0ec7979a23f9
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/mach-rtl8186/rtl8186.h>
+
+void __init prom_init(void)
+{
+	setup_8250_early_printk_port((unsigned long)RTL8186_UART0_BASE, 2,
+				     10000);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}

new file mode 100644
index 000000000000..78062b588bb3
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/init.h>
+#include <linux/clocksource.h>
+#include <linux/of_clk.h>
+
+void __init plat_time_init(void)
+{
+	of_clk_init(NULL);
+	timer_probe();
+}

2.19.0