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drm/msm/a6xx: Remove CP perfcounter selects from the protected list

PATCH New Jordan Crouse 1 participant 1 message Oct 5, 2018

Subsystems (4)
DRM drivers Arm Qualcomm mailing list DRM driver for Qualcomm display hardware DRM driver for Qualcomm Adreno GPUs
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Jordan Crouse

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PATCH 1/1 drm/msm/a6xx: Remove CP perfcounter selects from the protected list

The CP performance counter selects were accidentally marked as protected so they couldn't be written from PM4 streams. Remove the protection because user space does have an interest in setting up their own counters.

Signed-off-by Jordan Crouse <[email protected]>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +1 -3
index de01e6553999..cd67f45dee6e 100644
@@ -440,10 +440,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
 	gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
 	gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
 	gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
-			A6XX_PROTECT_RDONLY(0x8d0, 0x23));
-	gpu_write(gpu, REG_A6XX_CP_PROTECT(25),
 			A6XX_PROTECT_RDONLY(0x980, 0x4));
-	gpu_write(gpu, REG_A6XX_CP_PROTECT(26), A6XX_PROTECT_RW(0xa630, 0x0));
+	gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
 
 	/* Enable interrupts */
 	gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
Signature · 6 lines
2.18.0

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