Port mxs-dcp to 6ull and 6sll
Subsystems (3)
cover Port mxs-dcp to 6ull and 6sll
The only important difference relative to 6sl is that explicit clock enabling is required.
The driver currently doesn't even probe on 6sl, a separate series was posted to deal with the crypto functionality, those might take a while:
https://lkml.org/lkml/2018/10/2/1355
Since the functionality issues are not SOC-specific it seems reasonable to deal with porting separately.
Leonard Crestez (3):
dt-bindings: crypto: Mention clocks for mxs-dcp
crypto: mxs-dcp - Add support for dcp clk
ARM: dts: imx6ull: Add dcp node
.../devicetree/bindings/crypto/fsl-dcp.txt | 2 ++ arch/arm/boot/dts/imx6ull.dtsi | 10 ++++++++++ drivers/crypto/mxs-dcp.c | 18 ++++++++++++++++++ 3 files changed, 30 insertions(+)
Signature · 1 line
2.17.1
PATCH 1/3 dt-bindings: crypto: Mention clocks for mxs-dcp
Explicit clock enabling is required on 6sll and 6ull so mention that standard clock bindings are used.
--- Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/crypto/fsl-dcp.txt +2 -0
@@ -4,10 +4,12 @@ Required properties: - compatible : Should be "fsl,<soc>-dcp" - reg : Should contain MXS DCP registers location and length - interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ must be supplied, optionally Secure IRQ can be present, but is currently not implemented and not used. +- clocks : Clock reference (only required on some SOCs: 6ull and 6sll). +- clock-names : Must be "dcp". Example: dcp@80028000 { compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Signature · 1 line
2.17.1
Re: [PATCH 1/3] dt-bindings: crypto: Mention clocks for mxs-dcp
Quoted 7 lines · Leonard Crestez
Explicit clock enabling is required on 6sll and 6ull so mention that standard clock bindings are used.
Signed-off-by Leonard Crestez <[email protected]>--- Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++ 1 file changed, 2 insertions(+)
DT list and maintainers should be copied on bindings update, which needs to be ACK-ed by DT maintainers.
Shawn
Quoted 21 lines
Documentation/devicetree/bindings/crypto/fsl-dcp.txt +2
-0@@ -4,10 +4,12 @@ Required properties: - compatible : Should be "fsl,<soc>-dcp" - reg : Should contain MXS DCP registers location and length - interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ must be supplied, optionally Secure IRQ can be present, but is currently not implemented and not used. +- clocks : Clock reference (only required on some SOCs: 6ull and 6sll). +- clock-names : Must be "dcp". Example: dcp@80028000 { compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";Signature · 1 line
2.17.1
PATCH 2/3 crypto: mxs-dcp - Add support for dcp clk
In reply to Leonard CrestezOn 6ull and 6sll the DCP block has a clock which needs to be explicitly enabled.
Add minimal handling for this at probe/remove time.
--- drivers/crypto/mxs-dcp.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
drivers/crypto/mxs-dcp.c +18 -0
@@ -18,10 +18,11 @@#include <linux/kthread.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/stmp_device.h> +#include <linux/clk.h> #include <crypto/aes.h> #include <crypto/sha.h> #include <crypto/internal/hash.h> #include <crypto/internal/skcipher.h>
@@ -64,10 +65,11 @@ struct dcp {struct completion completion[DCP_MAX_CHANS ];spinlock_t lock[DCP_MAX_CHANS ];struct task_struct *thread[DCP_MAX_CHANS ];struct crypto_queue queue[DCP_MAX_CHANS ]; +struct clk *dcp_clk; };enum dcp_chan {DCP_CHAN_HASH_SHA =0 ,DCP_CHAN_CRYPTO =2 ,
@@ -947,10 +949,24 @@ static int mxs_dcp_probe(struct platform_device *pdev) sdcp->dev = dev; sdcp->base =devm_ioremap_resource (dev, iores);if (IS_ERR (sdcp->base))return PTR_ERR (sdcp->base); +/* DCP clock is optional, only used on some SOCs */ + sdcp->dcp_clk =devm_clk_get (dev,"dcp" ); +if (IS_ERR (sdcp->dcp_clk)) { +if (sdcp->dcp_clk !=ERR_PTR (-ENOENT )) +return PTR_ERR (sdcp->dcp_clk); + sdcp->dcp_clk =NULL ; + } + + ret =clk_prepare (sdcp->dcp_clk); +if (ret) +return ret; + ret =clk_enable (sdcp->dcp_clk); +if (ret) +return ret; ret =devm_request_irq (dev, dcp_vmi_irq, mxs_dcp_irq,0 ,"dcp-vmi-irq" , sdcp);if (ret) {dev_err (dev,"Failed to claim DCP VMI IRQ!\n" );
@@ -1088,10 +1104,12 @@ static int mxs_dcp_remove(struct platform_device *pdev)crypto_unregister_algs (dcp_aes_algs,ARRAY_SIZE (dcp_aes_algs));kthread_stop (sdcp->thread[DCP_CHAN_HASH_SHA ]);kthread_stop (sdcp->thread[DCP_CHAN_CRYPTO ]); +clk_disable (sdcp->dcp_clk); +platform_set_drvdata (pdev,NULL ); global_sdcp =NULL ;return 0 ;
Signature · 1 line
2.17.1
PATCH 3/3 ARM: dts: imx6ull: Add dcp node
In reply to Leonard CrestezThe DCP block on 6ull has no major differences other than requiring explicit clock enabling.
--- arch/arm/boot/dts/imx6ull.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/imx6ull.dtsi +10 -0
@@ -37,10 +37,20 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x02200000 0x100000>; ranges; + dcp: dcp@2280000 { + compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; + reg = <0x02280000 0x4000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6ULL_CLK_DCP_CLK>; + clock-names = "dcp"; + }; + iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; };
Signature · 1 line
2.17.1