Documentation/arm64: HugeTLB page implementation
PATCH 1/1 Documentation/arm64: HugeTLB page implementation
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
--- Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/arm64/hugetlbpage.txt
Documentation/arm64/hugetlbpage.txt new file +39 -0
@@ -0,0 +1,39 @@ +HugeTLBpage on ARM64 +==================== + +Hugepage relies on making efficient use of TLBs to improve performance of +address translations. The benefit depends on both - + + - the size of hugepages + - size of entries supported by the TLBs + +The ARM64 port supports two flavours of hugepages. + +1) Block mappings at the pud/pmd level +-------------------------------------- + +These are regular hugepages where a pmd or a pud page table entry points to a +block of memory. Regardless of the supported size of entries in TLB, block +mappings reduces the depth of page table walk needed to translate hugepage +addresses. + +2) Using the Contiguous bit +--------------------------- + +The architecture provides a contiguous bit in the translation table entries +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of a +contiguous set of entries that can be cached in a single TLB entry. + +The contiguous bit is used in Linux to increase the mapping size at the pmd and +pte (last) level. The number of supported contiguous entries vary by page size +and level of the page table. + + + +The following hugepage sizes are supported - + + CONT PTE PMD CONT PMD PUD + -------- --- -------- --- + 4K: 64K 2M 32M 1G + 16K: 2M 32M 1G + 64K: 2M 512M 16G
Signature · 1 line
2.18.0
Randy Dunlap
reviewerHi,
Just some minor stuff (below).
Quoted 34 lines · Punit Agrawal
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
Signed-off-by Punit Agrawal <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Cc Jonathan Corbet <[email protected]>--- Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/arm64/hugetlbpage.txtDocumentation/arm64/hugetlbpage.txt new file +7
-0@@ -0,0 +1,39 @@ +HugeTLBpage on ARM64 +==================== + +Hugepage relies on making efficient use of TLBs to improve performance of +address translations. The benefit depends on both - + + - the size of hugepages
Documentation/arm64/hugetlbpage.txt line 17
Quoted 10 lines
Documentation/arm64/hugetlbpage.txt new file +10
-0+ - size of entries supported by the TLBs + +The ARM64 port supports two flavours of hugepages. + +1) Block mappings at the pud/pmd level +-------------------------------------- + +These are regular hugepages where a pmd or a pud page table entry points to a +block of memory. Regardless of the supported size of entries in TLB, block +mappings reduces the depth of page table walk needed to translate hugepage
reduce
Documentation/arm64/hugetlbpage.txt line 24
Quoted 7 lines
Documentation/arm64/hugetlbpage.txt new file +7
-0+addresses. + +2) Using the Contiguous bit +--------------------------- + +The architecture provides a contiguous bit in the translation table entries +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of a
preferably MMU
Documentation/arm64/hugetlbpage.txt line 28
Quoted 4 lines
Documentation/arm64/hugetlbpage.txt new file +4
-0+contiguous set of entries that can be cached in a single TLB entry. + +The contiguous bit is used in Linux to increase the mapping size at the pmd and +pte (last) level. The number of supported contiguous entries vary by page size
varies
Documentation/arm64/hugetlbpage.txt line 39
Quoted 12 lines
Documentation/arm64/hugetlbpage.txt new file +11
-0+and level of the page table. + + + +The following hugepage sizes are supported - + + CONT PTE PMD CONT PMD PUD + -------- --- -------- --- + 4K: 64K 2M 32M 1G + 16K: 2M 32M 1G + 64K: 2M 512M 16G
thanks,
Signature · 1 line
~Randy
Hi Randy,
Quoted 68 lines · Randy Dunlap
Hi,
Just some minor stuff (below).Quoted 34 lines · Punit Agrawal
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
Signed-off-by Punit Agrawal <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Cc Jonathan Corbet <[email protected]>--- Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/arm64/hugetlbpage.txtDocumentation/arm64/hugetlbpage.txt new file +7
-0@@ -0,0 +1,39 @@ +HugeTLBpage on ARM64 +==================== + +Hugepage relies on making efficient use of TLBs to improve performance of +address translations. The benefit depends on both - + + - the size of hugepagesDocumentation/arm64/hugetlbpage.txt line 17
Quoted 10 lines
Documentation/arm64/hugetlbpage.txt new file +10
-0+ - size of entries supported by the TLBs + +The ARM64 port supports two flavours of hugepages. + +1) Block mappings at the pud/pmd level +-------------------------------------- + +These are regular hugepages where a pmd or a pud page table entry points to a +block of memory. Regardless of the supported size of entries in TLB, block +mappings reduces the depth of page table walk needed to translate hugepagereduce
Documentation/arm64/hugetlbpage.txt line 24
Quoted 7 lines
Documentation/arm64/hugetlbpage.txt new file +7
-0+addresses. + +2) Using the Contiguous bit +--------------------------- + +The architecture provides a contiguous bit in the translation table entries +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of apreferably MMU
Documentation/arm64/hugetlbpage.txt line 28
Quoted 4 lines
Documentation/arm64/hugetlbpage.txt new file +4
-0+contiguous set of entries that can be cached in a single TLB entry. + +The contiguous bit is used in Linux to increase the mapping size at the pmd and +pte (last) level. The number of supported contiguous entries vary by page sizevaries
Quoted 12 lines
Documentation/arm64/hugetlbpage.txt line 39
Quoted 12 lines
Documentation/arm64/hugetlbpage.txt new file +11
-0+and level of the page table. + + + +The following hugepage sizes are supported - + + CONT PTE PMD CONT PMD PUD + -------- --- -------- --- + 4K: 64K 2M 32M 1G + 16K: 2M 32M 1G + 64K: 2M 512M 16G
I've updated the patch with incorporating your feedback and will post an update shortly.
Thanks a lot for taking a look.
Punit
PATCH v2 1/1 Documentation/arm64: HugeTLB page implementation
In reply to Randy DunlapArm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
---
Hi,
This version incorporates the feedback on v1.
Thanks,
Punit
Documentation/arm64/hugetlbpage.txt | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/arm64/hugetlbpage.txt
Documentation/arm64/hugetlbpage.txt new file +38 -0
@@ -0,0 +1,38 @@ +HugeTLBpage on ARM64 +==================== + +Hugepage relies on making efficient use of TLBs to improve performance of +address translations. The benefit depends on both - + + - the size of hugepages + - size of entries supported by the TLBs + +The ARM64 port supports two flavours of hugepages. + +1) Block mappings at the pud/pmd level +-------------------------------------- + +These are regular hugepages where a pmd or a pud page table entry points to a +block of memory. Regardless of the supported size of entries in TLB, block +mappings reduce the depth of page table walk needed to translate hugepage +addresses. + +2) Using the Contiguous bit +--------------------------- + +The architecture provides a contiguous bit in the translation table entries +(D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a +contiguous set of entries that can be cached in a single TLB entry. + +The contiguous bit is used in Linux to increase the mapping size at the pmd and +pte (last) level. The number of supported contiguous entries varies by page size +and level of the page table. + + +The following hugepage sizes are supported - + + CONT PTE PMD CONT PMD PUD + -------- --- -------- --- + 4K: 64K 2M 32M 1G + 16K: 2M 32M 1G + 64K: 2M 512M 16G
Signature · 1 line
2.18.0
Quoted 9 lines · Punit Agrawal
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Quoted 7 lines
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
Signed-off-by Punit Agrawal <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Cc Jonathan Corbet <[email protected]>
Thanks.
Quoted 57 lines
---
Hi,This version incorporates the feedback on v1.
Thanks,
PunitDocumentation/arm64/hugetlbpage.txt | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/arm64/hugetlbpage.txtDocumentation/arm64/hugetlbpage.txt new file +38
-0@@ -0,0 +1,38 @@ +HugeTLBpage on ARM64 +==================== + +Hugepage relies on making efficient use of TLBs to improve performance of +address translations. The benefit depends on both - + + - the size of hugepages + - size of entries supported by the TLBs + +The ARM64 port supports two flavours of hugepages. + +1) Block mappings at the pud/pmd level +-------------------------------------- + +These are regular hugepages where a pmd or a pud page table entry points to a +block of memory. Regardless of the supported size of entries in TLB, block +mappings reduce the depth of page table walk needed to translate hugepage +addresses. + +2) Using the Contiguous bit +--------------------------- + +The architecture provides a contiguous bit in the translation table entries +(D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a +contiguous set of entries that can be cached in a single TLB entry. + +The contiguous bit is used in Linux to increase the mapping size at the pmd and +pte (last) level. The number of supported contiguous entries varies by page size +and level of the page table. + + +The following hugepage sizes are supported - + + CONT PTE PMD CONT PMD PUD + -------- --- -------- --- + 4K: 64K 2M 32M 1G + 16K: 2M 32M 1G + 64K: 2M 512M 16G
Signature · 1 line
~Randy
Quoted 13 lines · Randy Dunlap
Quoted 12 lines · Punit Agrawal
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
Quoted 6 lines
Quoted 4 lines
Signed-off-by Punit Agrawal <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Cc Jonathan Corbet <[email protected]>Acked-by Randy Dunlap <[email protected]>
Thanks!
Catalin, Will - I assume you'll pick this up at some point? Or do arm64 documentation patches get routed by another tree?
Quoted 60 lines
Thanks.
Quoted 57 lines
---
Hi,This version incorporates the feedback on v1.
Thanks,
PunitDocumentation/arm64/hugetlbpage.txt | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/arm64/hugetlbpage.txtDocumentation/arm64/hugetlbpage.txt new file +38
-0@@ -0,0 +1,38 @@ +HugeTLBpage on ARM64 +==================== + +Hugepage relies on making efficient use of TLBs to improve performance of +address translations. The benefit depends on both - + + - the size of hugepages + - size of entries supported by the TLBs + +The ARM64 port supports two flavours of hugepages. + +1) Block mappings at the pud/pmd level +-------------------------------------- + +These are regular hugepages where a pmd or a pud page table entry points to a +block of memory. Regardless of the supported size of entries in TLB, block +mappings reduce the depth of page table walk needed to translate hugepage +addresses. + +2) Using the Contiguous bit +--------------------------- + +The architecture provides a contiguous bit in the translation table entries +(D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a +contiguous set of entries that can be cached in a single TLB entry. + +The contiguous bit is used in Linux to increase the mapping size at the pmd and +pte (last) level. The number of supported contiguous entries varies by page size +and level of the page table. + + +The following hugepage sizes are supported - + + CONT PTE PMD CONT PMD PUD + -------- --- -------- --- + 4K: 64K 2M 32M 1G + 16K: 2M 32M 1G + 64K: 2M 512M 16G
Will Deacon
Acked-byQuoted 20 lines · Punit Agrawal
Quoted 18 lines · Randy Dunlap
Quoted 16 lines · Punit Agrawal
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
Signed-off-by Punit Agrawal <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Cc Jonathan Corbet <[email protected]>
Quoted 6 lines
Quoted 1 line
Acked-by Randy Dunlap <[email protected]>Thanks!
Catalin, Will - I assume you'll pick this up at some point? Or do arm64 documentation patches get routed by another tree?
Catalin can pick this up for 4.20.
Will
Quoted 23 lines · Will Deacon
Quoted 22 lines · Punit Agrawal
Quoted 19 lines · Randy Dunlap
Quoted 9 lines · Punit Agrawal
Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels.
In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes.
Quoted 7 lines
Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each.
Signed-off-by Punit Agrawal <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Cc Jonathan Corbet <[email protected]>Acked-by Randy Dunlap <[email protected]>
Quoted 8 lines
Quoted 4 lines
Thanks!
Catalin, Will - I assume you'll pick this up at some point? Or do arm64 documentation patches get routed by another tree?
Acked-by Will Deacon <[email protected]>Catalin can pick this up for 4.20.
Done.
Signature · 1 line
Catalin