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Scatter to CQE

PATCH In review Leon Romanovsky 2 participants 8 messages Oct 9, 2018 – Oct 17, 2018

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#0 lore raw

cover Scatter to CQE

From: Leon Romanovsky <[email protected]>

Changelog v0->v1:
* Changed patch #3 to use check_mask function from rdma-core instead define.

--------------------------------------------------------------------------

Quoted 1 line

From Yonatan,

Scatter to CQE is a HW offload feature that saves PCI writes by scattering the payload to the CQE.

The feature depends on the CQE size and if the CQE size is 64B, it will work for payload smaller than 32. If the CQE size is 128B, it will work for payload smaller than 64.

The feature works for responder and requestor:
1. For responder, if the payload is small as required above, the data will be part of the CQE, and thus we save another PCI transaction the recv buffers.
2. For requestor, this can be used to get the RDMA_READ response and RDMA_ATOMIC response in the CQE. This feature is already supported in upstream.

As part of this series, we are adding support for DC transport type and ability to enable the feature (force enable) in the requestor when SQ is not configured to signal all WRs.

Thanks

Yonatan Cohen (4):
net/mlx5: Expose DC scatter to CQE capability bit IB/mlx5: Support scatter to CQE for DC transport type IB/mlx5: Verify that driver supports user flags IB/mlx5: Allow scatter to CQE without global signaled WRs

 drivers/infiniband/hw/mlx5/cq.c      |  2 +-
 drivers/infiniband/hw/mlx5/mlx5_ib.h |  2 +-
 drivers/infiniband/hw/mlx5/qp.c      | 93 ++++++++++++++++++++++++++++--------
 include/linux/mlx5/mlx5_ifc.h        |  3 +-
 include/uapi/rdma/mlx5-abi.h         |  1 +
 5 files changed, 79 insertions(+), 22 deletions(-)
#1 lore raw

PATCH 1/4 net/mlx5: Expose DC scatter to CQE capability bit

From: Yonatan Cohen <[email protected]>

dc_req_scat_data_cqe capability bit determines
if requester scatter to cqe is available for 64 bytes CQE over DC transport type.

---
 include/linux/mlx5/mlx5_ifc.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
include/linux/mlx5/mlx5_ifc.h +2 -1
index 68f4d5f9d929..0f460fb22c31 100644
@@ -1005,7 +1005,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 	u8         umr_modify_atomic_disabled[0x1];
 	u8         umr_indirect_mkey_disabled[0x1];
 	u8         umr_fence[0x2];
-	u8         reserved_at_20c[0x3];
+	u8         dc_req_scat_data_cqe[0x1];
+	u8         reserved_at_20d[0x2];
 	u8         drain_sigerr[0x1];
 	u8         cmdif_checksum[0x2];
 	u8         sigerr_cqe[0x1];
Signature · 1 line
2.14.4
#2 lore raw

PATCH 2/4 IB/mlx5: Support scatter to CQE for DC transport type

In reply to Leon Romanovsky

From: Yonatan Cohen <[email protected]>

Scatter to CQE is a HW offload that saves PCI writes by scattering the payload to the CQE.
This patch extends already existing functionality to support DC transport type.

---
 drivers/infiniband/hw/mlx5/cq.c      |  2 +-
 drivers/infiniband/hw/mlx5/mlx5_ib.h |  2 +-
 drivers/infiniband/hw/mlx5/qp.c      | 71 ++++++++++++++++++++++++++----------
 3 files changed, 54 insertions(+), 21 deletions(-)
drivers/infiniband/hw/mlx5/cq.c +1 -1
index dae30b6478bf..a41519dc8d3a 100644
@@ -1460,7 +1460,7 @@ int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
 	return err;
 }
 
-int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
+int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
 {
 	struct mlx5_ib_cq *cq;
 
drivers/infiniband/hw/mlx5/mlx5_ib.h +1 -1
index e5ec3fdaa4d5..f52dfed1395d 100644
@@ -1127,7 +1127,7 @@ void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
 			  int page_shift, __be64 *pas, int access_flags);
 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
-int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
+int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
 
drivers/infiniband/hw/mlx5/qp.c +52 -19

101 lines not on this page · raw message

Signature · 1 line
2.14.4
#3 lore raw

PATCH 3/4 IB/mlx5: Verify that driver supports user flags

In reply to Leon Romanovsky

From: Yonatan Cohen <[email protected]>

Flags sent down from user might not be supported by running driver.
This might lead to unwanted bugs.
To solve this, added macro to test for unsupported flags.

---
 drivers/infiniband/hw/mlx5/qp.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
drivers/infiniband/hw/mlx5/qp.c +14 -0
index bae48bdf281c..73a53a8da9b6 100644
@@ -1728,6 +1728,11 @@ static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
 		MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
 }
 
+static inline bool check_flags_mask(uint64_t input, uint64_t supported)
+{
+	return (input & ~supported) == 0;
+}
+
 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 			    struct ib_qp_init_attr *init_attr,
 			    struct ib_udata *udata, struct mlx5_ib_qp *qp)
@@ -1825,6 +1830,15 @@ static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 			return -EFAULT;
 		}
 
+		if (!check_flags_mask(ucmd.flags,
+				      MLX5_QP_FLAG_SIGNATURE |
+					      MLX5_QP_FLAG_SCATTER_CQE |
+					      MLX5_QP_FLAG_TUNNEL_OFFLOADS |
+					      MLX5_QP_FLAG_BFREG_INDEX |
+					      MLX5_QP_FLAG_TYPE_DCT |
+					      MLX5_QP_FLAG_TYPE_DCI))
+			return -EINVAL;
+
 		err = get_qp_user_index(to_mucontext(pd->uobject->context),
 					&ucmd, udata->inlen, &uidx);
 		if (err)
Signature · 1 line
2.14.4
#4 lore raw

PATCH 4/4 IB/mlx5: Allow scatter to CQE without global signaled WRs

In reply to Leon Romanovsky

From: Yonatan Cohen <[email protected]>

Requester scatter to CQE is restricted to QPs configured to signal all WRs.

This patch adds ability to enable scatter to cqe (force enable) in the requester without sig_all, for users who do not want all WRs signaled but rather just the ones whose data found in the CQE.

---
 drivers/infiniband/hw/mlx5/qp.c | 14 +++++++++++---
 include/uapi/rdma/mlx5-abi.h    |  1 +
 2 files changed, 12 insertions(+), 3 deletions(-)
drivers/infiniband/hw/mlx5/qp.c +11 -3
index 73a53a8da9b6..1a6f34ea2f5d 100644
@@ -1706,15 +1706,20 @@ static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
 
 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
 					 struct ib_qp_init_attr *init_attr,
+					 struct mlx5_ib_create_qp *ucmd,
 					 void *qpc)
 {
 	enum ib_qp_type qpt = init_attr->qp_type;
 	int scqe_sz;
+	bool allow_scat_cqe = 0;
 
 	if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
 		return;
 
-	if (init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
+	if (ucmd)
+		allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
+
+	if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
 		return;
 
 	scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
@@ -1836,7 +1841,8 @@ static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 					      MLX5_QP_FLAG_TUNNEL_OFFLOADS |
 					      MLX5_QP_FLAG_BFREG_INDEX |
 					      MLX5_QP_FLAG_TYPE_DCT |
-					      MLX5_QP_FLAG_TYPE_DCI))
+					      MLX5_QP_FLAG_TYPE_DCI |
+					      MLX5_QP_FLAG_ALLOW_SCATTER_CQE))
 			return -EINVAL;
 
 		err = get_qp_user_index(to_mucontext(pd->uobject->context),
@@ -1971,7 +1977,9 @@ static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 
 	if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
 		configure_responder_scat_cqe(init_attr, qpc);
-		configure_requester_scat_cqe(dev, init_attr, qpc);
+		configure_requester_scat_cqe(dev, init_attr,
+					     (pd && pd->uobject) ? &ucmd : NULL,
+					     qpc);
 	}
 
 	if (qp->rq.wqe_cnt) {
include/uapi/rdma/mlx5-abi.h +1 -0
index 6056625237cf..8fa9f90e2bb1 100644
@@ -47,6 +47,7 @@ enum {
 	MLX5_QP_FLAG_TYPE_DCI		= 1 << 5,
 	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
 	MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
+	MLX5_QP_FLAG_ALLOW_SCATTER_CQE	= 1 << 8,
 };
 
 enum {
Signature · 1 line
2.14.4
#5 lore raw
In reply to Leon Romanovsky
Quoted 40 lines · Leon Romanovsky

From: Leon Romanovsky <[email protected]>

Changelog v0->v1:
* Changed patch #3 to use check_mask function from rdma-core instead define.

--------------------------------------------------------------------------
From Yonatan,

Scatter to CQE is a HW offload feature that saves PCI writes by scattering the payload to the CQE.

The feature depends on the CQE size and if the CQE size is 64B, it will work for payload smaller than 32. If the CQE size is 128B, it will work for payload smaller than 64.

The feature works for responder and requestor:
1. For responder, if the payload is small as required above, the data will be part of the CQE, and thus we save another PCI transaction the recv buffers.
2. For requestor, this can be used to get the RDMA_READ response and RDMA_ATOMIC response in the CQE. This feature is already supported in upstream.

As part of this series, we are adding support for DC transport type and ability to enable the feature (force enable) in the requestor when SQ is not configured to signal all WRs.

Thanks

Yonatan Cohen (4):
net/mlx5: Expose DC scatter to CQE capability bit IB/mlx5: Support scatter to CQE for DC transport type IB/mlx5: Verify that driver supports user flags IB/mlx5: Allow scatter to CQE without global signaled WRs

 drivers/infiniband/hw/mlx5/cq.c      |  2 +-
 drivers/infiniband/hw/mlx5/mlx5_ib.h |  2 +-
 drivers/infiniband/hw/mlx5/qp.c      | 93 ++++++++++++++++++++++++++++--------
 include/linux/mlx5/mlx5_ifc.h        |  3 +-
 include/uapi/rdma/mlx5-abi.h         |  1 +
 5 files changed, 79 insertions(+), 22 deletions(-)
Quoted 3 lines

--
2.14.4

Hi Leon,

This series looks fine. Let me know when the net/mlx5 portion has been committed.

Signature · 3 lines
Doug Ledford <[email protected]>
    GPG KeyID: B826A3330E572FDD
    Key fingerprint = AE6B 1BDA 122B 23B4 265B  1274 B826 A333 0E57 2FDD
#6 lore raw
Quoted 46 lines · Doug Ledford
Quoted 40 lines · Leon Romanovsky

From: Leon Romanovsky <[email protected]>

Changelog v0->v1:
* Changed patch #3 to use check_mask function from rdma-core instead define.

--------------------------------------------------------------------------
From Yonatan,

Scatter to CQE is a HW offload feature that saves PCI writes by scattering the payload to the CQE.

The feature depends on the CQE size and if the CQE size is 64B, it will work for payload smaller than 32. If the CQE size is 128B, it will work for payload smaller than 64.

The feature works for responder and requestor:
1. For responder, if the payload is small as required above, the data will be part of the CQE, and thus we save another PCI transaction the recv buffers.
2. For requestor, this can be used to get the RDMA_READ response and RDMA_ATOMIC response in the CQE. This feature is already supported in upstream.

As part of this series, we are adding support for DC transport type and ability to enable the feature (force enable) in the requestor when SQ is not configured to signal all WRs.

Thanks

Yonatan Cohen (4):
net/mlx5: Expose DC scatter to CQE capability bit IB/mlx5: Support scatter to CQE for DC transport type IB/mlx5: Verify that driver supports user flags IB/mlx5: Allow scatter to CQE without global signaled WRs

 drivers/infiniband/hw/mlx5/cq.c      |  2 +-
 drivers/infiniband/hw/mlx5/mlx5_ib.h |  2 +-
 drivers/infiniband/hw/mlx5/qp.c      | 93 ++++++++++++++++++++++++++++--------
 include/linux/mlx5/mlx5_ifc.h        |  3 +-
 include/uapi/rdma/mlx5-abi.h         |  1 +
 5 files changed, 79 insertions(+), 22 deletions(-)
Quoted 3 lines

--
2.14.4

Quoted 4 lines

Hi Leon,

This series looks fine. Let me know when the net/mlx5 portion has been committed.

Thanks Doug,
I pushed first patch to mlx5-next
94a04d1d3d36 ("net/mlx5: Expose DC scatter to CQE capability bit")

Quoted 5 lines

--
Doug Ledford <[email protected]>

    GPG KeyID: B826A3330E572FDD
    Key fingerprint = AE6B 1BDA 122B 23B4 265B  1274 B826 A333 0E57 2FDD
#7 lore raw
Quoted 47 lines · Leon Romanovsky
Quoted 46 lines · Doug Ledford
Quoted 43 lines · Leon Romanovsky

From: Leon Romanovsky <[email protected]>

Changelog v0->v1:
* Changed patch #3 to use check_mask function from rdma-core instead define.

--------------------------------------------------------------------------
From Yonatan,

Scatter to CQE is a HW offload feature that saves PCI writes by scattering the payload to the CQE.

The feature depends on the CQE size and if the CQE size is 64B, it will work for payload smaller than 32. If the CQE size is 128B, it will work for payload smaller than 64.

The feature works for responder and requestor:
1. For responder, if the payload is small as required above, the data will be part of the CQE, and thus we save another PCI transaction the recv buffers.
2. For requestor, this can be used to get the RDMA_READ response and RDMA_ATOMIC response in the CQE. This feature is already supported in upstream.

As part of this series, we are adding support for DC transport type and ability to enable the feature (force enable) in the requestor when SQ is not configured to signal all WRs.

Thanks

Yonatan Cohen (4):
net/mlx5: Expose DC scatter to CQE capability bit IB/mlx5: Support scatter to CQE for DC transport type IB/mlx5: Verify that driver supports user flags IB/mlx5: Allow scatter to CQE without global signaled WRs

 drivers/infiniband/hw/mlx5/cq.c      |  2 +-
 drivers/infiniband/hw/mlx5/mlx5_ib.h |  2 +-
 drivers/infiniband/hw/mlx5/qp.c      | 93 ++++++++++++++++++++++++++++--------
 include/linux/mlx5/mlx5_ifc.h        |  3 +-
 include/uapi/rdma/mlx5-abi.h         |  1 +
 5 files changed, 79 insertions(+), 22 deletions(-)

--
2.14.4

Quoted 8 lines
Quoted 4 lines

Hi Leon,

This series looks fine. Let me know when the net/mlx5 portion has been committed.

Thanks Doug,
I pushed first patch to mlx5-next
94a04d1d3d36 ("net/mlx5: Expose DC scatter to CQE capability bit")

Thanks Leon, mlx5-next merged in, then remainder of series applied to for-next.

Signature · 3 lines
Doug Ledford <[email protected]>
    GPG KeyID: B826A3330E572FDD
    Key fingerprint = AE6B 1BDA 122B 23B4 265B  1274 B826 A333 0E57 2FDD