Add support for Pinebook

PATCH Superseded Vasily Khoruzhick 4 participants 24 messages Oct 17, 2018 – Oct 18, 2018

Subsystems (5)

Arm (32-bit) Arm sub-architectures Framebuffer layer MMC, SD and SDIO +1 more subsystems

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Vasily Khoruzhick

author

2018-10-17 05:09 UTC #0 lore raw

v2 cover Add support for Pinebook

This series adds support for the Pinebook, an allwinner A64 laptop produced by Pine64. It also syncs sun50i-a64.dtsi with linux, adds support for mmc delay calibration, R_I2C controller, and addresses the issue with activating video bridge when any of GPIOs is missing.

v2: - sync sun50i-a64.dtsi with linux instead of adding missing nodes
- take sun50i-a64-pinebook.dts from linux
- don't introduce new Kconfig for A64 MMC calibration
- improve code in video bridge uclass to check for presensce of GPIO instead of ingoring EINVAL errors

Vasily Khoruzhick (5):
mmc: sunxi: A64: add support for automatic delay calibration
dm: video: bridge: don't fail to activate bridge if reset or sleep
GPIO is missing
sunxi: DT: A64: update device tree file for Allwinner A64 SoC
sun50i: A64: add support for R_I2C controller
sunxi: DT: add support for Pinebook

 arch/arm/dts/Makefile                      |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts       | 306 +++++++++++++++++++++
 arch/arm/dts/sun50i-a64.dtsi               | 122 ++++++--
 arch/arm/include/asm/arch-sunxi/gpio.h     |   1 +
 arch/arm/include/asm/arch-sunxi/mmc.h      |   6 +-
 arch/arm/mach-sunxi/Kconfig                |   1 +
 board/sunxi/board.c                        |   6 +
 configs/pinebook_defconfig                 |  27 ++
 drivers/mmc/sunxi_mmc.c                    |  21 +-
 drivers/video/bridge/video-bridge-uclass.c |  14 +-
 10 files changed, 481 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

Signature · 1 line

2.19.0

Vasily Khoruzhick

author

2018-10-17 05:09 UTC #1 lore raw

PATCH v2 1/5 mmc: sunxi: A64: add support for automatic delay calibration

A64 supports automatic delay calibration and Linux driver uses it instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/mmc.h |  6 +++++-
 drivers/mmc/sunxi_mmc.c               | 21 ++++++++++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)

arch/arm/include/asm/arch-sunxi/mmc.h +5 -1

index d98c53faaa..f2deafddd2 100644
@@ -46,7 +46,9 @@ struct sunxi_mmc {
 	u32 cbda;		/* 0x94 */
 	u32 res2[26];
 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
-	u32 res3[64];
+	u32 res3[17];
+	u32 samp_dl;
+	u32 res4[46];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
 };

@@ -130,5 +132,7 @@ struct sunxi_mmc {
 #define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
 #define SUNXI_MMC_COMMON_RESET			(1 << 18)
 
+#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
+
 struct mmc *sunxi_mmc_init(int sdc_no);
 #endif /* _SUNXI_MMC_H */

drivers/mmc/sunxi_mmc.c +20 -1

index 39f15eb423..9e08ad59c6 100644
@@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 	bool new_mode = false;
+	bool calibrate = false;
 	u32 val = 0;
 
 	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
 		new_mode = true;
 
+#ifdef CONFIG_MACH_SUN50I
+	calibrate = true;
+#endif
+
 	/*
 	 * The MMC clock has an extra /2 post-divider when operating in the new
 	 * mode.

@@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 		val = CCM_MMC_CTRL_MODE_SEL_NEW;
 		setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 #endif
-	} else {
+	} else if (!calibrate) {
+		/*
+		 * Use hardcoded delay values if controller doesn't support
+		 * calibration
+		 */
 		val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 			CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 	}

@@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 	writel(rval, &priv->reg->clkcr);
 
+#ifdef CONFIG_MACH_SUN50I
+	/* A64 supports calibration of delays on MMC controller and we
+	 * have to set delay of zero before starting calibration.
+	 * Allwinner BSP driver sets a delay only in the case of
+	 * using HS400 which is not supported by mainline U-Boot or
+	 * Linux at the moment
+	 */
+	writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
+#endif
+
 	/* Re-enable Clock */
 	rval |= SUNXI_MMC_CLK_ENABLE;
 	writel(rval, &priv->reg->clkcr);

Signature · 1 line

2.19.0

André Przywara

2018-10-18 00:22 UTC #2 lore raw

PATCH v2 1/5 mmc: sunxi: A64: add support for automatic delay calibration

Quoted 39 lines · Vasily Khoruzhick

A64 supports automatic delay calibration and Linux driver uses it instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/mmc.h |  6 +++++-
 drivers/mmc/sunxi_mmc.c               | 21 ++++++++++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)

arch/arm/include/asm/arch-sunxi/mmc.h +5 -1

index d98c53faaa..f2deafddd2 100644
@@ -46,7 +46,9 @@ struct sunxi_mmc {
 	u32 cbda;		/* 0x94 */
 	u32 res2[26];
 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
-	u32 res3[64];
+	u32 res3[17];
+	u32 samp_dl;
+	u32 res4[46];
 #endif
 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
 };

@@ -130,5 +132,7 @@ struct sunxi_mmc {
 #define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
 #define SUNXI_MMC_COMMON_RESET			(1 << 18)
 
+#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
+
 struct mmc *sunxi_mmc_init(int sdc_no);
 #endif /* _SUNXI_MMC_H */

drivers/mmc/sunxi_mmc.c +0 -0

index 39f15eb423..9e08ad59c6 100644

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) · line 108

Quoted 10 lines

drivers/mmc/sunxi_mmc.c +2 -0

@@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 	bool new_mode = false;
+	bool calibrate = false;
 	u32 val = 0;
 
 	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
 		new_mode = true;
 
+#ifdef CONFIG_MACH_SUN50I

According to the Linux driver this applies to the H6 eMMC controller as well. So can you please add CONFIG_MACH_SUN50I_H6 here as well? Same below, of course.

Rest looks fine to me.

Cheers,
Andre.

Quoted 37 lines

drivers/mmc/sunxi_mmc.c +18 -1

+	calibrate = true;
+#endif
+
 	/*
 	 * The MMC clock has an extra /2 post-divider when operating in the new
 	 * mode.

@@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 		val = CCM_MMC_CTRL_MODE_SEL_NEW;
 		setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 #endif
-	} else {
+	} else if (!calibrate) {
+		/*
+		 * Use hardcoded delay values if controller doesn't support
+		 * calibration
+		 */
 		val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 			CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 	}

@@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 	writel(rval, &priv->reg->clkcr);
 
+#ifdef CONFIG_MACH_SUN50I
+	/* A64 supports calibration of delays on MMC controller and we
+	 * have to set delay of zero before starting calibration.
+	 * Allwinner BSP driver sets a delay only in the case of
+	 * using HS400 which is not supported by mainline U-Boot or
+	 * Linux at the moment
+	 */
+	writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
+#endif
+
 	/* Re-enable Clock */
 	rval |= SUNXI_MMC_CLK_ENABLE;
 	writel(rval, &priv->reg->clkcr);

Vasily Khoruzhick

author

2018-10-17 05:09 UTC #3 lore raw

PATCH v2 2/5 dm: video: bridge: don't fail to activate bridge if reset or sleep GPIO is missing

In reply to Vasily Khoruzhick

Both GPIOs are optional, so we shouldn't fail if any is missing. Without this fix reset is not deasserted when sleep GPIO is missing.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 drivers/video/bridge/video-bridge-uclass.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

drivers/video/bridge/video-bridge-uclass.c +10 -4

index cd4959cc71..7542097769 100644
@@ -109,10 +109,16 @@ int video_bridge_set_active(struct udevice *dev, bool active)
 	int ret;
 
 	debug("%s: %d\n", __func__, active);
-	ret = dm_gpio_set_value(&uc_priv->sleep, !active);
-	if (ret)
-		return ret;
-	if (active) {
+	if (uc_priv->sleep.dev) {
+		ret = dm_gpio_set_value(&uc_priv->sleep, !active);
+		if (ret)
+			return ret;
+	}
+
+	if (!active)
+		return 0;
+
+	if (uc_priv->reset.dev) {
 		ret = dm_gpio_set_value(&uc_priv->reset, true);
 		if (ret)
 			return ret;

Signature · 1 line

2.19.0

André Przywara

2018-10-18 00:22 UTC #4 lore raw

PATCH v2 2/5 dm: video: bridge: don't fail to activate bridge if reset or sleep GPIO is missing

Quoted 4 lines · Vasily Khoruzhick

Both GPIOs are optional, so we shouldn't fail if any is missing. Without this fix reset is not deasserted when sleep GPIO is missing.
Signed-off-by Vasily Khoruzhick <[email protected]>

That looks much better now, thanks.
One small thing:

drivers/video/bridge/video-bridge-uclass.c int video_bridge_set_active(struct udevice *dev, bool active) · line 109

Quoted 10 lines

---
 drivers/video/bridge/video-bridge-uclass.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

drivers/video/bridge/video-bridge-uclass.c +0 -0

index cd4959cc71..7542097769 100644
@@ -109,10 +109,16 @@ int video_bridge_set_active(struct udevice *dev, bool active)
 	int ret;

This needs to be initialised now.

Cheers,
Andre.

Quoted 20 lines

drivers/video/bridge/video-bridge-uclass.c +10 -4

 	debug("%s: %d\n", __func__, active);
-	ret = dm_gpio_set_value(&uc_priv->sleep, !active);
-	if (ret)
-		return ret;
-	if (active) {
+	if (uc_priv->sleep.dev) {
+		ret = dm_gpio_set_value(&uc_priv->sleep, !active);
+		if (ret)
+			return ret;
+	}
+
+	if (!active)
+		return 0;
+
+	if (uc_priv->reset.dev) {
 		ret = dm_gpio_set_value(&uc_priv->reset, true);
 		if (ret)
 			return ret;

Vasily Khoruzhick

author

2018-10-17 05:09 UTC #5 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

In reply to Vasily Khoruzhick

Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:

commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700

    Linux 4.19-rc4

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/dts/sun50i-a64.dtsi | 122 +++++++++++++++++++++++++++++------
 1 file changed, 103 insertions(+), 19 deletions(-)

arch/arm/dts/sun50i-a64.dtsi +103 ~~-19~~

index 7a083637c4..d3daf90a87 100644
@@ -43,9 +43,12 @@
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 	interrupt-parent = <&gic>;

@@ -57,17 +60,21 @@
 		#size-cells = <1>;
 		ranges;
 
-/*
- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- * However there is no support for this clock on A64 yet, so we depend
- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
- */
 		simplefb_lcd: framebuffer-lcd {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "mixer0-lcd0";
 			clocks = <&ccu CLK_TCON0>,
-				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+				 <&display_clocks CLK_MIXER0>;
+			status = "disabled";
+		};
+
+		simplefb_hdmi: framebuffer-hdmi {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "mixer1-lcd1-hdmi";
+			clocks = <&display_clocks CLK_MIXER1>,
+				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
 			status = "disabled";
 		};
 	};

@@ -168,10 +175,46 @@
 		#size-cells = <1>;
 		ranges;
 
+		de2 at 1000000 {
+			compatible = "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock at 0 {
+				compatible = "allwinner,sun50i-a64-de2-clk";
+				reg = <0x0 0x100000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 		syscon: syscon at 1c00000 {
-			compatible = "allwinner,sun50i-a64-system-controller",
-				"syscon";
+			compatible = "allwinner,sun50i-a64-system-control";
 			reg = <0x01c00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram at 18000 {
+				compatible = "mmio-sram";
+				reg = <0x00018000 0x28000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00018000 0x28000>;
+
+				de2_sram: sram-section at 0 {
+					compatible = "allwinner,sun50i-a64-sram-c";
+					reg = <0x0000 0x28000>;
+				};
+			};
 		};
 
 		dma: dma-controller at 1c02000 {

@@ -364,6 +407,11 @@
 				bias-pull-up;
 			};
 
+			pwm_pin: pwm_pin {
+				pins = "PD22";
+				function = "pwm";
+			};
+
 			rmii_pins: rmii_pins {
 				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 				       "PD18", "PD19", "PD20", "PD22", "PD23";

@@ -474,15 +522,6 @@
 			status = "disabled";
 		};
 
-		pwm: pwm at 1c21400 {
-			compatible = "allwinner,sun50i-a64-pwm",
-				     "allwinner,sun5i-a13-pwm";
-			reg = <0x01c21400 0x8>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-
 		uart0: serial at 1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;

@@ -617,8 +656,6 @@
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
 			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
 
 			mdio: mdio {
 				compatible = "snps,dwmac-mdio";

@@ -638,11 +675,25 @@
 			#interrupt-cells = <3>;
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01c21400 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		rtc: rtc at 1f00000 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 		};
 
 		r_intc: interrupt-controller at 1f00c00 {

@@ -664,6 +715,29 @@
 			#reset-cells = <1>;
 		};
 
+		r_i2c: i2c at 1f02400 {
+			compatible = "allwinner,sun50i-a64-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		r_pwm: pwm at 1f03800 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01f03800 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		r_pio: pinctrl at 1f02c00 {
 			compatible = "allwinner,sun50i-a64-r-pinctrl";
 			reg = <0x01f02c00 0x400>;

@@ -675,6 +749,16 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			r_i2c_pins_a: i2c-a {
+				pins = "PL8", "PL9";
+				function = "s_i2c";
+			};
+
+			r_pwm_pin: pwm {
+				pins = "PL10";
+				function = "s_pwm";
+			};
+
 			r_rsb_pins: rsb {
 				pins = "PL0", "PL1";
 				function = "s_rsb";

Signature · 1 line

2.19.0

Vasily Khoruzhick

author

2018-10-17 15:03 UTC #6 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Quoted 10 lines · PDT Vasily Khoruzhick

Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4
Signed-off-by Vasily Khoruzhick <[email protected]>

+CC Jernej

Quoted 208 lines

---
 arch/arm/dts/sun50i-a64.dtsi | 122 +++++++++++++++++++++++++++++------
 1 file changed, 103 insertions(+), 19 deletions(-)

arch/arm/dts/sun50i-a64.dtsi +103 ~~-19~~

index 7a083637c4..d3daf90a87 100644
@@ -43,9 +43,12 @@
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 	interrupt-parent = <&gic>;

@@ -57,17 +60,21 @@
 		#size-cells = <1>;
 		ranges;
 
-/*
- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- * However there is no support for this clock on A64 yet, so we depend
- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
- */
 		simplefb_lcd: framebuffer-lcd {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "mixer0-lcd0";
 			clocks = <&ccu CLK_TCON0>,
-				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+				 <&display_clocks CLK_MIXER0>;
+			status = "disabled";
+		};
+
+		simplefb_hdmi: framebuffer-hdmi {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "mixer1-lcd1-hdmi";
+			clocks = <&display_clocks CLK_MIXER1>,
+				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
 			status = "disabled";
 		};
 	};

@@ -168,10 +175,46 @@
 		#size-cells = <1>;
 		ranges;
 
+		de2 at 1000000 {
+			compatible = "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock at 0 {
+				compatible = "allwinner,sun50i-a64-de2-clk";
+				reg = <0x0 0x100000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 		syscon: syscon at 1c00000 {
-			compatible = "allwinner,sun50i-a64-system-controller",
-				"syscon";
+			compatible = "allwinner,sun50i-a64-system-control";
 			reg = <0x01c00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram at 18000 {
+				compatible = "mmio-sram";
+				reg = <0x00018000 0x28000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00018000 0x28000>;
+
+				de2_sram: sram-section at 0 {
+					compatible = "allwinner,sun50i-a64-sram-c";
+					reg = <0x0000 0x28000>;
+				};
+			};
 		};
 
 		dma: dma-controller at 1c02000 {

@@ -364,6 +407,11 @@
 				bias-pull-up;
 			};
 
+			pwm_pin: pwm_pin {
+				pins = "PD22";
+				function = "pwm";
+			};
+
 			rmii_pins: rmii_pins {
 				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 				       "PD18", "PD19", "PD20", "PD22", "PD23";

@@ -474,15 +522,6 @@
 			status = "disabled";
 		};
 
-		pwm: pwm at 1c21400 {
-			compatible = "allwinner,sun50i-a64-pwm",
-				     "allwinner,sun5i-a13-pwm";
-			reg = <0x01c21400 0x8>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-
 		uart0: serial at 1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;

@@ -617,8 +656,6 @@
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
 			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
 
 			mdio: mdio {
 				compatible = "snps,dwmac-mdio";

@@ -638,11 +675,25 @@
 			#interrupt-cells = <3>;
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01c21400 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		rtc: rtc at 1f00000 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 		};
 
 		r_intc: interrupt-controller at 1f00c00 {

@@ -664,6 +715,29 @@
 			#reset-cells = <1>;
 		};
 
+		r_i2c: i2c at 1f02400 {
+			compatible = "allwinner,sun50i-a64-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		r_pwm: pwm at 1f03800 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01f03800 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		r_pio: pinctrl at 1f02c00 {
 			compatible = "allwinner,sun50i-a64-r-pinctrl";
 			reg = <0x01f02c00 0x400>;

@@ -675,6 +749,16 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			r_i2c_pins_a: i2c-a {
+				pins = "PL8", "PL9";
+				function = "s_i2c";
+			};
+
+			r_pwm_pin: pwm {
+				pins = "PL10";
+				function = "s_pwm";
+			};
+
 			r_rsb_pins: rsb {
 				pins = "PL0", "PL1";
 				function = "s_rsb";

Jernej Škrabec

2018-10-17 15:13 UTC #7 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Hi,

Dne sreda, 17. oktober 2018 ob 17:03:23 CEST je Vasily Khoruzhick napisal(a):

Quoted 11 lines · PDT Vasily Khoruzhick

Quoted 10 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4
Signed-off-by Vasily Khoruzhick <[email protected]>

Wouldn't be best to use latest version from linux-next?

Best regards,
Jernej

Quoted 266 lines

+CC Jernej

Quoted 263 lines

---

 arch/arm/dts/sun50i-a64.dtsi | 122 +++++++++++++++++++++++++++++------
 1 file changed, 103 insertions(+), 19 deletions(-)

arch/arm/dts/sun50i-a64.dtsi +56 -8

index 7a083637c4..d3daf90a87 100644
@@ -43,9 +43,12 @@
 
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
 
+#include <dt-bindings/clock/sun8i-de2.h>
 
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 
 	interrupt-parent = <&gic>;

@@ -57,17 +60,21 @@
 
 		#size-cells = <1>;
 		ranges;
 
-/*
- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- * However there is no support for this clock on A64 yet, so we depend
- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
- */
 
 		simplefb_lcd: framebuffer-lcd {
 
 			compatible = "allwinner,simple-framebuffer",
 
 				     "simple-framebuffer";
 
 			allwinner,pipeline = "mixer0-lcd0";
 			clocks = <&ccu CLK_TCON0>,
 
-				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+				 <&display_clocks CLK_MIXER0>;
+			status = "disabled";
+		};
+
+		simplefb_hdmi: framebuffer-hdmi {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "mixer1-lcd1-hdmi";
+			clocks = <&display_clocks CLK_MIXER1>,
+				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
 
 			status = "disabled";
 
 		};
 
 	};

@@ -168,10 +175,46 @@
 
 		#size-cells = <1>;
 		ranges;
 
+		de2 at 1000000 {
+			compatible = "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock at 0 {
+				compatible = "allwinner,sun50i-a64-de2-clk";
+				reg = <0x0 0x100000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 
 		syscon: syscon at 1c00000 {
 
-			compatible = "allwinner,sun50i-a64-system-controller",
-				"syscon";
+			compatible = "allwinner,sun50i-a64-system-control";
 
 			reg = <0x01c00000 0x1000>;
 
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram at 18000 {
+				compatible = "mmio-sram";
+				reg = <0x00018000 0x28000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00018000 0x28000>;
+
+				de2_sram: sram-section at 0 {
+					compatible = "allwinner,sun50i-a64-sram-c";
+					reg = <0x0000 0x28000>;
+				};
+			};
 
 		};
 
 		dma: dma-controller at 1c02000 {

@@ -364,6 +407,11 @@
 
 				bias-pull-up;
 
 			};
 
+			pwm_pin: pwm_pin {
+				pins = "PD22";
+				function = "pwm";
+			};
+

arch/arm/dts/sun50i-a64.dtsi +0 -9

 			rmii_pins: rmii_pins {
 
 				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 
 				       "PD18", "PD19", "PD20", "PD22", "PD23";

@@ -474,15 +522,6 @@
 
 			status = "disabled";
 
 		};
 
-		pwm: pwm at 1c21400 {
-			compatible = "allwinner,sun50i-a64-pwm",
-				     "allwinner,sun5i-a13-pwm";
-			reg = <0x01c21400 0x8>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-

arch/arm/dts/sun50i-a64.dtsi +0 -2

 		uart0: serial at 1c28000 {
 
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;

@@ -617,8 +656,6 @@
 
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 
-			#address-cells = <1>;
-			#size-cells = <0>;

arch/arm/dts/sun50i-a64.dtsi +37 -0

 			mdio: mdio {
 
 				compatible = "snps,dwmac-mdio";

@@ -638,11 +675,25 @@
 
 			#interrupt-cells = <3>;
 
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01c21400 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 
 		rtc: rtc at 1f00000 {
 
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 
+			clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 
 		};
 
 		r_intc: interrupt-controller at 1f00c00 {

@@ -664,6 +715,29 @@
 
 			#reset-cells = <1>;
 
 		};
 
+		r_i2c: i2c at 1f02400 {
+			compatible = "allwinner,sun50i-a64-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		r_pwm: pwm at 1f03800 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01f03800 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+

arch/arm/dts/sun50i-a64.dtsi +10 -0

 		r_pio: pinctrl at 1f02c00 {
 
 			compatible = "allwinner,sun50i-a64-r-pinctrl";
 			reg = <0x01f02c00 0x400>;

@@ -675,6 +749,16 @@
 
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			r_i2c_pins_a: i2c-a {
+				pins = "PL8", "PL9";
+				function = "s_i2c";
+			};
+
+			r_pwm_pin: pwm {
+				pins = "PL10";
+				function = "s_pwm";
+			};
+
 
 			r_rsb_pins: rsb {

arch/arm/dts/sun50i-a64.dtsi +0 -0

 				pins = "PL0", "PL1";
 				function = "s_rsb";

Andre Przywara

2018-10-17 15:18 UTC #8 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

In reply to Vasily Khoruzhick

On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:

Hi,

Quoted 2 lines

Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:

Does this work easily without syncing the .dts files as well?

Quoted 5 lines

commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4

So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1).
I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.

Cheers,
Andre.

[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-September/602153.html

Quoted 217 lines

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/dts/sun50i-a64.dtsi | 122

+++++++++++++++++++++++++++++------ 1 file changed, 103 insertions(+), 19 deletions(-)

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..d3daf90a87 100644

arch/arm/dts/sun50i-a64.dtsi +3 -3

@@ -43,9 +43,12 @@
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 	interrupt-parent = <&gic>;

@@ -57,17 +60,21 @@
 		#size-cells = <1>;
 		ranges;
 
-/*
- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- * However there is no support for this clock on A64 yet, so we

depend
- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
- */

arch/arm/dts/sun50i-a64.dtsi +48 -3

 		simplefb_lcd: framebuffer-lcd {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "mixer0-lcd0";
 			clocks = <&ccu CLK_TCON0>,
-				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+				 <&display_clocks CLK_MIXER0>;
+			status = "disabled";
+		};
+
+		simplefb_hdmi: framebuffer-hdmi {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "mixer1-lcd1-hdmi";
+			clocks = <&display_clocks CLK_MIXER1>,
+				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
 			status = "disabled";
 		};
 	};

@@ -168,10 +175,46 @@
 		#size-cells = <1>;
 		ranges;
 
+		de2 at 1000000 {
+			compatible = "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock at 0 {
+				compatible =
 "allwinner,sun50i-a64-de2-clk";
+				reg = <0x0 0x100000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 		syscon: syscon at 1c00000 {
-			compatible =
 "allwinner,sun50i-a64-system-controller",
-				"syscon";
+			compatible =
 "allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram at 18000 {
+				compatible = "mmio-sram";
+				reg = <0x00018000 0x28000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00018000 0x28000>;
+
+				de2_sram: sram-section at 0 {
+					compatible =
 "allwinner,sun50i-a64-sram-c";
+					reg = <0x0000 0x28000>;
+				};
+			};

arch/arm/dts/sun50i-a64.dtsi +19 ~~-11~~

 		};
 
 		dma: dma-controller at 1c02000 {

@@ -364,6 +407,11 @@
 				bias-pull-up;
 			};
 
+			pwm_pin: pwm_pin {
+				pins = "PD22";
+				function = "pwm";
+			};
+
 			rmii_pins: rmii_pins {
 				pins = "PD10", "PD11", "PD13",
 "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23";

@@ -474,15 +522,6 @@
 			status = "disabled";
 		};
 
-		pwm: pwm at 1c21400 {
-			compatible = "allwinner,sun50i-a64-pwm",
-				     "allwinner,sun5i-a13-pwm";
-			reg = <0x01c21400 0x8>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-
 		uart0: serial at 1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;

@@ -617,8 +656,6 @@
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
 			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
 
 			mdio: mdio {
 				compatible = "snps,dwmac-mdio";

@@ -638,11 +675,25 @@
 			#interrupt-cells = <3>;
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01c21400 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		rtc: rtc at 1f00000 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40
 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			clock-output-names = "rtc-osc32k",
 "rtc-osc32k-out";
+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 		};

arch/arm/dts/sun50i-a64.dtsi +23 -0

 		r_intc: interrupt-controller at 1f00c00 {

@@ -664,6 +715,29 @@
 			#reset-cells = <1>;
 		};
 
+		r_i2c: i2c at 1f02400 {
+			compatible = "allwinner,sun50i-a64-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44
 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		r_pwm: pwm at 1f03800 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01f03800 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		r_pio: pinctrl at 1f02c00 {
 			compatible =

"allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>;

arch/arm/dts/sun50i-a64.dtsi +10 -0

@@ -675,6 +749,16 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			r_i2c_pins_a: i2c-a {
+				pins = "PL8", "PL9";
+				function = "s_i2c";
+			};
+
+			r_pwm_pin: pwm {
+				pins = "PL10";
+				function = "s_pwm";
+			};
+
 			r_rsb_pins: rsb {
 				pins = "PL0", "PL1";
 				function = "s_rsb";

Maxime Ripard

2018-10-17 15:29 UTC #9 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Quoted 16 lines · Andre Przywara

On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:
Hi,
Quoted 2 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:
Does this work easily without syncing the .dts files as well?
Quoted 5 lines
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4

Quoted 13 lines

So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1).
I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.

tl; dr: You want to build something robust on top of assumptions that have never been guaranteed. I'm fine with having it as a U-Boot addition, if it's what it takes.

Maxime

Signature · 3 lines

Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Andre Przywara

2018-10-17 16:54 UTC #10 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

On Wed, 17 Oct 2018 17:29:58 +0200
Maxime Ripard <[email protected]> wrote:

Hi,

Quoted 31 lines · Andre Przywara

Quoted 16 lines
On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:
Hi,
Quoted 2 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:
Does this work easily without syncing the .dts files as well?
Quoted 5 lines
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4  
Quoted 13 lines
So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1). I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.

Quoted 2 lines

tl; dr: You want to build something robust on top of assumptions that have never been guaranteed.

I just find it sad that "we do not guarantee" translates into "we actually don't even try". My understanding of your concern is that you can't rule this breakage out forever, which I can understand. But if it is possible to avoid breaking compatibility, I believe we should try this, on a case-by-case base.
We have been pretty good so far (leaving alone the MMC regulator breakage in v4.15, but A64 support was quite basic before that anyway).

Quoted 2 lines

I'm fine with having it as a U-Boot
addition, if it's what it takes.

Sounds good to me! Thanks!

I will check what's the easiest path to get the 4.20 DTs into U-Boot, considering a stopover at the Pinebook DTs, and send patches ASAP.

Cheers,
Andre.

Vasily Khoruzhick

author

2018-10-17 17:09 UTC #11 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Quoted 48 lines · Andre Przywara

On Wed, 17 Oct 2018 17:29:58 +0200
Maxime Ripard <[email protected]> wrote:
Hi,
Quoted 31 lines · Andre Przywara
Quoted 16 lines
On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:
Hi,
Quoted 2 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:
Does this work easily without syncing the .dts files as well?
Quoted 5 lines
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4
Quoted 13 lines
So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1). I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.
Quoted 2 lines
tl; dr: You want to build something robust on top of assumptions that have never been guaranteed.
I just find it sad that "we do not guarantee" translates into "we actually don't even try". My understanding of your concern is that you can't rule this breakage out forever, which I can understand. But if it is possible to avoid breaking compatibility, I believe we should try this, on a case-by-case base.
We have been pretty good so far (leaving alone the MMC regulator breakage in v4.15, but A64 support was quite basic before that anyway).

Quoted 7 lines

Quoted 2 lines
I'm fine with having it as a U-Boot
addition, if it's what it takes.
Sounds good to me! Thanks!
I will check what's the easiest path to get the 4.20 DTs into U-Boot, considering a stopover at the Pinebook DTs, and send patches ASAP.

So do you want me to wait for you to submit a patch that syncs sun50i-a64.dtsi?

Quoted 3 lines

Cheers,
Andre.

Andre Przywara

2018-10-17 17:15 UTC #12 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Quoted 54 lines · On Wed, 17 Oct 2018 10:09:55 -0700 Vasily Khoruzhick <[email protected]> wrote:

Quoted 52 lines · Andre Przywara
On Wed, 17 Oct 2018 17:29:58 +0200
Maxime Ripard <[email protected]> wrote:
Hi,
Quoted 32 lines · Andre Przywara
Quoted 16 lines
On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:
Hi,
Quoted 2 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:
Does this work easily without syncing the .dts files as well?
Quoted 5 lines
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4  
Quoted 14 lines
So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1). I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.
Quoted 2 lines
tl; dr: You want to build something robust on top of assumptions that have never been guaranteed.
I just find it sad that "we do not guarantee" translates into "we actually don't even try". My understanding of your concern is that you can't rule this breakage out forever, which I can understand. But if it is possible to avoid breaking compatibility, I believe we should try this, on a case-by-case base.
We have been pretty good so far (leaving alone the MMC regulator breakage in v4.15, but A64 support was quite basic before that anyway).
Quoted 2 lines
I'm fine with having it as a U-Boot
addition, if it's what it takes.

Quoted 8 lines

Quoted 5 lines
Sounds good to me! Thanks!
I will check what's the easiest path to get the 4.20 DTs into U-Boot, considering a stopover at the Pinebook DTs, and send patches ASAP.
So do you want me to wait for you to submit a patch that syncs sun50i-a64.dtsi?

I will review the rest of your series later tonight and try to suggest something that's the easiest for you then.

Cheers,
Andre

Vasily Khoruzhick

author

2018-10-17 15:40 UTC #13 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

In reply to Andre Przywara

Quoted 9 lines · PDT Andre Przywara

On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:
Hi,
Quoted 3 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4,
exactly Linux commit:
Does this work easily without syncing the .dts files as well?

Well, we need r_i2c node from upstream. Jernej also wants HDMI nodes. Easiest way to do that is to sync this file.

Quoted 7 lines

Quoted 6 lines
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4

Quoted 13 lines

So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1).
I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.

Can you do it with a separate patch once this one merges? I have no way to test UEFI and updating sun50i-a64.dtsi doesn't break anything for me.

Quoted 274 lines

Cheers,
Andre.

[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-September/602153.
html

Quoted 268 lines

Signed-off-by Vasily Khoruzhick <[email protected]>

---

 arch/arm/dts/sun50i-a64.dtsi | 122

+++++++++++++++++++++++++++++------ 1 file changed, 103 insertions(+), 19 deletions(-)

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..d3daf90a87 100644

arch/arm/dts/sun50i-a64.dtsi +3 -3

@@ -43,9 +43,12 @@
 
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
 
+#include <dt-bindings/clock/sun8i-de2.h>
 
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 
 	interrupt-parent = <&gic>;

@@ -57,17 +60,21 @@
 
 		#size-cells = <1>;
 		ranges;
 
-/*
- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- * However there is no support for this clock on A64 yet, so we

depend
- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
- */

arch/arm/dts/sun50i-a64.dtsi +32 -3

 		simplefb_lcd: framebuffer-lcd {
 
 			compatible = "allwinner,simple-framebuffer",
 
 				     "simple-framebuffer";
 
 			allwinner,pipeline = "mixer0-lcd0";
 			clocks = <&ccu CLK_TCON0>,
 
-				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+				 <&display_clocks CLK_MIXER0>;
+			status = "disabled";
+		};
+
+		simplefb_hdmi: framebuffer-hdmi {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "mixer1-lcd1-hdmi";
+			clocks = <&display_clocks CLK_MIXER1>,
+				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
 
 			status = "disabled";
 
 		};
 
 	};

@@ -168,10 +175,46 @@
 
 		#size-cells = <1>;
 		ranges;
 
+		de2 at 1000000 {
+			compatible = "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock at 0 {
+				compatible =
 "allwinner,sun50i-a64-de2-clk";
+				reg = <0x0 0x100000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 
 		syscon: syscon at 1c00000 {
 
-			compatible =
 "allwinner,sun50i-a64-system-controller",
-				"syscon";
+			compatible =

"allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>;

arch/arm/dts/sun50i-a64.dtsi +13 -0

+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram at 18000 {
+				compatible = "mmio-sram";
+				reg = <0x00018000 0x28000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00018000 0x28000>;
+
+				de2_sram: sram-section at 0 {
+					compatible =

"allwinner,sun50i-a64-sram-c";

arch/arm/dts/sun50i-a64.dtsi +8 -0

+					reg = <0x0000 0x28000>;
+				};
+			};
 
 		};
 
 		dma: dma-controller at 1c02000 {

@@ -364,6 +407,11 @@
 
 				bias-pull-up;
 
 			};
 
+			pwm_pin: pwm_pin {
+				pins = "PD22";
+				function = "pwm";
+			};
+

arch/arm/dts/sun50i-a64.dtsi +0 -0

 			rmii_pins: rmii_pins {
 
 				pins = "PD10", "PD11", "PD13",

"PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23";

arch/arm/dts/sun50i-a64.dtsi +0 -9

@@ -474,15 +522,6 @@
 
 			status = "disabled";
 
 		};
 
-		pwm: pwm at 1c21400 {
-			compatible = "allwinner,sun50i-a64-pwm",
-				     "allwinner,sun5i-a13-pwm";
-			reg = <0x01c21400 0x8>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-

arch/arm/dts/sun50i-a64.dtsi +0 -2

 		uart0: serial at 1c28000 {
 
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;

@@ -617,8 +656,6 @@
 
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 
-			#address-cells = <1>;
-			#size-cells = <0>;

arch/arm/dts/sun50i-a64.dtsi +11 -0

 			mdio: mdio {
 
 				compatible = "snps,dwmac-mdio";

@@ -638,11 +675,25 @@
 
 			#interrupt-cells = <3>;
 
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01c21400 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 
 		rtc: rtc at 1f00000 {
 
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40

IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/dts/sun50i-a64.dtsi +1 -0

+			clock-output-names = "rtc-osc32k",

"rtc-osc32k-out";

arch/arm/dts/sun50i-a64.dtsi +25 -0

+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 
 		};
 
 		r_intc: interrupt-controller at 1f00c00 {

@@ -664,6 +715,29 @@
 
 			#reset-cells = <1>;
 
 		};
 
+		r_i2c: i2c at 1f02400 {
+			compatible = "allwinner,sun50i-a64-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44
 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		r_pwm: pwm at 1f03800 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01f03800 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+

arch/arm/dts/sun50i-a64.dtsi +0 -0

 		r_pio: pinctrl at 1f02c00 {
 
 			compatible =

"allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>;

arch/arm/dts/sun50i-a64.dtsi +10 -0

@@ -675,6 +749,16 @@
 
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			r_i2c_pins_a: i2c-a {
+				pins = "PL8", "PL9";
+				function = "s_i2c";
+			};
+
+			r_pwm_pin: pwm {
+				pins = "PL10";
+				function = "s_pwm";
+			};
+
 
 			r_rsb_pins: rsb {

arch/arm/dts/sun50i-a64.dtsi +0 -0

 				pins = "PL0", "PL1";
 				function = "s_rsb";

André Przywara

2018-10-18 00:21 UTC #14 lore raw

PATCH v2 3/5 sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Quoted 6 lines · Vasily Khoruzhick

Quoted 5 lines · PDT Andre Przywara
On Tue, 16 Oct 2018 22:09:30 -0700
Vasily Khoruzhick <[email protected]> wrote:
Hi,

Quoted 7 lines

Quoted 4 lines
Quoted 3 lines
Updates the device tree file from the the Linux tree as of v4.19-rc4,
exactly Linux commit:
Does this work easily without syncing the .dts files as well?
Well, we need r_i2c node from upstream. Jernej also wants HDMI nodes. Easiest way to do that is to sync this file.

I understand that, but sometimes we have changes in the .dtsi that require board .dts updates at the same time (the UART pins in 4.20, for instance). This one seems to be fine, though.

Quoted 21 lines

Quoted 7 lines
Quoted 6 lines
commit 7876320f8880 (tag: v4.19-rc4)
Author: Linus Torvalds <[email protected]>
Date: Sun Sep 16 11:52:37 2018 -0700
    Linux 4.19-rc4
Quoted 13 lines
So this sounds like the right thing to do, but in this particular case breaks Ethernet with UEFI booting in all distribution installers or kernels out there (except >= Linux 4.19-rc1).
I consider this a major use case of U-Boot's DTB, so what do we do about this?
The reason is that we dropped the "syscon" compatible string at the end of the system-controller node, which older kernels rely on to find the syscon node.
I suggested to re-add this[1], but didn't have much success, unfortunately.
The easiest would be to re-add (or not remove) "syscon" for U-Boot's copy, but this would mean a deviation from the Linux DT's. I am fine with this, but would like to hear more opinions.

Quoted 1 line

Can you do it with a separate patch once this one merges?

Yes, that seems like the easiest way.

Quoted 2 lines

I have no way to
test UEFI and updating sun50i-a64.dtsi doesn't break anything for me.

You actually don't need to boot UEFI, just DON'T load some .dtb, instead pass on U-Boot's copy (this is what the automated UEFI boot does).

=> booti $kernel_addr_r - $fdtcontroladdr

This way you can boot any kernel or distribution, without requiring it to ship your particular .dtb.
And for installers: download some generic arm64 .iso image and "dd" this to a USB pen drive. Put that in a working USB socket and power on. The rest works automatically.

Cheers,
Andre.

Quoted 279 lines

Quoted 275 lines

Cheers,
Andre.

[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-September/602153.
html

Quoted 268 lines

Signed-off-by Vasily Khoruzhick <[email protected]>

---

 arch/arm/dts/sun50i-a64.dtsi | 122

+++++++++++++++++++++++++++++------ 1 file changed, 103 insertions(+), 19 deletions(-)

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..d3daf90a87 100644

arch/arm/dts/sun50i-a64.dtsi +3 -3

@@ -43,9 +43,12 @@
 
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
 
+#include <dt-bindings/clock/sun8i-de2.h>
 
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 
 	interrupt-parent = <&gic>;

@@ -57,17 +60,21 @@
 
 		#size-cells = <1>;
 		ranges;
 
-/*
- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
- * However there is no support for this clock on A64 yet, so we

depend
- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
- */

arch/arm/dts/sun50i-a64.dtsi +32 -3

 		simplefb_lcd: framebuffer-lcd {
 
 			compatible = "allwinner,simple-framebuffer",
 
 				     "simple-framebuffer";
 
 			allwinner,pipeline = "mixer0-lcd0";
 			clocks = <&ccu CLK_TCON0>,
 
-				 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+				 <&display_clocks CLK_MIXER0>;
+			status = "disabled";
+		};
+
+		simplefb_hdmi: framebuffer-hdmi {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "mixer1-lcd1-hdmi";
+			clocks = <&display_clocks CLK_MIXER1>,
+				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
 
 			status = "disabled";
 
 		};
 
 	};

@@ -168,10 +175,46 @@
 
 		#size-cells = <1>;
 		ranges;
 
+		de2 at 1000000 {
+			compatible = "allwinner,sun50i-a64-de2";
+			reg = <0x1000000 0x400000>;
+			allwinner,sram = <&de2_sram 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x1000000 0x400000>;
+
+			display_clocks: clock at 0 {
+				compatible =
 "allwinner,sun50i-a64-de2-clk";
+				reg = <0x0 0x100000>;
+				clocks = <&ccu CLK_DE>,
+					 <&ccu CLK_BUS_DE>;
+				clock-names = "mod",
+					      "bus";
+				resets = <&ccu RST_BUS_DE>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 
 		syscon: syscon at 1c00000 {
 
-			compatible =
 "allwinner,sun50i-a64-system-controller",
-				"syscon";
+			compatible =

"allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>;

arch/arm/dts/sun50i-a64.dtsi +13 -0

+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_c: sram at 18000 {
+				compatible = "mmio-sram";
+				reg = <0x00018000 0x28000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00018000 0x28000>;
+
+				de2_sram: sram-section at 0 {
+					compatible =

"allwinner,sun50i-a64-sram-c";

arch/arm/dts/sun50i-a64.dtsi +8 -0

+					reg = <0x0000 0x28000>;
+				};
+			};
 
 		};
 
 		dma: dma-controller at 1c02000 {

@@ -364,6 +407,11 @@
 
 				bias-pull-up;
 
 			};
 
+			pwm_pin: pwm_pin {
+				pins = "PD22";
+				function = "pwm";
+			};
+

arch/arm/dts/sun50i-a64.dtsi +0 -0

 			rmii_pins: rmii_pins {
 
 				pins = "PD10", "PD11", "PD13",

"PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23";

arch/arm/dts/sun50i-a64.dtsi +0 -9

@@ -474,15 +522,6 @@
 
 			status = "disabled";
 
 		};
 
-		pwm: pwm at 1c21400 {
-			compatible = "allwinner,sun50i-a64-pwm",
-				     "allwinner,sun5i-a13-pwm";
-			reg = <0x01c21400 0x8>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-

arch/arm/dts/sun50i-a64.dtsi +0 -2

 		uart0: serial at 1c28000 {
 
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;

@@ -617,8 +656,6 @@
 
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 
-			#address-cells = <1>;
-			#size-cells = <0>;

arch/arm/dts/sun50i-a64.dtsi +11 -0

 			mdio: mdio {
 
 				compatible = "snps,dwmac-mdio";

@@ -638,11 +675,25 @@
 
 			#interrupt-cells = <3>;
 
 		};
 
+		pwm: pwm at 1c21400 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01c21400 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 
 		rtc: rtc at 1f00000 {
 
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40

IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/dts/sun50i-a64.dtsi +1 -0

+			clock-output-names = "rtc-osc32k",

"rtc-osc32k-out";

arch/arm/dts/sun50i-a64.dtsi +25 -0

+			clocks = <&osc32k>;
+			#clock-cells = <1>;
 
 		};
 
 		r_intc: interrupt-controller at 1f00c00 {

@@ -664,6 +715,29 @@
 
 			#reset-cells = <1>;
 
 		};
 
+		r_i2c: i2c at 1f02400 {
+			compatible = "allwinner,sun50i-a64-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44
 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		r_pwm: pwm at 1f03800 {
+			compatible = "allwinner,sun50i-a64-pwm",
+				     "allwinner,sun5i-a13-pwm";
+			reg = <0x01f03800 0x400>;
+			clocks = <&osc24M>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_pwm_pin>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+

arch/arm/dts/sun50i-a64.dtsi +0 -0

 		r_pio: pinctrl at 1f02c00 {
 
 			compatible =

"allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>;

arch/arm/dts/sun50i-a64.dtsi +10 -0

@@ -675,6 +749,16 @@
 
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			r_i2c_pins_a: i2c-a {
+				pins = "PL8", "PL9";
+				function = "s_i2c";
+			};
+
+			r_pwm_pin: pwm {
+				pins = "PL10";
+				function = "s_pwm";
+			};
+
 
 			r_rsb_pins: rsb {

arch/arm/dts/sun50i-a64.dtsi +0 -0

 				pins = "PL0", "PL1";
 				function = "s_rsb";

Vasily Khoruzhick

author

2018-10-17 05:09 UTC #15 lore raw

PATCH v2 4/5 sun50i: A64: add support for R_I2C controller

In reply to Vasily Khoruzhick

Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict with RSB.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
 arch/arm/mach-sunxi/Kconfig            | 1 +
 board/sunxi/board.c                    | 6 ++++++
 3 files changed, 8 insertions(+)

arch/arm/include/asm/arch-sunxi/gpio.h +1 -0

index 6a5eafc3d3..2daf23f6f5 100644
@@ -211,6 +211,7 @@ enum sunxi_gpio_number {
 #define SUN8I_H3_GPL_R_TWI	2
 #define SUN8I_A23_GPL_R_TWI	3
 #define SUN8I_GPL_R_UART	2
+#define SUN50I_GPL_R_TWI	2
 
 #define SUN9I_GPN_R_RSB		3

arch/arm/mach-sunxi/Kconfig +1 -0

index 686f38fec4..7ba429c744 100644
@@ -272,6 +272,7 @@ config MACH_SUN50I
 	select ARM64
 	select DM_I2C
 	select PHY_SUN4I_USB
+	select SUN6I_PRCM
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL

board/sunxi/board.c +6 -0

index d1d7f9f400..90f8bc0a6e 100644
@@ -168,10 +168,16 @@ void i2c_init_board(void)
 #endif
 
 #ifdef CONFIG_R_I2C_ENABLE
+#ifdef CONFIG_MACH_SUN50I
+	clock_twi_onoff(5, 1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
+#else
 	clock_twi_onoff(5, 1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
 #endif
+#endif
 }
 
 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)

Signature · 1 line

2.19.0

André Przywara

2018-10-18 00:22 UTC #16 lore raw

PATCH v2 4/5 sun50i: A64: add support for R_I2C controller

Quoted 7 lines · Vasily Khoruzhick

Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has two groups of pinmuxes on PL bank, so it's called R_I2C.
Add support for this I2C controller and the pinmux which doesn't conflict with RSB.
Signed-off-by Vasily Khoruzhick <[email protected]>

Reviewed-by Andre Przywara <[email protected]>

Thanks!
Andre.

Quoted 52 lines

---
 arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
 arch/arm/mach-sunxi/Kconfig            | 1 +
 board/sunxi/board.c                    | 6 ++++++
 3 files changed, 8 insertions(+)

arch/arm/include/asm/arch-sunxi/gpio.h +1 -0

index 6a5eafc3d3..2daf23f6f5 100644
@@ -211,6 +211,7 @@ enum sunxi_gpio_number {
 #define SUN8I_H3_GPL_R_TWI	2
 #define SUN8I_A23_GPL_R_TWI	3
 #define SUN8I_GPL_R_UART	2
+#define SUN50I_GPL_R_TWI	2
 
 #define SUN9I_GPN_R_RSB		3

arch/arm/mach-sunxi/Kconfig +1 -0

index 686f38fec4..7ba429c744 100644
@@ -272,6 +272,7 @@ config MACH_SUN50I
 	select ARM64
 	select DM_I2C
 	select PHY_SUN4I_USB
+	select SUN6I_PRCM
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL

board/sunxi/board.c +6 -0

index d1d7f9f400..90f8bc0a6e 100644
@@ -168,10 +168,16 @@ void i2c_init_board(void)
 #endif
 
 #ifdef CONFIG_R_I2C_ENABLE
+#ifdef CONFIG_MACH_SUN50I
+	clock_twi_onoff(5, 1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
+#else
 	clock_twi_onoff(5, 1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
 #endif
+#endif
 }
 
 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)

Vasily Khoruzhick

author

2018-10-17 05:09 UTC #17 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

In reply to Vasily Khoruzhick

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

arch/arm/dts/Makefile +2 -1

index dfe9335a04..ccb93f1e46 100644
@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb \

arch/arm/dts/sun50i-a64-pinebook.dts new file +306 -0

306 lines not on this page · raw message

configs/pinebook_defconfig new file +27 -0

new file mode 100644
index 0000000000..f5190d96d2
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
+# CONFIG_MMC_VERBOSE is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

Signature · 1 line

2.19.0

Maxime Ripard

2018-10-17 14:37 UTC #18 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

Quoted 18 lines · Vasily Khoruzhick

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.
Signed-off-by Vasily Khoruzhick <[email protected]>
---
 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig
arch/arm/dts/Makefile +0 -0
index dfe9335a04..ccb93f1e46 100644

arch/arm/dts/Makefile dtb-$(CONFIG_MACH_SUN50I) += \ · line 408

Quoted 6 lines

arch/arm/dts/Makefile +2 -1

@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb

This should be ordered by alphabetical order. Otherwise, the whole series looks sane to me:

Acked-by Maxime Ripard <[email protected]>

Thanks!
Maxime

Signature · 3 lines

Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Vasily Khoruzhick

author

2018-10-17 15:13 UTC #19 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

In reply to Vasily Khoruzhick

Quoted 5 lines · PDT Vasily Khoruzhick

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.
Signed-off-by Vasily Khoruzhick <[email protected]>

+CC Jernej

Quoted 367 lines

---
 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

arch/arm/dts/Makefile +2 -1

index dfe9335a04..ccb93f1e46 100644
@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb \

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64-pinebook.dts new file mode 100644 index 0000000000..5d111fab64

arch/arm/dts/sun50i-a64-pinebook.dts new file +306 -0

@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
+ * Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Pinebook";
+	compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &rtl8723cs;
+	};
+
+	vdd_bl: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "bl-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+		enable-active-high;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 0>;
+		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+		default-brightness-level = <2>;
+		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+		power-supply = <&vdd_bl>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+
+		framebuffer-lcd {
+			panel-supply = <&reg_dc1sw>;
+			dvdd25-supply = <&reg_dldo2>;
+			dvdd12-supply = <&reg_fldo1>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		lid_switch {
+			label = "Lid Switch";
+			gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+	};
+
+	speaker_amp: speaker_amp {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&ehci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_dldo4>;
+	vqmmc-supply = <&reg_eldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	rtl8723cs: wifi at 1 {
+		reg = <1>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_eldo1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&ohci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp803: pmic at 3a3 {
+		compatible = "x-powers,axp803";
+		reg = <0x3a3>;
+		interrupt-parent = <&r_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+/* The ANX6345 eDP-bridge is on r_i2c */
+&r_i2c {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_i2c_pins_a>;
+	status = "okay";
+	anx6345: edp-bridge at 38 {
+		compatible = "analogix,anx6345";
+		reg = <0x38>;
+		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+		status = "okay";
+	};
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-csi";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vcc-edp";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "cpvdd";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vdd-1v8-csi";
+};
+
+&reg_fldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-usb";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+	vcc-hdmi-supply = <&reg_dldo1>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_ldo_io0>;
+	usb1_vbus-supply = <&reg_ldo_io0>;
+	status = "okay";
+};

configs/pinebook_defconfig new file +27 -0

new file mode 100644
index 0000000000..f5190d96d2
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
+# CONFIG_MMC_VERBOSE is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

Jernej Škrabec

2018-10-17 15:22 UTC #20 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

Hi!

Dne sreda, 17. oktober 2018 ob 17:13:42 CEST je Vasily Khoruzhick napisal(a):

Quoted 203 lines · PDT Vasily Khoruzhick

Quoted 5 lines

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.
Signed-off-by Vasily Khoruzhick <[email protected]>

+CC Jernej

Quoted 194 lines

---

 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

arch/arm/dts/Makefile +2 -1

index dfe9335a04..ccb93f1e46 100644
@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
 
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb

dtb-$(CONFIG_MACH_SUN9I) += \

arch/arm/dts/Makefile +0 -0

 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb \

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64-pinebook.dts new file mode 100644 index 0000000000..5d111fab64

arch/arm/dts/sun50i-a64-pinebook.dts new file +160 -0

@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
+ * Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Pinebook";
+	compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &rtl8723cs;
+	};
+
+	vdd_bl: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "bl-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+		enable-active-high;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 0>;
+		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+		default-brightness-level = <2>;
+		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+		power-supply = <&vdd_bl>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+
+		framebuffer-lcd {
+			panel-supply = <&reg_dc1sw>;
+			dvdd25-supply = <&reg_dldo2>;
+			dvdd12-supply = <&reg_fldo1>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		lid_switch {
+			label = "Lid Switch";
+			gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+	};
+
+	speaker_amp: speaker_amp {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&ehci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_dldo4>;
+	vqmmc-supply = <&reg_eldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	rtl8723cs: wifi at 1 {
+		reg = <1>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_eldo1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&ohci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp803: pmic at 3a3 {
+		compatible = "x-powers,axp803";
+		reg = <0x3a3>;
+		interrupt-parent = <&r_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+/* The ANX6345 eDP-bridge is on r_i2c */
+&r_i2c {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";

Quoted 8 lines

arch/arm/dts/sun50i-a64-pinebook.dts line 168
Quoted 8 lines
arch/arm/dts/sun50i-a64-pinebook.dts new file +8 -0
+	pinctrl-0 = <&r_i2c_pins_a>;
+	status = "okay";
+	anx6345: edp-bridge at 38 {
+		compatible = "analogix,anx6345";
+		reg = <0x38>;
+		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+		status = "okay";
+	};

Given that this node is currently U-Boot specific, wouldn't be better to leave sun50i-a64-pinebook.dts as it is in Linux and add additional sun50i-a64- pinebook-u-boot.dts with U-Boot specific nodes as it is already done with a lot of other DT files?

That way there is less chance to mistakenly left out something when syncing DT files from Linux.

Best regards,
Jernej

Quoted 171 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +138 -0

+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-csi";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vcc-edp";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "cpvdd";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vdd-1v8-csi";
+};
+
+&reg_fldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-usb";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+	vcc-hdmi-supply = <&reg_dldo1>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_ldo_io0>;
+	usb1_vbus-supply = <&reg_ldo_io0>;
+	status = "okay";
+};

configs/pinebook_defconfig new file +27 -0

new file mode 100644
index 0000000000..f5190d96d2
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
+# CONFIG_MMC_VERBOSE is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

Vasily Khoruzhick

author

2018-10-17 15:37 UTC #21 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

Quoted 3 lines · PDT Jernej Å krabec

Hi!
Dne sreda, 17. oktober 2018 ob 17:13:42 CEST je Vasily Khoruzhick

napisal(a):

Quoted 217 lines

Quoted 203 lines · PDT Vasily Khoruzhick

Quoted 5 lines

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.
Signed-off-by Vasily Khoruzhick <[email protected]>

+CC Jernej

Quoted 194 lines

---

 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

arch/arm/dts/Makefile +2 -1

index dfe9335a04..ccb93f1e46 100644
@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
 
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb

dtb-$(CONFIG_MACH_SUN9I) += \

arch/arm/dts/Makefile +0 -0

 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb \

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64-pinebook.dts new file mode 100644 index 0000000000..5d111fab64

arch/arm/dts/sun50i-a64-pinebook.dts new file +160 -0

@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
+ * Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Pinebook";
+	compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &rtl8723cs;
+	};
+
+	vdd_bl: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "bl-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+		enable-active-high;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 0>;
+		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+		default-brightness-level = <2>;
+		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+		power-supply = <&vdd_bl>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+
+		framebuffer-lcd {
+			panel-supply = <&reg_dc1sw>;
+			dvdd25-supply = <&reg_dldo2>;
+			dvdd12-supply = <&reg_fldo1>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		lid_switch {
+			label = "Lid Switch";
+			gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+	};
+
+	speaker_amp: speaker_amp {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&ehci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_dldo4>;
+	vqmmc-supply = <&reg_eldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	rtl8723cs: wifi at 1 {
+		reg = <1>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_eldo1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&ohci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp803: pmic at 3a3 {
+		compatible = "x-powers,axp803";
+		reg = <0x3a3>;
+		interrupt-parent = <&r_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+/* The ANX6345 eDP-bridge is on r_i2c */
+&r_i2c {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";

Quoted 8 lines

arch/arm/dts/sun50i-a64-pinebook.dts line 168
Quoted 8 lines
arch/arm/dts/sun50i-a64-pinebook.dts new file +8 -0
+	pinctrl-0 = <&r_i2c_pins_a>;
+	status = "okay";
+	anx6345: edp-bridge at 38 {
+		compatible = "analogix,anx6345";
+		reg = <0x38>;
+		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+		status = "okay";
+	};

Quoted 2 lines

That way there is less chance to mistakenly left out something when syncing DT files from Linux.

Sounds good, will do in v3.

Quoted 175 lines

Best regards,
Jernej

Quoted 171 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +138 -0

+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-csi";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vcc-edp";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "cpvdd";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vdd-1v8-csi";
+};
+
+&reg_fldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-usb";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+	vcc-hdmi-supply = <&reg_dldo1>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_ldo_io0>;
+	usb1_vbus-supply = <&reg_ldo_io0>;
+	status = "okay";
+};

configs/pinebook_defconfig new file +27 -0

new file mode 100644
index 0000000000..f5190d96d2
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
+# CONFIG_MMC_VERBOSE is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

André Przywara

2018-10-18 00:23 UTC #22 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

In reply to Vasily Khoruzhick

On 10/17/18 6:09 AM, Vasily Khoruzhick wrote:

Hi,

Quoted 104 lines

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.

Signed-off-by Vasily Khoruzhick <[email protected]>

---
 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

arch/arm/dts/Makefile +2 -1

index dfe9335a04..ccb93f1e46 100644
@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb \

arch/arm/dts/sun50i-a64-pinebook.dts new file +71 -0

new file mode 100644
index 0000000000..5d111fab64
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
+ * Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Pinebook";
+	compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &rtl8723cs;
+	};
+
+	vdd_bl: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "bl-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+		enable-active-high;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 0>;
+		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+		default-brightness-level = <2>;
+		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+		power-supply = <&vdd_bl>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+
+		framebuffer-lcd {
+			panel-supply = <&reg_dc1sw>;
+			dvdd25-supply = <&reg_dldo2>;
+			dvdd12-supply = <&reg_fldo1>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		lid_switch {
+			label = "Lid Switch";
+			gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};

arch/arm/dts/sun50i-a64-pinebook.dts line 81

Quoted 10 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +10 -0

+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+	};
+
+	speaker_amp: speaker_amp {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
+	};

I see that this is the only sound related node not dependent on any .dtsi nodes, but how useful is it to have it in here on its own? Shouldn't we wait until all sound nodes are agreed upon and merged?

Quoted 71 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +71 -0

+};
+
+&ehci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_dldo4>;
+	vqmmc-supply = <&reg_eldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	rtl8723cs: wifi at 1 {
+		reg = <1>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_eldo1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&ohci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp803: pmic at 3a3 {
+		compatible = "x-powers,axp803";
+		reg = <0x3a3>;
+		interrupt-parent = <&r_intc>;

arch/arm/dts/sun50i-a64-pinebook.dts line 162

Quoted 10 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +10 -0

+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+/* The ANX6345 eDP-bridge is on r_i2c */
+&r_i2c {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_i2c_pins_a>;
+	status = "okay";

Nit: please add an empty line here, to separate the slave section from the master.

arch/arm/dts/sun50i-a64-pinebook.dts line 168

Quoted 6 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +6 -0

+	anx6345: edp-bridge at 38 {
+		compatible = "analogix,anx6345";
+		reg = <0x38>;
+		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+		status = "okay";
+	};

Do you have any plans on upstreaming this binding?

Quoted 144 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +138 -0

+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-csi";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vcc-edp";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "cpvdd";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vdd-1v8-csi";
+};
+
+&reg_fldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-usb";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+	vcc-hdmi-supply = <&reg_dldo1>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_ldo_io0>;
+	usb1_vbus-supply = <&reg_ldo_io0>;
+	status = "okay";
+};

configs/pinebook_defconfig new file +0 -0

new file mode 100644
index 0000000000..f5190d96d2

configs/pinebook_defconfig line 5

Quoted 5 lines

configs/pinebook_defconfig new file +5 -0

@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y

I think you can drop this.

configs/pinebook_defconfig line 13

Quoted 8 lines

configs/pinebook_defconfig new file +8 -0

+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set

Why these two? I see that they save 219 bytes of the SPL, but the image size is still way below the limit.
So I'd prefer to not deviate from the other boards here.

configs/pinebook_defconfig line 18

Quoted 5 lines

configs/pinebook_defconfig new file +5 -0

+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
+# CONFIG_MMC_VERBOSE is not set

Why this one? Doesn't seem to affect SPL size?

Cheers,
Andre.

Quoted 10 lines

configs/pinebook_defconfig new file +9 -0

+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

Vasily Khoruzhick

author

2018-10-18 04:48 UTC #23 lore raw

PATCH v2 5/5 sunxi: DT: add support for Pinebook

On 10/17/18 6:09 AM, Vasily Khoruzhick wrote:

Hi,

Quoted 116 lines

Pinebook is a laptop produced by Pine64, with USB-connected keyboard, USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP bridge from Analogix.

Signed-off-by Vasily Khoruzhick <[email protected]>

---

 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/sun50i-a64-pinebook.dts | 306 +++++++++++++++++++++++++++
 configs/pinebook_defconfig           |  27 +++
 3 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
 create mode 100644 configs/pinebook_defconfig

arch/arm/dts/Makefile +2 -1

index dfe9335a04..ccb93f1e46 100644
@@ -404,7 +404,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
 
 	sun50i-a64-orangepi-win.dtb \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb \
 
-	sun50i-a64-sopine-baseboard.dtb
+	sun50i-a64-sopine-baseboard.dtb \
+	sun50i-a64-pinebook.dtb

dtb-$(CONFIG_MACH_SUN9I) += \

arch/arm/dts/Makefile +0 -0

 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb \

(quoted diff) +0 -0

b/arch/arm/dts/sun50i-a64-pinebook.dts new file mode 100644 index 0000000000..5d111fab64

arch/arm/dts/sun50i-a64-pinebook.dts new file +77 -0

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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
+ * Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Pinebook";
+	compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &rtl8723cs;
+	};
+
+	vdd_bl: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "bl-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+		enable-active-high;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 0>;
+		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+		default-brightness-level = <2>;
+		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+		power-supply = <&vdd_bl>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+
+		framebuffer-lcd {
+			panel-supply = <&reg_dc1sw>;
+			dvdd25-supply = <&reg_dldo2>;
+			dvdd12-supply = <&reg_fldo1>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		lid_switch {
+			label = "Lid Switch";
+			gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+	};
+

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arch/arm/dts/sun50i-a64-pinebook.dts line 81
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arch/arm/dts/sun50i-a64-pinebook.dts new file +4 -0
+	speaker_amp: speaker_amp {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
+	};
I see that this is the only sound related node not dependent on any .dtsi nodes, but how useful is it to have it in here on its own? Shouldn't we wait until all sound nodes are agreed upon and merged?

I'll drop it for v3.

Quoted 76 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +76 -0

+};
+
+&ehci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&reg_dldo4>;
+	vqmmc-supply = <&reg_eldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	rtl8723cs: wifi at 1 {
+		reg = <1>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_eldo1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&ohci0 {
+	phys = <&usbphy 0>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp803: pmic at 3a3 {
+		compatible = "x-powers,axp803";
+		reg = <0x3a3>;
+		interrupt-parent = <&r_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+/* The ANX6345 eDP-bridge is on r_i2c */

Quoted 8 lines

arch/arm/dts/sun50i-a64-pinebook.dts line 162
Quoted 5 lines
arch/arm/dts/sun50i-a64-pinebook.dts new file +5 -0
+&r_i2c {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_i2c_pins_a>;
+	status = "okay";
Nit: please add an empty line here, to separate the slave section from the master.

I'll move it to sun50i-a64-pinebook-u-boot.dtsi for v3 as Jernej suggested, so we can drop it when anx6345 merges into linux.

Quoted 9 lines

arch/arm/dts/sun50i-a64-pinebook.dts line 168
Quoted 7 lines
arch/arm/dts/sun50i-a64-pinebook.dts new file +6 -0
+	anx6345: edp-bridge at 38 {
+		compatible = "analogix,anx6345";
+		reg = <0x38>;
+		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+		status = "okay";
+	};
Do you have any plans on upstreaming this binding?

Icenowy has plans to merge it.

Quoted 144 lines

arch/arm/dts/sun50i-a64-pinebook.dts new file +138 -0

+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-csi";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vcc-edp";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "cpvdd";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vdd-1v8-csi";
+};
+
+&reg_fldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-usb";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+	vcc-hdmi-supply = <&reg_dldo1>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_ldo_io0>;
+	usb1_vbus-supply = <&reg_ldo_io0>;
+	status = "okay";
+};

configs/pinebook_defconfig new file +0 -0

new file mode 100644
index 0000000000..f5190d96d2

Quoted 8 lines

configs/pinebook_defconfig line 5
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configs/pinebook_defconfig new file +5 -0
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+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
I think you can drop this.

Quoted 4 lines

Quoted 4 lines
configs/pinebook_defconfig new file +4 -0
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

Quoted 8 lines

configs/pinebook_defconfig line 13
Quoted 4 lines
configs/pinebook_defconfig new file +4 -0
+CONFIG_R_I2C_ENABLE=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
Why these two? I see that they save 219 bytes of the SPL, but the image size is still way below the limit.
So I'd prefer to not deviate from the other boards here.

OK, I'll drop these.

Quoted 7 lines

configs/pinebook_defconfig line 18
Quoted 5 lines
configs/pinebook_defconfig new file +5 -0
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
+# CONFIG_MMC_VERBOSE is not set
Why this one? Doesn't seem to affect SPL size?

OK, will keep it.

Quoted 12 lines

Cheers,
Andre.

Quoted 9 lines

configs/pinebook_defconfig new file +9 -0

+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y