i.MX: Add i.MX8QXP support
Subsystems (12)
v6 cover i.MX: Add i.MX8QXP support
This patchset is to upstream basic i.MX8QXP and MEK board support, with some drivers update to support i.MX8QXP. The information about the processor could be found under
The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource management/thermal and etc.
V6:
This series was rebased on master and addresses some v5 review comments and additionally adds FEC support. Summary of the changes to v5 patches is below.
Patch 08/32:
- fixed error string: s/clk/iomux
Patch 09/32:
- minor coding style fix (dropped empty lines), added API functions for reading SCFW buildinfo and for reading MAC address from fuses
Patch 18/32:
- fixed typo in subject and one line over 80 chars warning
Patch 19/32:
- s/u-boot/U-Boot in comments
Added two new patches (20/34 and 21/34) for adding uclass cpu driver and extension for reading MAC address from fuses (required for FEC driver)
Extended original patch 25/32:
- added support for more I2C/ENET/UART clocks, added 'clk dump' command
- fixed to propagate error codes (if returned by sc_pm_* API) to the caller
- fixed printf formatting in debug()
- extended for clock ID range checks to differentiate between not yet supported and invalid clock IDs.
Patch 28/32:
- guard get_lpuart_clk_rate() by IS_ENABLED to prevent build issues
Patch 30/32:
- propagate error code if clk api calls fail
Patch 31/32:
- added FEC nodes and aliases
Patch 32/32:
In DTS:
- added fec1 support, pca9646 switch description on i2c1 bus with i2c slaves
- removed not used 'pinctrl-assert-gpios' property
- s/lpi1cgrp/lpi2c1grp/
- added 'dm-pre-reloc' to cpu0 node (needed for print_cpuinfo()!)
In board code:
- reworked gpio init (repaced by init via properties in DTS), dropped GPIO5_9 mux init (was unused, will be added later when adding USB support)
- added board_phy_config() for FEC0 support
- added SCFW build info output
- moved CONFIG_MXC_GPIO from board config header to defconfig
- added required FEC driver options to the board config header
- updated defconfig: enabled 'clk', 'cpu' and 'dm' commands, PHY, FEC, MII and MXC GPIO support
V5:
Addressed Lothar Waßmann's comments for patch 24 and 32. Rebased on master.
V4:
Add reviewed tag from Anatolij Gustschin
Addressed comments from Anatolig for patch "misc: add i.MX8 misc driver" Addressed comments from Anatolig for patch "misc: imx8: add scfw api impementation"
Merged the files into one
Moved one error handle to patch 4
Moved patch "arm: global_data: add scu_dev for i.MX8" to patch 7
For Fabio's comments to imx-mkimage, I'll start the porting work, but needs more time, it will be not be in this patchset.
V3:
patch 7: use CONFIG_IMX8
patch 29: use CONFIG_IMX8
patch 32: Added README with scfw_tcm.bin link added
misc: remove sc_rpc_msg_t typedef, use struct sc_rpc_msg_s in patchset.
V2:
In this V2 patchset, the SCFW API is replaced by uclass driver implementation, but the api name is not changed from scfw api. The related macro definitions are kept in different api.h file following SCFW API file structure.
Impelemnted scu misc driver to handle the low level communication between Acore and SCU.
Implemented rm/pm/pad/misc protocol code to invoke misc_call for different functionality.
The dm clk/pinctrl/power and others will invokde the protocol api to communicate with SCU.
The arch/arm/mach-imx/imx8/clock.c currently is only a dummy file to avoid build break for mxc_get_clock.
The i2c patch and common power domain patches are removed from this patchset.
The imx8 name still kept, this is because NXP marketing requires to use this name for i.MX branding.
Anatolij Gustschin (2):
imx8: cpu: add function for reading FEC MAC from fuse
imx8: cpu: add uclass based CPU driver
Peng Fan (30):
dt-bindings: pinctrl: add i.MX8QXP pads definition
dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks
definition
dt-bindings: soc: add i.MX8QXP pm and rsrc definition
imx8: add scfw macro definition
imx: add Kconfig entry for i.MX8QXP
arm: build mach-imx for i.MX8
arm: global_data: add scu_dev for i.MX8
misc: add i.MX8 misc driver
misc: imx8: add scfw api impementation
imx: boot_mode: Add FLEXSPI boot entry
imx8: add imx-regs header file
imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
imx: add i.MX8 cpu type
armv8: add cpu core helper functions
imx8: add basic cpu support
imx8: add boot device detection
imx8: implement mmc_get_env_dev
imx8: add mmu and dram related functions
imx8: add arch_cpu_init arch_cpu_init_dm
imx8: add iomux configuration api
imx8: add dummy clock
gpio: mxc_gpio: add support for i.MX8
pinctrl: Add pinctrl driver for i.MX8
power: Add power domain driver for i.MX8
clk: imx: add clk driver for i.MX8QXP
serial_lpuart: Update lpuart driver to support i.MX8
serial: lpuart: support uclass clk api
mmc: fsl_esdhc: add uclass clk support
arm: dts: introduce dtsi for i.MX8QXP
imx: add i.MX8QXP MEK board support
Ye Li (2):
serial: lpuart: Enable RX and TX FIFO
fsl_esdhc: Update usdhc driver to support i.MX8
arch/arm/Kconfig | 8 + arch/arm/Makefile | 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8-ca35.dtsi | 66 ++ arch/arm/dts/fsl-imx8dx.dtsi | 499 ++++++++++++ arch/arm/dts/fsl-imx8dxp.dtsi | 11 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246 ++++++ arch/arm/dts/fsl-imx8qxp.dtsi | 51 ++ arch/arm/include/asm/arch-imx/cpu.h | 6 + arch/arm/include/asm/arch-imx8/clock.h | 27 + arch/arm/include/asm/arch-imx8/gpio.h | 21 + arch/arm/include/asm/arch-imx8/imx-regs.h | 46 ++ arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + arch/arm/include/asm/arch-imx8/iomux.h | 40 + arch/arm/include/asm/arch-imx8/power-domain.h | 15 + arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 ++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 88 ++ .../include/asm/arch-imx8/sci/svc/misc/api.h | 30 + .../include/asm/arch-imx8/sci/svc/pad/api.h | 57 ++ .../include/asm/arch-imx8/sci/svc/pm/api.h | 44 + .../include/asm/arch-imx8/sci/svc/rm/api.h | 69 ++ arch/arm/include/asm/arch-imx8/sci/types.h | 220 +++++ arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + arch/arm/include/asm/armv8/cpu.h | 26 + arch/arm/include/asm/global_data.h | 4 + arch/arm/include/asm/mach-imx/boot_mode.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 26 + arch/arm/mach-imx/imx8/Makefile | 7 + arch/arm/mach-imx/imx8/clock.c | 21 + arch/arm/mach-imx/imx8/cpu.c | 646 +++++++++++++++ arch/arm/mach-imx/imx8/iomux.c | 43 + board/freescale/imx8qxp_mek/Kconfig | 14 + board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 ++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 ++++ board/freescale/mx8mq_evk/README | 81 ++ configs/imx8qxp_mek_defconfig | 51 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/imx/Kconfig | 6 + drivers/clk/imx/Makefile | 5 + drivers/clk/imx/clk-imx8.c | 393 +++++++++ drivers/gpio/mxc_gpio.c | 30 +- drivers/misc/Makefile | 1 + drivers/misc/imx8/Makefile | 3 + drivers/misc/imx8/scu.c | 266 ++++++ drivers/misc/imx8/scu_api.c | 367 +++++++++ drivers/mmc/fsl_esdhc.c | 34 +- drivers/pinctrl/nxp/Kconfig | 18 + drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 209 ++--- drivers/pinctrl/nxp/pinctrl-imx.h | 16 + drivers/pinctrl/nxp/pinctrl-imx8.c | 40 + drivers/pinctrl/nxp/pinctrl-scu.c | 66 ++ drivers/power/domain/Kconfig | 8 +- drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8-power-domain.c | 315 ++++++++ drivers/serial/serial_lpuart.c | 128 ++- include/configs/imx8qxp_mek.h | 157 ++++ include/dt-bindings/clock/imx8qxp-clock.h | 583 ++++++++++++++ include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 ++++++++++++++++++ include/dt-bindings/soc/imx8_pd.h | 188 +++++ include/dt-bindings/soc/imx_rsrc.h | 557 +++++++++++++ include/fsl_lpuart.h | 2 +- 67 files changed, 6931 insertions(+), 142 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h create mode 100644 arch/arm/include/asm/armv8/cpu.h create mode 100644 arch/arm/mach-imx/imx8/Kconfig create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/clock.c create mode 100644 arch/arm/mach-imx/imx8/cpu.c create mode 100644 arch/arm/mach-imx/imx8/iomux.c create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/README create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 drivers/clk/imx/Kconfig create mode 100644 drivers/clk/imx/Makefile create mode 100644 drivers/clk/imx/clk-imx8.c create mode 100644 drivers/misc/imx8/Makefile create mode 100644 drivers/misc/imx8/scu.c create mode 100644 drivers/misc/imx8/scu_api.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c create mode 100644 drivers/power/domain/imx8-power-domain.c create mode 100644 include/configs/imx8qxp_mek.h create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h
Signature · 1 line
2.17.1
PATCH v6 1/34 dt-bindings: pinctrl: add i.MX8QXP pads definition
From: Peng Fan <[email protected]>
Add i.MX8QXP pads definition
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 +++++++++++++++++++++ 1 file changed, 757 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
include/dt-bindings/pinctrl/pads-imx8qxp.h new file +757 -0
@@ -0,0 +1,757 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef _SC_PADS_H +#define _SC_PADS_H + +#define SC_P_PCIE_CTRL0_PERST_B 0/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3/* */ +#define SC_P_USB_SS3_TC0 4/* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5/* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6/* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7/* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8/* */ +#define SC_P_EMMC0_CLK 9/* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10/* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15/* */ +#define SC_P_EMMC0_DATA4 16/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20/* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22/* */ +#define SC_P_USDHC1_RESET_B 23/* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24/* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25/* */ +#define SC_P_USDHC1_WP 26/* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27/* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28/* */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29/* */ +#define SC_P_USDHC1_CLK 30/* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31/* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32/* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33/* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34/* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35/* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36/* */ +#define SC_P_ENET0_RGMII_TXC 37/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38/* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39/* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40/* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41/* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42/* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43/* */ +#define SC_P_ENET0_RGMII_RXC 44/* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45/* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46/* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47/* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49/* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50/* */ +#define SC_P_ENET0_REFCLK_125M_25M 51/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52/* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53/* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54/* */ +#define SC_P_ESAI0_FSR 55/* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56/* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57/* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58/* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59/* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60/* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61/* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62/* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63/* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64/* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65/* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66/* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67/* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68/* */ +#define SC_P_SPI3_SCK 69/* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70/* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71/* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72/* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73/* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74/* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75/* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76/* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77/* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78/* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79/* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80/* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81/* */ +#define SC_P_SAI0_TXD 82/* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83/* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84/* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85/* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86/* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87/* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88/* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89/* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90/* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91/* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92/* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93/* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94/* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95/* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96/* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97/* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98/* */ +#define SC_P_ADC_IN1 99/* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100/* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101/* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102/* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103/* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104/* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105/* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106/* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107/* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108/* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109/* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110/* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111/* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112/* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113/* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114/* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115/* */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116/* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117/* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118/* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119/* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120/* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121/* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122/* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123/* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124/* */ +#define SC_P_JTAG_TRST_B 125/* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126/* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127/* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128/* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129/* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130/* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131/* SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132/* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133/* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134/* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135/* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136/* CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137/* CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138/* CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139/* CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140/* CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141/* CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142/* CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143/* CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144/* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145/* CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146/* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147/* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148/* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149/* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150/* */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151/* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152/* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153/* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154/* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155/* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156/* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157/* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158/* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159/* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160/* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161/* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162/* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163/* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164/* */ +#define SC_P_QSPI0B_SCLK 165/* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166/* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167/* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168/* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169/* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170/* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171/* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172/* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173/* */ +/*@}*/ + +/*! +* @name Pad Mux Definitions +* format: name padid padmux +*/ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4 +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4 +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4 +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4 +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1 +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1 +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4 +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0 +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1 +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2 +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4 +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1 +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3 +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2 +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2 +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2 +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2 +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2 +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2 +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2 +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2 +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4 +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1 +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2 +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4 +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1 +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2 +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4 +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2 +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4 +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1 +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2 +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4 +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1 +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2 +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4 +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2 +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4 +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1 +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4 +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2 +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4 +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2 +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4 +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2 +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4 +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4 +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4 +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2 +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2 +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4 +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2 +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4 +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2 +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4 +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2 +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3 +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4 +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0 +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1 +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2 +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4 +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3 +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4 +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3 +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4 +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2 +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4 +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2 +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3 +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4 +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3 +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4 +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4 +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0 +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1 +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2 +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3 +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4 +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0 +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1 +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2 +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3 +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4 +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0 +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1 +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2 +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3 +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4 +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0 +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1 +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2 +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4 +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2 +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4 +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4 +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4 +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4 +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4 +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4 +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4 +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2 +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4 +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2 +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4 +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2 +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4 +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2 +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3 +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4 +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2 +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4 +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1 +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4 +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1 +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4 +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4 +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1 +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4 +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4 +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4 +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1 +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2 +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4 +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1 +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2 +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4 +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1 +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2 +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4 +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1 +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2 +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4 +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1 +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2 +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4 +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1 +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2 +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4 +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1 +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3 +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4 +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1 +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3 +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4 +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0 +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1 +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2 +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4 +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0 +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1 +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2 +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4 +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0 +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1 +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1 +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2 +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2 +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4 +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3 +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0 +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2 +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0 +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2 +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0 +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2 +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0 +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2 +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0 +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2 +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0 +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2 +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0 +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2 +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0 +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2 +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0 +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1 +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2 +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0 +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1 +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0 +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1 +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3 +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4 +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0 +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1 +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3 +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4 +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0 +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1 +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2 +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3 +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4 +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0 +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1 +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2 +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3 +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1 +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2 +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1 +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2 +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1 +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2 +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1 +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2 +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1 +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2 +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1 +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2 +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1 +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2 +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1 +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2 +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 + +#endif /* _SC_PADS_H */
Signature · 1 line
2.17.1
PATCH v6 2/34 dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8QXP clocks definition
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- include/dt-bindings/clock/imx8qxp-clock.h | 583 ++++++++++++++++++++++ 1 file changed, 583 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h
include/dt-bindings/clock/imx8qxp-clock.h new file +583 -0
@@ -0,0 +1,583 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV 7 +#define IMX8QXP_GPU0_SHADER_CLK 8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64 +#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65 +#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66 +#define IMX8QXP_LSIO_GPT0_HF_CLK 67 +#define IMX8QXP_LSIO_GPT0_CLK 68 +#define IMX8QXP_LSIO_GPT1_DIV 69 +#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70 +#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71 +#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72 +#define IMX8QXP_LSIO_GPT1_HF_CLK 73 +#define IMX8QXP_LSIO_GPT1_CLK 74 +#define IMX8QXP_LSIO_GPT2_DIV 75 +#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76 +#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77 +#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78 +#define IMX8QXP_LSIO_GPT2_HF_CLK 79 +#define IMX8QXP_LSIO_GPT2_CLK 80 +#define IMX8QXP_LSIO_GPT3_DIV 81 +#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82 +#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83 +#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84 +#define IMX8QXP_LSIO_GPT3_HF_CLK 85 +#define IMX8QXP_LSIO_GPT3_CLK 86 +#define IMX8QXP_LSIO_GPT4_DIV 87 +#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88 +#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89 +#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90 +#define IMX8QXP_LSIO_GPT4_HF_CLK 91 +#define IMX8QXP_LSIO_GPT4_CLK 92 +#define IMX8QXP_LSIO_FSPI0_DIV 93 +#define IMX8QXP_LSIO_FSPI0_HCLK 94 +#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95 +#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96 +#define IMX8QXP_LSIO_FSPI0_CLK 97 +#define IMX8QXP_LSIO_FSPI1_DIV 98 +#define IMX8QXP_LSIO_FSPI1_HCLK 99 +#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100 +#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101 +#define IMX8QXP_LSIO_FSPI1_CLK 102 +#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103 +#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104 +#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105 +#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106 +#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107 +#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108 +#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109 +#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110 +#define IMX8QXP_LSIO_ROMCP_REG_CLK 111 +#define IMX8QXP_LSIO_ROMCP_CLK 112 +#define IMX8QXP_LSIO_96KROM_CLK 113 +#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114 +#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115 + +/* ADMA SS */ +#define IMX8QXP_UART1_IPG_CLK 116 +#define IMX8QXP_UART2_IPG_CLK 117 +#define IMX8QXP_UART3_IPG_CLK 118 +#define IMX8QXP_UART1_DIV 119 +#define IMX8QXP_UART2_DIV 120 +#define IMX8QXP_UART3_DIV 121 +#define IMX8QXP_UART1_CLK 122 +#define IMX8QXP_UART2_CLK 123 +#define IMX8QXP_UART3_CLK 124 +#define IMX8QXP_SPI0_IPG_CLK 125 +#define IMX8QXP_SPI1_IPG_CLK 126 +#define IMX8QXP_SPI2_IPG_CLK 127 +#define IMX8QXP_SPI3_IPG_CLK 128 +#define IMX8QXP_SPI0_DIV 129 +#define IMX8QXP_SPI1_DIV 130 +#define IMX8QXP_SPI2_DIV 131 +#define IMX8QXP_SPI3_DIV 132 +#define IMX8QXP_SPI0_CLK 133 +#define IMX8QXP_SPI1_CLK 134 +#define IMX8QXP_SPI2_CLK 135 +#define IMX8QXP_SPI3_CLK 136 +#define IMX8QXP_CAN0_IPG_CHI_CLK 137 +#define IMX8QXP_CAN1_IPG_CHI_CLK 138 +#define IMX8QXP_CAN2_IPG_CHI_CLK 139 +#define IMX8QXP_CAN0_IPG_CLK 140 +#define IMX8QXP_CAN1_IPG_CLK 141 +#define IMX8QXP_CAN2_IPG_CLK 142 +#define IMX8QXP_CAN0_DIV 143 +#define IMX8QXP_CAN1_DIV 144 +#define IMX8QXP_CAN2_DIV 145 +#define IMX8QXP_CAN0_CLK 146 +#define IMX8QXP_CAN1_CLK 147 +#define IMX8QXP_CAN2_CLK 148 +#define IMX8QXP_I2C0_IPG_CLK 149 +#define IMX8QXP_I2C1_IPG_CLK 150 +#define IMX8QXP_I2C2_IPG_CLK 151 +#define IMX8QXP_I2C3_IPG_CLK 152 +#define IMX8QXP_I2C0_DIV 153 +#define IMX8QXP_I2C1_DIV 154 +#define IMX8QXP_I2C2_DIV 155 +#define IMX8QXP_I2C3_DIV 156 +#define IMX8QXP_I2C0_CLK 157 +#define IMX8QXP_I2C1_CLK 158 +#define IMX8QXP_I2C2_CLK 159 +#define IMX8QXP_I2C3_CLK 160 +#define IMX8QXP_FTM0_IPG_CLK 161 +#define IMX8QXP_FTM1_IPG_CLK 162 +#define IMX8QXP_FTM0_DIV 163 +#define IMX8QXP_FTM1_DIV 164 +#define IMX8QXP_FTM0_CLK 165 +#define IMX8QXP_FTM1_CLK 166 +#define IMX8QXP_ADC0_IPG_CLK 167 +#define IMX8QXP_ADC0_DIV 168 +#define IMX8QXP_ADC0_CLK 169 +#define IMX8QXP_PWM_IPG_CLK 170 +#define IMX8QXP_PWM_DIV 171 +#define IMX8QXP_PWM_CLK 172 +#define IMX8QXP_LCD_IPG_CLK 173 +#define IMX8QXP_LCD_DIV 174 +#define IMX8QXP_LCD_CLK 175 + +/* Connectivity SS */ +#define IMX8QXP_AXI_CONN_CLK_ROOT 176 +#define IMX8QXP_AHB_CONN_CLK_ROOT 177 +#define IMX8QXP_IPG_CONN_CLK_ROOT 178 +#define IMX8QXP_SDHC0_IPG_CLK 179 +#define IMX8QXP_SDHC1_IPG_CLK 180 +#define IMX8QXP_SDHC2_IPG_CLK 181 +#define IMX8QXP_SDHC0_DIV 182 +#define IMX8QXP_SDHC1_DIV 183 +#define IMX8QXP_SDHC2_DIV 184 +#define IMX8QXP_SDHC0_CLK 185 +#define IMX8QXP_SDHC1_CLK 186 +#define IMX8QXP_SDHC2_CLK 187 +#define IMX8QXP_ENET0_ROOT_DIV 188 +#define IMX8QXP_ENET0_REF_DIV 189 +#define IMX8QXP_ENET1_REF_DIV 190 +#define IMX8QXP_ENET0_BYPASS_DIV 191 +#define IMX8QXP_ENET0_RGMII_DIV 192 +#define IMX8QXP_ENET1_ROOT_DIV 193 +#define IMX8QXP_ENET1_BYPASS_DIV 194 +#define IMX8QXP_ENET1_RGMII_DIV 195 +#define IMX8QXP_ENET0_AHB_CLK 196 +#define IMX8QXP_ENET0_IPG_S_CLK 197 +#define IMX8QXP_ENET0_IPG_CLK 198 +#define IMX8QXP_ENET1_AHB_CLK 199 +#define IMX8QXP_ENET1_IPG_S_CLK 200 +#define IMX8QXP_ENET1_IPG_CLK 201 +#define IMX8QXP_ENET0_ROOT_CLK 202 +#define IMX8QXP_ENET1_ROOT_CLK 203 +#define IMX8QXP_ENET0_TX_CLK 204 +#define IMX8QXP_ENET1_TX_CLK 205 +#define IMX8QXP_ENET0_PTP_CLK 206 +#define IMX8QXP_ENET1_PTP_CLK 207 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209 +#define IMX8QXP_ENET0_RMII_TX_SEL 210 +#define IMX8QXP_ENET1_RMII_TX_SEL 211 +#define IMX8QXP_ENET0_RGMII_TX_CLK 212 +#define IMX8QXP_ENET1_RGMII_TX_CLK 213 +#define IMX8QXP_ENET0_RMII_RX_CLK 214 +#define IMX8QXP_ENET1_RMII_RX_CLK 215 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217 +#define IMX8QXP_ENET0_REF_50MHZ_CLK 218 +#define IMX8QXP_ENET1_REF_50MHZ_CLK 219 +#define IMX8QXP_GPMI_BCH_IO_DIV 220 +#define IMX8QXP_GPMI_BCH_DIV 221 +#define IMX8QXP_GPMI_APB_CLK 222 +#define IMX8QXP_GPMI_APB_BCH_CLK 223 +#define IMX8QXP_GPMI_BCH_IO_CLK 224 +#define IMX8QXP_GPMI_BCH_CLK 225 +#define IMX8QXP_APBHDMA_CLK 226 +#define IMX8QXP_USB3_ACLK_DIV 227 +#define IMX8QXP_USB3_BUS_DIV 228 +#define IMX8QXP_USB3_LPM_DIV 229 +#define IMX8QXP_USB3_IPG_CLK 230 +#define IMX8QXP_USB3_CORE_PCLK 231 +#define IMX8QXP_USB3_PHY_CLK 232 +#define IMX8QXP_USB3_ACLK 233 +#define IMX8QXP_USB3_BUS_CLK 234 +#define IMX8QXP_USB3_LPM_CLK 235 +#define IMX8QXP_USB2_OH_AHB_CLK 236 +#define IMX8QXP_USB2_OH_IPG_S_CLK 237 +#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238 +#define IMX8QXP_USB2_PHY_IPG_CLK 239 +#define IMX8QXP_EDMA_CLK 240 +#define IMX8QXP_EDMA_IPG_CLK 241 +#define IMX8QXP_MLB_HCLK 242 +#define IMX8QXP_MLB_CLK 243 +#define IMX8QXP_MLB_IPG_CLK 244 + +/* Display controller SS */ +/* DC part1 */ +#define IMX8QXP_DC_AXI_EXT_CLK 245 +#define IMX8QXP_DC_AXI_INT_CLK 246 +#define IMX8QXP_DC_CFG_CLK 247 +#define IMX8QXP_DC0_DISP0_CLK 248 +#define IMX8QXP_DC0_DISP1_CLK 249 +#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250 +#define IMX8QXP_DC0_PRG0_APB_CLK 251 +#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252 +#define IMX8QXP_DC0_PRG1_APB_CLK 253 +#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254 +#define IMX8QXP_DC0_PRG2_APB_CLK 255 +#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256 +#define IMX8QXP_DC0_PRG3_APB_CLK 257 +#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258 +#define IMX8QXP_DC0_PRG4_APB_CLK 259 +#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260 +#define IMX8QXP_DC0_PRG5_APB_CLK 261 +#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262 +#define IMX8QXP_DC0_PRG6_APB_CLK 263 +#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264 +#define IMX8QXP_DC0_PRG7_APB_CLK 265 +#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266 +#define IMX8QXP_DC0_PRG8_APB_CLK 267 +#define IMX8QXP_DC0_DPR0_APB_CLK 268 +#define IMX8QXP_DC0_DPR0_B_CLK 269 +#define IMX8QXP_DC0_RTRAM0_CLK 270 +#define IMX8QXP_DC0_RTRAM1_CLK 271 + +/* MIPI-LVDS part1 */ +#define IMX8QXP_MIPI_IPG_CLK 272 +#define IMX8QXP_MIPI0_I2C0_DIV 273 +#define IMX8QXP_MIPI0_I2C1_DIV 274 +#define IMX8QXP_MIPI0_I2C0_CLK 275 +#define IMX8QXP_MIPI0_I2C1_CLK 276 +#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277 +#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 +#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279 +#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 +#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281 +#define IMX8QXP_MIPI0_PWM_IPG_CLK 282 +#define IMX8QXP_MIPI0_PWM_32K_CLK 283 +#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 + +#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285 +#define IMX8QXP_IMG_JPEG_ENC_CLK 286 +#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287 +#define IMX8QXP_IMG_JPEG_DEC_CLK 288 +#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289 +#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290 +#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291 +#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292 +#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293 +#define IMX8QXP_IMG_PDMA_0_CLK 294 +#define IMX8QXP_IMG_PDMA_1_CLK 295 +#define IMX8QXP_IMG_PDMA_2_CLK 296 +#define IMX8QXP_IMG_PDMA_3_CLK 297 +#define IMX8QXP_IMG_PDMA_4_CLK 298 +#define IMX8QXP_IMG_PDMA_5_CLK 299 +#define IMX8QXP_IMG_PDMA_6_CLK 300 +#define IMX8QXP_IMG_PDMA_7_CLK 301 +#define IMX8QXP_IMG_AXI_CLK 302 +#define IMX8QXP_IMG_IPG_CLK 303 +#define IMX8QXP_IMG_PXL_CLK 304 + +#define IMX8QXP_CSI0_I2C0_DIV 305 +#define IMX8QXP_CSI0_PWM0_DIV 306 +#define IMX8QXP_CSI0_CORE_DIV 307 +#define IMX8QXP_CSI0_ESC_DIV 308 +#define IMX8QXP_CSI0_IPG_CLK_S 309 +#define IMX8QXP_CSI0_IPG_CLK 310 +#define IMX8QXP_CSI0_APB_CLK 311 +#define IMX8QXP_CSI0_I2C0_IPG_CLK 312 +#define IMX8QXP_CSI0_I2C0_CLK 313 +#define IMX8QXP_CSI0_PWM0_IPG_CLK 314 +#define IMX8QXP_CSI0_PWM0_CLK 315 +#define IMX8QXP_CSI0_CORE_CLK 316 +#define IMX8QXP_CSI0_ESC_CLK 317 + +#define IMX8QXP_HSIO_AXI_CLK 318 +#define IMX8QXP_HSIO_PER_CLK 319 +#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320 +#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321 +#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322 +#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323 +#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324 +#define IMX8QXP_HSIO_MISC_PER_CLK 325 +#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326 +#define IMX8QXP_HSIO_GPIO_CLK 327 +#define IMX8QXP_HSIO_PHY_X1_PCLK 328 + +#define IMX8QXP_A35_DIV 329 + +/* ACM */ +#define IMX8QXP_EXT_AUD_MCLK0 330 +#define IMX8QXP_EXT_AUD_MCLK1 331 +#define IMX8QXP_ESAI0_RX_CLK 332 +#define IMX8QXP_ESAI0_RX_HF_CLK 333 +#define IMX8QXP_ESAI0_TX_CLK 334 +#define IMX8QXP_ESAI0_TX_HF_CLK 335 +#define IMX8QXP_SPDIF0_RX 336 +#define IMX8QXP_SAI0_RX_BCLK 337 +#define IMX8QXP_SAI0_TX_BCLK 338 +#define IMX8QXP_SAI1_RX_BCLK 339 +#define IMX8QXP_SAI1_TX_BCLK 340 +#define IMX8QXP_SAI2_RX_BCLK 341 +#define IMX8QXP_SAI3_RX_BCLK 342 +#define IMX8QXP_SAI4_RX_BCLK 343 + +#define IMX8QXP_ACM_AUD_CLK0_SEL 344 +#define IMX8QXP_ACM_AUD_CLK0_CLK 345 +#define IMX8QXP_ACM_AUD_CLK1_SEL 346 +#define IMX8QXP_ACM_AUD_CLK1_CLK 347 +#define IMX8QXP_ACM_MCLKOUT0_SEL 348 +#define IMX8QXP_ACM_MCLKOUT0_CLK 349 +#define IMX8QXP_ACM_MCLKOUT1_SEL 350 +#define IMX8QXP_ACM_MCLKOUT1_CLK 351 +#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352 +#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353 +#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354 +#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355 +#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356 +#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357 +#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358 +#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359 +#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360 +#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361 +#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362 +#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363 +#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364 +#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365 +#define IMX8QXP_ACM_SAI0_MCLK_SEL 366 +#define IMX8QXP_ACM_SAI0_MCLK_CLK 367 +#define IMX8QXP_ACM_SAI1_MCLK_SEL 368 +#define IMX8QXP_ACM_SAI1_MCLK_CLK 369 +#define IMX8QXP_ACM_SAI2_MCLK_SEL 370 +#define IMX8QXP_ACM_SAI2_MCLK_CLK 371 +#define IMX8QXP_ACM_SAI3_MCLK_SEL 372 +#define IMX8QXP_ACM_SAI3_MCLK_CLK 373 +#define IMX8QXP_ACM_SAI4_MCLK_SEL 374 +#define IMX8QXP_ACM_SAI4_MCLK_CLK 375 +#define IMX8QXP_ACM_SAI5_MCLK_SEL 376 +#define IMX8QXP_ACM_SAI5_MCLK_CLK 377 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379 +#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380 +#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383 +#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384 +#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385 + +#define IMX8QXP_IPG_AUD_CLK_ROOT 386 + +/* Audio */ +#define IMX8QXP_AUD_PLL0_DIV 387 +#define IMX8QXP_AUD_PLL0 388 +#define IMX8QXP_AUD_PLL1_DIV 389 +#define IMX8QXP_AUD_PLL1 390 +#define IMX8QXP_AUD_AMIX_IPG 391 +#define IMX8QXP_AUD_ESAI_0_IPG 392 +#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393 +#define IMX8QXP_AUD_SAI_0_IPG 394 +#define IMX8QXP_AUD_SAI_0_MCLK 395 +#define IMX8QXP_AUD_SAI_1_IPG 396 +#define IMX8QXP_AUD_SAI_1_MCLK 397 +#define IMX8QXP_AUD_SAI_2_IPG 398 +#define IMX8QXP_AUD_SAI_2_MCLK 399 +#define IMX8QXP_AUD_SAI_3_IPG 400 +#define IMX8QXP_AUD_SAI_3_MCLK 401 +#define IMX8QXP_AUD_SAI_4_IPG 402 +#define IMX8QXP_AUD_SAI_4_MCLK 403 +#define IMX8QXP_AUD_SAI_5_IPG 404 +#define IMX8QXP_AUD_SAI_5_MCLK 405 +#define IMX8QXP_AUD_MQS_IPG 406 +#define IMX8QXP_AUD_MQS_HMCLK 407 +#define IMX8QXP_AUD_GPT5_IPG 408 +#define IMX8QXP_AUD_GPT5_CLKIN 409 +#define IMX8QXP_AUD_GPT6_IPG 410 +#define IMX8QXP_AUD_GPT6_CLKIN 411 +#define IMX8QXP_AUD_GPT7_IPG 412 +#define IMX8QXP_AUD_GPT7_CLKIN 413 +#define IMX8QXP_AUD_GPT8_IPG 414 +#define IMX8QXP_AUD_GPT8_CLKIN 415 +#define IMX8QXP_AUD_GPT9_IPG 416 +#define IMX8QXP_AUD_GPT9_CLKIN 417 +#define IMX8QXP_AUD_GPT10_IPG 418 +#define IMX8QXP_AUD_GPT10_CLKIN 419 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427 +#define IMX8QXP_AUD_MCLKOUT0 428 +#define IMX8QXP_AUD_MCLKOUT1 429 +#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430 +#define IMX8QXP_AUD_SPDIF_0_GCLKW 431 +#define IMX8QXP_AUD_SPDIF_0_IPG 432 +#define IMX8QXP_AUD_ASRC_0_IPG 433 +#define IMX8QXP_AUD_ASRC_1_IPG 434 +#define IMX8QXP_AUD_DSP_ADB_ACLK 435 +#define IMX8QXP_AUD_DSP_IPG 436 +#define IMX8QXP_AUD_DSP_CORE_CLK 437 +#define IMX8QXP_AUD_OCRAM_IPG 438 + +/* DC part2 */ +#define IMX8QXP_DC0_DISP0_DIV 439 +#define IMX8QXP_DC0_DISP1_DIV 440 +#define IMX8QXP_DC0_BYPASS_0_DIV 441 +#define IMX8QXP_DC0_BYPASS_1_DIV 442 +#define IMX8QXP_DC0_PLL0_DIV 443 +#define IMX8QXP_DC0_PLL1_DIV 444 +#define IMX8QXP_DC0_PLL0_CLK 445 +#define IMX8QXP_DC0_PLL1_CLK 446 + +/* MIPI-LVDS part2 */ +#define IMX8QXP_MIPI0_BYPASS_CLK 447 +#define IMX8QXP_MIPI0_PIXEL_DIV 448 +#define IMX8QXP_MIPI0_PIXEL_CLK 449 +#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450 +#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451 +#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452 +#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453 +#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454 +#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV 455 +#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV 456 +#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK 457 +#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK 458 +#define IMX8QXP_MIPI0_LIS_IPG_CLK 459 +#define IMX8QXP_MIPI1_I2C0_DIV 460 +#define IMX8QXP_MIPI1_I2C1_DIV 461 +#define IMX8QXP_MIPI1_I2C0_CLK 462 +#define IMX8QXP_MIPI1_I2C1_CLK 463 +#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 464 +#define IMX8QXP_MIPI1_I2C0_IPG_CLK 465 +#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 466 +#define IMX8QXP_MIPI1_I2C1_IPG_CLK 467 +#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 468 +#define IMX8QXP_MIPI1_PWM_IPG_CLK 469 +#define IMX8QXP_MIPI1_PWM_32K_CLK 470 +#define IMX8QXP_MIPI1_GPIO_IPG_CLK 471 +#define IMX8QXP_MIPI1_BYPASS_CLK 472 +#define IMX8QXP_MIPI1_PIXEL_DIV 473 +#define IMX8QXP_MIPI1_PIXEL_CLK 474 +#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 475 +#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 476 +#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 477 +#define IMX8QXP_MIPI1_LVDS_PHY_DIV 478 +#define IMX8QXP_MIPI1_LVDS_PHY_CLK 479 +#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV 480 +#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV 481 +#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK 482 +#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK 483 + +#define IMX8QXP_MIPI1_LIS_IPG_CLK 484 + +/* CM40 */ +#define IMX8QXP_CM40_IPG_CLK 485 +#define IMX8QXP_CM40_I2C_DIV 486 +#define IMX8QXP_CM40_I2C_CLK 487 +#define IMX8QXP_CM40_I2C_IPG_CLK 488 + +/* VPU clocks. */ +#define IMX8QXP_VPU_ENC_CLK 489 +#define IMX8QXP_VPU_DEC_CLK 490 + +/* MIPI-LVDS part3 */ +#define IMX8QXP_MIPI0_DSI_PLL_CLK 491 +#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK 492 +#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL 493 +#define IMX8QXP_MIPI0_LVDS_PHY_SEL 494 +#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL 495 +#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL 496 +#define IMX8QXP_MIPI0_DSI_PHY_SEL 498 +#define IMX8QXP_MIPI0_DSI_PHY_DIV 499 +#define IMX8QXP_MIPI0_DSI_PHY_CLK 500 +#define IMX8QXP_MIPI1_DSI_PLL_CLK 501 +#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK 502 +#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL 503 +#define IMX8QXP_MIPI1_LVDS_PHY_SEL 504 +#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL 505 +#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL 506 +#define IMX8QXP_MIPI1_DSI_PHY_SEL 507 +#define IMX8QXP_MIPI1_DSI_PHY_DIV 508 +#define IMX8QXP_MIPI1_DSI_PHY_CLK 509 + +/* DC part3 */ +#define IMX8QXP_DC0_DPR1_APB_CLK 510 +#define IMX8QXP_DC0_DPR1_B_CLK 511 + +#define IMX8QXP_CONN_PLL0_CLK 512 +#define IMX8QXP_CONN_PLL1_CLK 513 +#define IMX8QXP_SDHC0_SEL 514 +#define IMX8QXP_SDHC1_SEL 515 +#define IMX8QXP_SDHC2_SEL 516 + +/* PARALLER CSI */ +#define IMX8QXP_PARALLEL_CSI_CLK_DPLL 517 +#define IMX8QXP_PARALLEL_CSI_CLK_SEL 518 +#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV 519 +#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 520 +#define IMX8QXP_PARALLEL_CSI_IPG_CLK 521 +#define IMX8QXP_PARALLEL_CSI_MCLK_DIV 522 +#define IMX8QXP_PARALLEL_CSI_MISC0_CLK 523 + +#define IMX8QXP_MIPI0_PWM_DIV 524 +#define IMX8QXP_MIPI1_PWM_DIV 525 +#define IMX8QXP_MIPI0_PWM_CLK 526 +#define IMX8QXP_MIPI1_PWM_CLK 527 + +#define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528 +#define IMX8QXP_LSIO_MU5A_IPG_CLK 529 + +#define IMX8QXP_CLK_END 530 +#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
Signature · 1 line
2.17.1
PATCH v6 3/34 dt-bindings: soc: add i.MX8QXP pm and rsrc definition
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8QXP power and resource definition
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- include/dt-bindings/soc/imx8_pd.h | 188 ++++++++++ include/dt-bindings/soc/imx_rsrc.h | 557 +++++++++++++++++++++++++++++ 2 files changed, 745 insertions(+) create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h
include/dt-bindings/soc/imx8_pd.h new file +188 -0
@@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! +* These defines are used to indicate a resource. Resources include peripherals +* and bus masters (but not memory regions). Note items from list should +* never be changed or removed (only added to at the end of the list). +*/ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0 lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1 lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWM lvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0 dma_spi0 +#define PD_DMA_SPI_1 dma_spi1 +#define PD_DMA_SPI_2 dma_spi2 +#define PD_DMA_SPI_3 dma_spi3 +#define PD_DMA_UART0 dma_lpuart0 +#define PD_DMA_UART1 dma_lpuart1 +#define PD_DMA_UART2 dma_lpuart2 +#define PD_DMA_UART3 dma_lpuart3 +#define PD_DMA_UART4 dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0 dma_lpi2c0 +#define PD_DMA_I2C_1 dma_lpi2c1 +#define PD_DMA_I2C_2 dma_lpi2c2 +#define PD_DMA_I2C_3 dma_lpi2c3 +#define PD_DMA_I2C_4 dma_lpi2c4 +#define PD_DMA_ADC_0 dma_adc0 +#define PD_DMA_ADC_1 dma_adc1 +#define PD_DMA_FTM_0 dma_ftm0 +#define PD_DMA_FTM_1 dma_ftm1 +#define PD_DMA_CAN_0 dma_flexcan0 +#define PD_DMA_CAN_1 dma_flexcan1 +#define PD_DMA_CAN_2 dma_flexcan2 +#define PD_DMA_PWM_0 dma_pwm0 +#define PD_DMA_LCD_0 dma_lcd0 + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIO hsio_gpio + +#define PD_LCD_0 lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0 lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET_1 conn_enet1 +#define PD_CONN_MLB_0 conn_mlb0 +#define PD_CONN_DMA_4_CH0 conn_dma4_ch0 +#define PD_CONN_DMA_4_CH1 conn_dma4_ch1 +#define PD_CONN_DMA_4_CH2 conn_dma4_ch2 +#define PD_CONN_DMA_4_CH3 conn_dma4_ch3 +#define PD_CONN_DMA_4_CH4 conn_dma4_ch4 +#define PD_CONN_USB_0 conn_usb0 +#define PD_CONN_USB_1 conn_usb1 +#define PD_CONN_USB_0_PHY conn_usb0_phy +#define PD_CONN_USB_2 conn_usb2 +#define PD_CONN_USB_2_PHY conn_usb2_phy +#define PD_CONN_NAND conn_nand + +#define PD_AUDIO audio_power_domain +#define PD_AUD_SAI_0 audio_sai0 +#define PD_AUD_SAI_1 audio_sai1 +#define PD_AUD_SAI_2 audio_sai2 +#define PD_AUD_ASRC_0 audio_asrc0 +#define PD_AUD_ASRC_1 audio_asrc1 +#define PD_AUD_ESAI_0 audio_esai0 +#define PD_AUD_ESAI_1 audio_esai1 +#define PD_AUD_SPDIF_0 audio_spdif0 +#define PD_AUD_SPDIF_1 audio_spdif1 +#define PD_AUD_SAI_3 audio_sai3 +#define PD_AUD_SAI_4 audio_sai4 +#define PD_AUD_SAI_5 audio_sai5 +#define PD_AUD_SAI_6 audio_sai6 +#define PD_AUD_SAI_7 audio_sai7 +#define PD_AUD_GPT_5 audio_gpt5 +#define PD_AUD_GPT_6 audio_gpt6 +#define PD_AUD_GPT_7 audio_gpt7 +#define PD_AUD_GPT_8 audio_gpt8 +#define PD_AUD_GPT_9 audio_gpt9 +#define PD_AUD_GPT_10 audio_gpt10 +#define PD_AUD_AMIX audio_amix +#define PD_AUD_MQS_0 audio_mqs0 +#define PD_AUD_HIFI audio_hifi +#define PD_AUD_OCRAM audio_ocram +#define PD_AUD_MCLK_OUT_0 audio_mclkout0 +#define PD_AUD_MCLK_OUT_1 audio_mclkout1 +#define PD_AUD_AUDIO_PLL_0 audio_audiopll0 +#define PD_AUD_AUDIO_PLL_1 audio_audiopll1 +#define PD_AUD_AUDIO_CLK_0 audio_audioclk0 +#define PD_AUD_AUDIO_CLK_1 audio_audioclk1 + +#define PD_IMAGING imaging_power_domain +#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec +#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc +#define PD_IMAGING_PDMA0 PD_IMAGING +#define PD_IMAGING_PDMA1 imaging_pdma1 +#define PD_IMAGING_PDMA2 imaging_pdma2 +#define PD_IMAGING_PDMA3 imaging_pdma3 +#define PD_IMAGING_PDMA4 imaging_pdma4 +#define PD_IMAGING_PDMA5 imaging_pdma5 +#define PD_IMAGING_PDMA6 imaging_pdma6 +#define PD_IMAGING_PDMA7 imaging_pdma7 + +#define PD_MIPI_0_DSI mipi0_dsi_power_domain +#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0 +#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1 +#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0 +#define PD_MIPI_1_DSI mipi1_dsi_power_domain +#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0 +#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1 +#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0 + +#define PD_MIPI_CSI0 mipi_csi0_power_domain +#define PD_MIPI_CSI0_PWM mipi_csi0_pwm +#define PD_MIPI_CSI0_I2C mipi_csi0_i2c +#define PD_MIPI_CSI1 mipi_csi1_power_domain +#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm +#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c + +#define PD_HDMI hdmi_power_domain +#define PD_HDMI_I2C_0 hdmi_i2c +#define PD_HDMI_PWM_0 hdmi_pwm +#define PD_HDMI_GPIO_0 hdmi_gpio + +#define PD_HDMI_RX hdmi_rx_power_domain +#define PD_HDMI_RX_I2C hdmi_rx_i2c +#define PD_HDMI_RX_PWM hdmi_rx_pwm + +#define PD_CM40 cm40_power_domain +#define PD_CM40_I2C cm40_i2c +#define PD_CM40_INTMUX cm40_intmux + +#endif /* __DT_BINDINGS_IMX8_PD_H */
include/dt-bindings/soc/imx_rsrc.h new file +557 -0
557 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH v6 4/34 imx8: add scfw macro definition
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add SCFW macro definition.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 +++++++++++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 58 +++++ .../include/asm/arch-imx8/sci/svc/misc/api.h | 30 +++ .../include/asm/arch-imx8/sci/svc/pad/api.h | 57 +++++ .../include/asm/arch-imx8/sci/svc/pm/api.h | 44 ++++ .../include/asm/arch-imx8/sci/svc/rm/api.h | 69 ++++++ arch/arm/include/asm/arch-imx8/sci/types.h | 220 ++++++++++++++++++ 7 files changed, 636 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h
arch/arm/include/asm/arch-imx8/sci/rpc.h new file +158 -0
@@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2017-2018 NXP +* +*/ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Note: Check SCFW API Released DOC before you want to modify something */ +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER (MSG ) ((MSG)->version) +#define RPC_SIZE (MSG ) ((MSG)->size) +#define RPC_SVC (MSG ) ((MSG)->svc) +#define RPC_FUNC (MSG ) ((MSG)->func) +#define RPC_R8 (MSG ) ((MSG)->func) +#define RPC_I32 (MSG ,IDX ) ((MSG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16 (MSG ,IDX ) ((MSG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8 (MSG ,IDX ) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U32 (MSG ,IDX ) ((MSG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16 (MSG ,IDX ) ((MSG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8 (MSG ,IDX ) ((MSG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_ABORT 9U + +/* Types */ + +struct sc_rpc_msg_s { +u8 version; +u8 size; +u8 svc; +u8 func; +union { +s32 i32[(SC_RPC_MAX_MSG -1U )]; +s16 i16[(SC_RPC_MAX_MSG -1U ) *2U ]; +s8 i8[(SC_RPC_MAX_MSG -1U ) *4U ]; +u32 u32[(SC_RPC_MAX_MSG -1U )]; +u16 u16[(SC_RPC_MAX_MSG -1U ) *2U ]; +u8 u8[(SC_RPC_MAX_MSG -1U ) *4U ]; + } DATA; +}; + +/* PM RPC */ +#define PM_FUNC_UNKNOWN 0 +#define PM_FUNC_SET_SYS_POWER_MODE 19U +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U +#define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U +#define PM_FUNC_REQ_LOW_POWER_MODE 16U +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U +#define PM_FUNC_SET_CPU_RESUME 21U +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U +#define PM_FUNC_SET_CLOCK_RATE 5U +#define PM_FUNC_GET_CLOCK_RATE 6U +#define PM_FUNC_CLOCK_ENABLE 7U +#define PM_FUNC_SET_CLOCK_PARENT 14U +#define PM_FUNC_GET_CLOCK_PARENT 15U +#define PM_FUNC_RESET 13U +#define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_BOOT 8U +#define PM_FUNC_REBOOT 9U +#define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_CPU_START 11U + +/* MISC RPC */ +#define MISC_FUNC_UNKNOWN 0 +#define MISC_FUNC_SET_CONTROL 1U +#define MISC_FUNC_GET_CONTROL 2U +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U +#define MISC_FUNC_SET_DMA_GROUP 5U +#define MISC_FUNC_SECO_IMAGE_LOAD 8U +#define MISC_FUNC_SECO_AUTHENTICATE 9U +#define MISC_FUNC_SECO_FUSE_WRITE 20U +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U +#define MISC_FUNC_SECO_BUILD_INFO 24U +#define MISC_FUNC_DEBUG_OUT 10U +#define MISC_FUNC_WAVEFORM_CAPTURE 6U +#define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_UNIQUE_ID 19U +#define MISC_FUNC_SET_ARI 3U +#define MISC_FUNC_BOOT_STATUS 7U +#define MISC_FUNC_BOOT_DONE 14U +#define MISC_FUNC_OTP_FUSE_READ 11U +#define MISC_FUNC_OTP_FUSE_WRITE 17U +#define MISC_FUNC_SET_TEMP 12U +#define MISC_FUNC_GET_TEMP 13U +#define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BUTTON_STATUS 18U + +/* PAD RPC */ +#define PAD_FUNC_UNKNOWN 0 +#define PAD_FUNC_SET_MUX 1U +#define PAD_FUNC_GET_MUX 6U +#define PAD_FUNC_SET_GP 2U +#define PAD_FUNC_GET_GP 7U +#define PAD_FUNC_SET_WAKEUP 4U +#define PAD_FUNC_GET_WAKEUP 9U +#define PAD_FUNC_SET_ALL 5U +#define PAD_FUNC_GET_ALL 10U +#define PAD_FUNC_SET 15U +#define PAD_FUNC_GET 16U +#define PAD_FUNC_SET_GP_28FDSOI 11U +#define PAD_FUNC_GET_GP_28FDSOI 12U +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U + +/* RM RPC */ +#define RM_FUNC_UNKNOWN 0 +#define RM_FUNC_PARTITION_ALLOC 1U +#define RM_FUNC_SET_CONFIDENTIAL 31U +#define RM_FUNC_PARTITION_FREE 2U +#define RM_FUNC_GET_DID 26U +#define RM_FUNC_PARTITION_STATIC 3U +#define RM_FUNC_PARTITION_LOCK 4U +#define RM_FUNC_GET_PARTITION 5U +#define RM_FUNC_SET_PARENT 6U +#define RM_FUNC_MOVE_ALL 7U +#define RM_FUNC_ASSIGN_RESOURCE 8U +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U +#define RM_FUNC_SET_MASTER_SID 11U +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U +#define RM_FUNC_IS_RESOURCE_OWNED 13U +#define RM_FUNC_IS_RESOURCE_MASTER 14U +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U +#define RM_FUNC_GET_RESOURCE_INFO 16U +#define RM_FUNC_MEMREG_ALLOC 17U +#define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FREE 18U +#define RM_FUNC_FIND_MEMREG 30U +#define RM_FUNC_ASSIGN_MEMREG 19U +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U +#define RM_FUNC_IS_MEMREG_OWNED 21U +#define RM_FUNC_GET_MEMREG_INFO 22U +#define RM_FUNC_ASSIGN_PAD 23U +#define RM_FUNC_SET_PAD_MOVABLE 24U +#define RM_FUNC_IS_PAD_OWNED 25U +#define RM_FUNC_DUMP 27U + +#endif /* SC_RPC_H */
arch/arm/include/asm/arch-imx8/sci/sci.h new file +58 -0
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arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h new file +30 -0
@@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Defines for sc_misc_boot_status_t */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U/* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U/* Security violation */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_SECO_AUTH_SECO_FW 0U/* SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U/* HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U/* HDMI RX Firmware */ + +/* Defines for sc_misc_temp_t */ +#define SC_MISC_TEMP 0U/* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U/* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U/* Temp low alarm */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_AUTH_CONTAINER 0U/* Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U/* Verify image */ +#define SC_MISC_REL_CONTAINER 2U/* Release container */ + +typedef u8 sc_misc_boot_status_t ; + +#endif /* SC_MISC_API_H */
arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h new file +57 -0
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arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h new file +44 -0
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arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h new file +69 -0
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arch/arm/include/asm/arch-imx8/sci/types.h new file +220 -0
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Signature · 1 line
2.17.1
PATCH v6 5/34 imx: add Kconfig entry for i.MX8QXP
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add Kconfig entry for i.MX8QXP
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/Kconfig | 8 ++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 13 +++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Kconfig
arch/arm/Kconfig +8 -0
@@ -668,6 +668,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_IMX8 + bool "NXP i.MX8 platform" + select ARM64 + select DM + select OF_CONTROL + config ARCH_MX8M bool "NXP i.MX8M platform" select ARM64
@@ -1416,6 +1422,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" source "arch/arm/mach-imx/mx7ulp/Kconfig" +source "arch/arm/mach-imx/imx8/Kconfig" + source "arch/arm/mach-imx/mx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig"
arch/arm/mach-imx/Makefile +1 -0
@@ -141,3 +141,4 @@ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_ARCH_IMX8) += imx8/
arch/arm/mach-imx/imx8/Kconfig new file +13 -0
@@ -0,0 +1,13 @@ +if ARCH_IMX8 + +config IMX8 + bool + +config IMX8QXP + select IMX8 + bool + +config SYS_SOC + default "imx8" + +endif
Signature · 1 line
2.17.1
PATCH v6 6/34 arm: build mach-imx for i.MX8
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Build mach-imx for i.MX8
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/Makefile +1 -1
@@ -106,7 +106,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif
Signature · 1 line
2.17.1
PATCH v6 7/34 arm: global_data: add scu_dev for i.MX8
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add scu_dev for i.MX8, this will be used as a handle to communite with SCU from A35.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/global_data.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/include/asm/global_data.h +4 -0
@@ -74,6 +74,10 @@ struct arch_global_data {#if defined(CONFIG_FSL_LSCH3 ) && defined(CONFIG_SYS_FSL_HAS_DP_DDR )unsigned long mem2_clk;#endif + +#ifdef CONFIG_ARCH_IMX8 +struct udevice *scu_dev; +#endif };#include <asm-generic/global_data.h>
Signature · 1 line
2.17.1
PATCH v6 8/34 misc: add i.MX8 misc driver
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8 MISC driver to handle the communication between A35 Core and SCU.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/misc/Makefile | 1 + drivers/misc/imx8/Makefile | 3 + drivers/misc/imx8/scu.c | 266 +++++++++++++++++++++++++++++++++++++ 3 files changed, 270 insertions(+) create mode 100644 drivers/misc/imx8/Makefile create mode 100644 drivers/misc/imx8/scu.c
drivers/misc/Makefile +1 -0
@@ -20,6 +20,7 @@ obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o +obj-$(CONFIG_IMX8) += imx8/ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
drivers/misc/imx8/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += scu.o
drivers/misc/imx8/scu.c new file +266 -0
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Signature · 1 line
2.17.1
PATCH v6 9/34 misc: imx8: add scfw api impementation
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add clk/misc/pad/pm/rm scfw api implementaion for different drivers to invoke. The low level code is using misc_call to invoke imx8_scu driver.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/sci/sci.h | 30 ++ drivers/misc/imx8/Makefile | 2 +- drivers/misc/imx8/scu_api.c | 367 +++++++++++++++++++++++ 3 files changed, 398 insertions(+), 1 deletion(-) create mode 100644 drivers/misc/imx8/scu_api.c
arch/arm/include/asm/arch-imx8/sci/sci.h +30 -0
@@ -55,4 +55,34 @@ static inline int sc_err_to_linux(sc_err_t err)return ret; } +/* PM API*/ +int sc_pm_set_resource_power_mode (sc_ipc_t ipc,sc_rsrc_t resource, +sc_pm_power_mode_t mode); +int sc_pm_set_clock_rate (sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk, +sc_pm_clock_rate_t *rate); +int sc_pm_get_clock_rate (sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk, +sc_pm_clock_rate_t *rate); +int sc_pm_set_clock_rate (sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk, +sc_pm_clock_rate_t *rate); +int sc_pm_get_clock_rate (sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk, +sc_pm_clock_rate_t *rate); +int sc_pm_clock_enable (sc_ipc_t ipc,sc_rsrc_t resource,sc_pm_clk_t clk, +sc_bool_t enable,sc_bool_t autog); + +/* MISC API */ +int sc_misc_get_control (sc_ipc_t ipc,sc_rsrc_t resource,sc_ctrl_t ctrl, +u32 *val); +void sc_misc_get_boot_dev (sc_ipc_t ipc,sc_rsrc_t *boot_dev); +void sc_misc_boot_status (sc_ipc_t ipc,sc_misc_boot_status_t status); +void sc_misc_build_info (sc_ipc_t ipc,u32 *build,u32 *commit); +int sc_misc_otp_fuse_read (sc_ipc_t ipc,u32 word,u32 *val); + +/* RM API */ +sc_bool_t sc_rm_is_memreg_owned (sc_ipc_t ipc,sc_rm_mr_t mr); +int sc_rm_get_memreg_info (sc_ipc_t ipc,sc_rm_mr_t mr,sc_faddr_t *addr_start, +sc_faddr_t *addr_end); +sc_bool_t sc_rm_is_resource_owned (sc_ipc_t ipc,sc_rsrc_t resource); + +/* PAD API */ +int sc_pad_set (sc_ipc_t ipc,sc_pad_t pad,u32 val);#endif
drivers/misc/imx8/Makefile +1 -1
@@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += scu.o +obj-y += scu_api.o scu.o
drivers/misc/imx8/scu_api.c new file +367 -0
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Signature · 1 line
2.17.1
PATCH v6 10/34 imx: boot_mode: Add FLEXSPI boot entry
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/mach-imx/boot_mode.h | 1 + 1 file changed, 1 insertion(+)
arch/arm/include/asm/mach-imx/boot_mode.h +1 -0
@@ -25,6 +25,7 @@ enum boot_device {MMC4_BOOT ,NAND_BOOT ,QSPI_BOOT , +FLEXSPI_BOOT ,USB_BOOT ,UNKNOWN_BOOT , BOOT_DEV_NUM = UNKNOWN_BOOT,
Signature · 1 line
2.17.1
PATCH v6 11/34 imx8: add imx-regs header file
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add imx-regs header file to include the register base definition
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/imx-regs.h | 46 +++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h
arch/arm/include/asm/arch-imx8/imx-regs.h new file +46 -0
@@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __ASM_ARCH_IMX8_REGS_H__ +#define __ASM_ARCH_IMX8_REGS_H__ + +#define LPUART_BASE 0x5A060000 + +#define GPT1_BASE_ADDR 0x5D140000 +#define SCU_LPUART_BASE 0x33220000 +#define GPIO1_BASE_ADDR 0x5D080000 +#define GPIO2_BASE_ADDR 0x5D090000 +#define GPIO3_BASE_ADDR 0x5D0A0000 +#define GPIO4_BASE_ADDR 0x5D0B0000 +#define GPIO5_BASE_ADDR 0x5D0C0000 +#define GPIO6_BASE_ADDR 0x5D0D0000 +#define GPIO7_BASE_ADDR 0x5D0E0000 +#define GPIO8_BASE_ADDR 0x5D0F0000 +#define LPI2C1_BASE_ADDR 0x5A800000 +#define LPI2C2_BASE_ADDR 0x5A810000 +#define LPI2C3_BASE_ADDR 0x5A820000 +#define LPI2C4_BASE_ADDR 0x5A830000 +#define LPI2C5_BASE_ADDR 0x5A840000 + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x56240000 +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B810000 +#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define PASS_OVER_INFO_ADDR 0x0010fe00 + +#define USB_BASE_ADDR 0x5b0d0000 +#define USB_PHY0_BASE_ADDR 0x5b100000 + +#endif /* __ASM_ARCH_IMX8_REGS_H__ */
Signature · 1 line
2.17.1
PATCH v6 12/34 imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Include i.MX8QXP pin header when CONFIG_IMX8QXP defined, if no SoC macro defined, report error.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h
arch/arm/include/asm/arch-imx8/imx8-pins.h new file +15 -0
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QXP ) +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */
Signature · 1 line
2.17.1
PATCH v6 13/34 imx: add i.MX8 cpu type
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros.
Signed-off-by Peng Fan <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx/cpu.h | 5 +++++ arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++ 2 files changed, 8 insertions(+)
arch/arm/include/asm/arch-imx/cpu.h +5 -0
@@ -25,12 +25,14 @@#define MXC_CPU_MX7S 0x71/* dummy ID */ #define MXC_CPU_MX7D 0x72#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP 0x92/* dummy ID */ #define MXC_CPU_MX7ULP 0xE1/* Temporally hard code */ #define MXC_CPU_VF610 0xF6/* dummy ID */ #define MXC_SOC_MX6 0x60#define MXC_SOC_MX7 0x70#define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8 0x90/* dummy */ #define MXC_SOC_MX7ULP 0xE0/* dummy */ #define CHIP_REV_1_0 0x10
@@ -41,6 +43,9 @@#define CHIP_REV_2_5 0x25#define CHIP_REV_3_0 0x30 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 +#define BOARD_REV_1_0 0x0#define BOARD_REV_2_0 0x1#define BOARD_VER_OFFSET 0x8
arch/arm/include/asm/mach-imx/sys_proto.h +3 -0
@@ -27,6 +27,7 @@#define is_mx6 () (is_soc_type(MXC_SOC_MX6))#define is_mx7 () (is_soc_type(MXC_SOC_MX7))#define is_mx8m () (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8 () (is_soc_type(MXC_SOC_IMX8))#define is_mx6dqp () (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))#define is_mx6dq () (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
@@ -41,6 +42,8 @@#define is_mx7ulp () (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8qxp () (is_cpu_type(MXC_CPU_IMX8QXP)) +#ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28)
Signature · 1 line
2.17.1
PATCH v6 14/34 armv8: add cpu core helper functions
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add helper functions to identify different armv8 variants.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/armv8/cpu.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/arm/include/asm/armv8/cpu.h
arch/arm/include/asm/armv8/cpu.h new file +26 -0
@@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << 0x4) + +static inline unsigned int read_midr (void ) +{ +unsigned long val; + + asmvolatile ("mrs %0, midr_el1" :"=r" (val)); + +return val; +} + +#define is_cortex_a35 () (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) +#define is_cortex_a53 () (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) +#define is_cortex_a72 () (((read_midr() & MIDR_PARTNUM_MASK) >>\ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
Signature · 1 line
2.17.1
PATCH v6 15/34 imx8: add basic cpu support
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add basic cpu support, including cpu revision, cpu type, cpu core detection.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/mach-imx/imx8/Makefile | 7 +++ arch/arm/mach-imx/imx8/cpu.c | 93 +++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/cpu.c
arch/arm/mach-imx/imx8/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o
arch/arm/mach-imx/imx8/cpu.c new file +93 -0
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2.17.1
PATCH v6 16/34 imx8: add boot device detection
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add get_boot_device to detect boot device.
Add print_bootinfo to print the boot device info.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/sys_proto.h | 10 +++ arch/arm/mach-imx/imx8/cpu.c | 85 ++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h
arch/arm/include/asm/arch-imx8/sys_proto.h new file +10 -0
@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#include <asm/mach-imx/sys_proto.h> +#include <linux/types.h> + +enum boot_device get_boot_device (void ); +int print_bootinfo (void );
arch/arm/mach-imx/imx8/cpu.c +85 -0
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2.17.1
PATCH v6 17/34 imx8: implement mmc_get_env_dev
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Implement mmc_get_env_dev for i.MX8.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/mach-imx/imx8/cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
arch/arm/mach-imx/imx8/cpu.c +32 -0
@@ -176,3 +176,35 @@ enum boot_device get_boot_device(void)return boot_dev; } + +#ifdef CONFIG_ENV_IS_IN_MMC +__weak int board_mmc_get_env_dev (int devno) +{ +return CONFIG_SYS_MMC_ENV_DEV ; +} + +int mmc_get_env_dev (void ) +{ +sc_rsrc_t dev_rsrc; +int devno; + +sc_misc_get_boot_dev (-1 , &dev_rsrc); + +switch (dev_rsrc) { +case SC_R_SDHC_0 : + devno =0 ; +break ; +case SC_R_SDHC_1 : + devno =1 ; +break ; +case SC_R_SDHC_2 : + devno =2 ; +break ; +default : +/* If not boot from sd/mmc, use default value */ +return CONFIG_SYS_MMC_ENV_DEV ; + } + +return board_mmc_get_env_dev (devno); +} +#endif
Signature · 1 line
2.17.1
PATCH v6 18/34 imx8: add mmu and dram related functions
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add mmu memmap, some memory regions are reserved by M4, Arm Trusted Firmware, so need to get memreg using SCFW API and setup the memmap.
Add dram_init, dram_init_banksize, get_effective_memsize functions, according to the memreg.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/mach-imx/imx8/cpu.c | 284 +++++++++++++++++++++++++++++++++++ 1 file changed, 284 insertions(+)
arch/arm/mach-imx/imx8/cpu.c +284 -0
@@ -14,6 +14,7 @@#include <asm/arch/sys_proto.h> #include <asm/arch-imx/cpu.h> #include <asm/armv8/cpu.h> +#include <asm/armv8/mmu.h> #include <asm/mach-imx/boot_mode.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -208,3 +209,286 @@ int mmc_get_env_dev(void)return board_mmc_get_env_dev (devno); }#endif + +#define MEMSTART_ALIGNMENT SZ_2M/* Align the memory start with 2MB */ + +static int get_owned_memreg (sc_rm_mr_t mr,sc_faddr_t *addr_start, +sc_faddr_t *addr_end) +{ +sc_faddr_t start, end; +int ret; +bool owned; + + owned =sc_rm_is_memreg_owned (-1 , mr); +if (owned) { + ret =sc_rm_get_memreg_info (-1 , mr, &start, &end); +if (ret) { +printf ("Memreg get info failed, %d\n" , ret); +return -EINVAL ; + } +debug ("0x%llx -- 0x%llx\n" , start, end); + *addr_start = start; + *addr_end = end; + +return 0 ; + } + +return -EINVAL ; +} + +phys_size_t get_effective_memsize (void ) +{ +sc_rm_mr_t mr; +sc_faddr_t start, end, end1; +int err; + + end1 = (sc_faddr_t )PHYS_SDRAM_1 +PHYS_SDRAM_1_SIZE ; + +for (mr =0 ; mr <64 ; mr++) { + err =get_owned_memreg (mr, &start, &end); +if (!err) { + start =roundup (start,MEMSTART_ALIGNMENT ); +/* Too small memory region, not use it */ +if (start > end) +continue ; + +/* Find the memory region runs the u-boot */ +if (start >=PHYS_SDRAM_1 && start <= end1 && + (start <=CONFIG_SYS_TEXT_BASE && + end >=CONFIG_SYS_TEXT_BASE )) { +if ((end +1 ) <= ((sc_faddr_t )PHYS_SDRAM_1 + +PHYS_SDRAM_1_SIZE )) +return (end -PHYS_SDRAM_1 +1 ); +else +return PHYS_SDRAM_1_SIZE ; + } + } + } + +return PHYS_SDRAM_1_SIZE ; +} + +int dram_init (void ) +{ +sc_rm_mr_t mr; +sc_faddr_t start, end, end1, end2; +int err; + + end1 = (sc_faddr_t )PHYS_SDRAM_1 +PHYS_SDRAM_1_SIZE ; + end2 = (sc_faddr_t )PHYS_SDRAM_2 +PHYS_SDRAM_2_SIZE ; +for (mr =0 ; mr <64 ; mr++) { + err =get_owned_memreg (mr, &start, &end); +if (!err) { + start =roundup (start,MEMSTART_ALIGNMENT ); +/* Too small memory region, not use it */ +if (start > end) +continue ; + +if (start >=PHYS_SDRAM_1 && start <= end1) { +if ((end +1 ) <= end1) + gd->ram_size += end - start +1 ; +else + gd->ram_size += end1 - start; + }else if (start >=PHYS_SDRAM_2 && start <= end2) { +if ((end +1 ) <= end2) + gd->ram_size += end - start +1 ; +else + gd->ram_size += end2 - start; + } + } + } + +/* If error, set to the default value */ +if (!gd->ram_size) { + gd->ram_size =PHYS_SDRAM_1_SIZE ; + gd->ram_size +=PHYS_SDRAM_2_SIZE ; + } +return 0 ; +} + +static void dram_bank_sort (int current_bank) +{ +phys_addr_t start; +phys_size_t size; + +while (current_bank >0 ) { +if (gd->bd->bi_dram[current_bank -1 ].start > + gd->bd->bi_dram[current_bank].start) { + start = gd->bd->bi_dram[current_bank -1 ].start; + size = gd->bd->bi_dram[current_bank -1 ].size; + + gd->bd->bi_dram[current_bank -1 ].start = + gd->bd->bi_dram[current_bank].start; + gd->bd->bi_dram[current_bank -1 ].size = + gd->bd->bi_dram[current_bank].size; + + gd->bd->bi_dram[current_bank].start = start; + gd->bd->bi_dram[current_bank].size = size; + } + current_bank--; + } +} + +int dram_init_banksize (void ) +{ +sc_rm_mr_t mr; +sc_faddr_t start, end, end1, end2; +int i =0 ; +int err; + + end1 = (sc_faddr_t )PHYS_SDRAM_1 +PHYS_SDRAM_1_SIZE ; + end2 = (sc_faddr_t )PHYS_SDRAM_2 +PHYS_SDRAM_2_SIZE ; + +for (mr =0 ; mr <64 && i <CONFIG_NR_DRAM_BANKS ; mr++) { + err =get_owned_memreg (mr, &start, &end); +if (!err) { + start =roundup (start,MEMSTART_ALIGNMENT ); +if (start > end)/* Small memory region, no use it */ +continue ; + +if (start >=PHYS_SDRAM_1 && start <= end1) { + gd->bd->bi_dram[i].start = start; + +if ((end +1 ) <= end1) + gd->bd->bi_dram[i].size = + end - start +1 ; +else + gd->bd->bi_dram[i].size = end1 - start; + +dram_bank_sort (i); + i++; + }else if (start >=PHYS_SDRAM_2 && start <= end2) { + gd->bd->bi_dram[i].start = start; + +if ((end +1 ) <= end2) + gd->bd->bi_dram[i].size = + end - start +1 ; +else + gd->bd->bi_dram[i].size = end2 - start; + +dram_bank_sort (i); + i++; + } + } + } + +/* If error, set to the default value */ +if (!i) { + gd->bd->bi_dram[0 ].start =PHYS_SDRAM_1 ; + gd->bd->bi_dram[0 ].size =PHYS_SDRAM_1_SIZE ; + gd->bd->bi_dram[1 ].start =PHYS_SDRAM_2 ; + gd->bd->bi_dram[1 ].size =PHYS_SDRAM_2_SIZE ; + } + +return 0 ; +} + +static u64 get_block_attrs (sc_faddr_t addr_start) +{ +u64 attr =PTE_BLOCK_MEMTYPE (MT_DEVICE_NGNRNE ) |PTE_BLOCK_NON_SHARE | +PTE_BLOCK_PXN |PTE_BLOCK_UXN ; + +if ((addr_start >=PHYS_SDRAM_1 && + addr_start <= ((sc_faddr_t )PHYS_SDRAM_1 +PHYS_SDRAM_1_SIZE )) || + (addr_start >=PHYS_SDRAM_2 && + addr_start <= ((sc_faddr_t )PHYS_SDRAM_2 +PHYS_SDRAM_2_SIZE ))) +return (PTE_BLOCK_MEMTYPE (MT_NORMAL ) |PTE_BLOCK_OUTER_SHARE ); + +return attr; +} + +static u64 get_block_size (sc_faddr_t addr_start,sc_faddr_t addr_end) +{ +sc_faddr_t end1, end2; + + end1 = (sc_faddr_t )PHYS_SDRAM_1 +PHYS_SDRAM_1_SIZE ; + end2 = (sc_faddr_t )PHYS_SDRAM_2 +PHYS_SDRAM_2_SIZE ; + +if (addr_start >=PHYS_SDRAM_1 && addr_start <= end1) { +if ((addr_end +1 ) > end1) +return end1 - addr_start; + }else if (addr_start >=PHYS_SDRAM_2 && addr_start <= end2) { +if ((addr_end +1 ) > end2) +return end2 - addr_start; + } + +return (addr_end - addr_start +1 ); +} + +#define MAX_PTE_ENTRIES 512 +#define MAX_MEM_MAP_REGIONS 16 + +static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS ]; +struct mm_region *mem_map = imx8_mem_map; + +void enable_caches (void ) +{ +sc_rm_mr_t mr; +sc_faddr_t start, end; +int err, i; + +/* Create map for registers access from 0x1c000000 to 0x80000000*/ + imx8_mem_map[0 ].virt =0x1c000000UL ; + imx8_mem_map[0 ].phys =0x1c000000UL ; + imx8_mem_map[0 ].size =0x64000000UL ; + imx8_mem_map[0 ].attrs =PTE_BLOCK_MEMTYPE (MT_DEVICE_NGNRNE ) | +PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN |PTE_BLOCK_UXN ; + + i =1 ; +for (mr =0 ; mr <64 && i <MAX_MEM_MAP_REGIONS ; mr++) { + err =get_owned_memreg (mr, &start, &end); +if (!err) { + imx8_mem_map[i].virt = start; + imx8_mem_map[i].phys = start; + imx8_mem_map[i].size =get_block_size (start, end); + imx8_mem_map[i].attrs =get_block_attrs (start); + i++; + } + } + +if (i <MAX_MEM_MAP_REGIONS ) { + imx8_mem_map[i].size =0 ; + imx8_mem_map[i].attrs =0 ; + }else { +puts ("Error, need more MEM MAP REGIONS reserved\n" ); +icache_enable (); +return ; + } + +for (i =0 ; i <MAX_MEM_MAP_REGIONS ; i++) { +debug ("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n" , + i, imx8_mem_map[i].virt, imx8_mem_map[i].phys, + imx8_mem_map[i].size, imx8_mem_map[i].attrs); + } + +icache_enable (); +dcache_enable (); +} + +#ifndef CONFIG_SYS_DCACHE_OFF +u64 get_page_table_size (void ) +{ +u64 one_pt =MAX_PTE_ENTRIES *sizeof (u64); +u64 size =0 ; + +/* +* For each memory region, the max table size: +* 2 level 3 tables + 2 level 2 tables + 1 level 1 table +*/ + size = (2 +2 +1 ) * one_pt *MAX_MEM_MAP_REGIONS + one_pt; + +/* +* We need to duplicate our page table once to have an emergency pt to +* resort to when splitting page tables later on +*/ + size *=2 ; + +/* +* We may need to split page tables later on if dcache settings change, +* so reserve up to 4 (random pick) page tables for that. +*/ + size += one_pt *4 ; + +return size; +} +#endif
Signature · 1 line
2.17.1
PATCH v6 19/34 imx8: add arch_cpu_init arch_cpu_init_dm
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/sys_proto.h | 9 ++++ arch/arm/mach-imx/imx8/cpu.c | 53 +++++++++++++++++++++- 2 files changed, 61 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-imx8/sys_proto.h +9 -0
@@ -6,5 +6,14 @@#include <asm/mach-imx/sys_proto.h> #include <linux/types.h> +struct pass_over_info_t { +u16 barker; +u16 len; +u32 g_bt_cfg_shadow; +u32 card_address_mode; +u32 bad_block_count_met; +u32 g_ap_mu; +}; +enum boot_device get_boot_device (void );int print_bootinfo (void );
arch/arm/mach-imx/imx8/cpu.c +52 -1
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2.17.1
PATCH v6 20/34 imx8: cpu: add function for reading FEC MAC from fuse
In reply to Anatolij GustschinFEC driver requires imx_get_mac_from_fuse(). Add it in preparation for ENETx support.
Signed-off-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/mach-imx/imx8/cpu.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
arch/arm/mach-imx/imx8/cpu.c +38 -0
@@ -543,3 +543,41 @@ u64 get_page_table_size(void)return size; }#endif + +#define FUSE_MAC0_WORD0 708 +#define FUSE_MAC0_WORD1 709 +#define FUSE_MAC1_WORD0 710 +#define FUSE_MAC1_WORD1 711 + +void imx_get_mac_from_fuse (int dev_id,unsigned char *mac) +{ +u32 word[2 ], val[2 ] = {}; +int i, ret; + +if (dev_id ==0 ) { + word[0 ] =FUSE_MAC0_WORD0 ; + word[1 ] =FUSE_MAC0_WORD1 ; + }else { + word[0 ] =FUSE_MAC1_WORD0 ; + word[1 ] =FUSE_MAC1_WORD1 ; + } + +for (i =0 ; i <2 ; i++) { + ret =sc_misc_otp_fuse_read (-1 , word[i], &val[i]); +if (ret <0 ) + goto err; + } + + mac[0 ] = val[0 ]; + mac[1 ] = val[0 ] >>8 ; + mac[2 ] = val[0 ] >>16 ; + mac[3 ] = val[0 ] >>24 ; + mac[4 ] = val[1 ]; + mac[5 ] = val[1 ] >>8 ; + +debug ("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n" , + __func__, dev_id, mac[0 ], mac[1 ], mac[2 ], mac[3 ], mac[4 ], mac[5 ]); +return ; +err: +printf ("%s: fuse %d, err: %d\n" , __func__, word[i], ret); +}
Signature · 1 line
2.17.1
Peng Fan
reviewerPATCH v6 20/34 imx8: cpu: add function for reading FEC MAC from fuse
Hi Anatolij,
Quoted 51 lines
-----Original Message-----
From: Anatolij Gustschin [mailto:agust at denx.de]
Sent: 2018年10月18日 20:28
To: u-boot at lists.denx.de; Peng Fan <[email protected]>; sbabic at denx.de
Subject: [PATCH v6 20/34] imx8: cpu: add function for reading FEC MAC from fuseFEC driver requires
imx_get_mac_from_fuse(). Add it in preparation for ENETx support.Signed-off-by Anatolij Gustschin <[email protected]>Cc Stefano Babic <[email protected]>--- arch/arm/mach-imx/imx8/cpu.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)arch/arm/mach-imx/imx8/cpu.c +26
-0@@ -543,3 +543,41 @@ u64 get_page_table_size(void)return size; }#endif + +#define FUSE_MAC0_WORD0 708 +#define FUSE_MAC0_WORD1 709 +#define FUSE_MAC1_WORD0 710 +#define FUSE_MAC1_WORD1 711 + +void imx_get_mac_from_fuse (int dev_id,unsigned char *mac) { +u32 word[2 ], val[2 ] = {}; +int i, ret; + +if (dev_id ==0 ) { + word[0 ] =FUSE_MAC0_WORD0 ; + word[1 ] =FUSE_MAC0_WORD1 ; + }else { + word[0 ] =FUSE_MAC1_WORD0 ; + word[1 ] =FUSE_MAC1_WORD1 ; + } + +for (i =0 ; i <2 ; i++) { + ret =sc_misc_otp_fuse_read (-1 , word[i], &val[i]); +if (ret <0 ) + goto err; + } + + mac[0 ] = val[0 ]; + mac[1 ] = val[0 ] >>8 ;
arch/arm/mach-imx/imx8/cpu.c u64 get_page_table_size(void) · line 581
Quoted 10 lines
arch/arm/mach-imx/imx8/cpu.c +10
-0+ mac[2 ] = val[0 ] >>16 ; + mac[3 ] = val[0 ] >>24 ; + mac[4 ] = val[1 ]; + mac[5 ] = val[1 ] >>8 ; + +debug ("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n" , + __func__, dev_id, mac[0 ], mac[1 ], mac[2 ], mac[3 ], mac[4 ], mac[5 ]); +return ; +err: +printf ("%s: fuse %d, err: %d\n" , __func__, word[i], ret); }
Reviewed-by Peng Fan <[email protected]>
Thanks,
Peng.
Quoted 2 lines
--
2.17.1
PATCH v6 21/34 imx8: cpu: add uclass based CPU driver
In reply to Anatolij Gustschinprint_cpuinfo() in board init code requires uclass CPU driver, add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO option is enabled. CPU node in DT will have to include 'clocks' and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo() to work as expected. The driver outputs info for i.MX8QXP Rev A and Rev B CPUs.
Signed-off-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx/cpu.h | 5 +- arch/arm/mach-imx/imx8/cpu.c | 215 ++++++++++++++++++---------- 2 files changed, 142 insertions(+), 78 deletions(-)
arch/arm/include/asm/arch-imx/cpu.h +3 -2
@@ -25,6 +25,7 @@#define MXC_CPU_MX7S 0x71/* dummy ID */ #define MXC_CPU_MX7D 0x72#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP_A0 0x90/* dummy ID */ #define MXC_CPU_IMX8QXP 0x92/* dummy ID */ #define MXC_CPU_MX7ULP 0xE1/* Temporally hard code */ #define MXC_CPU_VF610 0xF6/* dummy ID */
@@ -43,8 +44,8 @@#define CHIP_REV_2_5 0x25#define CHIP_REV_3_0 0x30 -#define CHIP_REV_A 0x0 -#define CHIP_REV_B 0x1 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1#define BOARD_REV_1_0 0x0#define BOARD_REV_2_0 0x1
arch/arm/mach-imx/imx8/cpu.c +139 -76
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Signature · 1 line
2.17.1
Peng Fan
reviewerPATCH v6 21/34 imx8: cpu: add uclass based CPU driver
Hi Anatolij,
Quoted 265 lines
-----Original Message-----
From: Anatolij Gustschin [mailto:agust at denx.de]
Sent: 2018年10月18日 20:28
To: u-boot at lists.denx.de; Peng Fan <[email protected]>; sbabic at denx.de
Subject: [PATCH v6 21/34] imx8: cpu: add uclass based CPU driver
print_cpuinfo()in board init code requires uclass CPU driver, add it to be able to display CPU info whenCONFIG_DISPLAY_CPUINFOoption is enabled. CPU node in DT will have to include 'clocks'
and 'u-boot,dm-pre-reloc' properties for genericprint_cpuinfo()to work as expected. The driver outputs info for i.MX8QXP Rev A and Rev B CPUs.Signed-off-by Anatolij Gustschin <[email protected]>Cc Stefano Babic <[email protected]>--- arch/arm/include/asm/arch-imx/cpu.h | 5 +- arch/arm/mach-imx/imx8/cpu.c | 215 ++++++++++++++++++---------- 2 files changed, 142 insertions(+), 78 deletions(-)arch/arm/include/asm/arch-imx/cpu.h +3
-2@@ -25,6 +25,7 @@#define MXC_CPU_MX7S 0x71/* dummy ID */ #define MXC_CPU_MX7D 0x72#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP_A0 0x90/* dummy ID */ #define MXC_CPU_IMX8QXP 0x92/* dummy ID */ #define MXC_CPU_MX7ULP 0xE1/* Temporally hard code */ #define MXC_CPU_VF610 0xF6/* dummy ID */ @@ -43,8 +44,8 @@#define CHIP_REV_2_5 0x25#define CHIP_REV_3_0 0x30 -#define CHIP_REV_A 0x0 -#define CHIP_REV_B 0x1 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1#define BOARD_REV_1_0 0x0#define BOARD_REV_2_0 0x1arch/arm/mach-imx/imx8/cpu.c +1
-76@@ -5,6 +5,7 @@#include <common.h> #include <clk.h> +#include <cpu.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> @@ -19,82 +20,6 @@DECLARE_GLOBAL_DATA_PTR ; -u32 get_cpu_rev (void ) -{ -u32 id =0 , rev =0 ; -int ret; - - ret =sc_misc_get_control (-1 ,SC_R_SYSTEM ,SC_C_ID , &id); -if (ret) -return 0 ; - - rev = (id >>5 ) &0xf ; - id = (id &0x1f ) +MXC_SOC_IMX8 ;/* Dummy ID for chip */ - -return (id <<12 ) | rev; -} - -#ifdef CONFIG_DISPLAY_CPUINFO -const char *get_imx8_type (u32 imxtype) -{ -switch (imxtype) { -case MXC_CPU_IMX8QXP : -return "8QXP" ; -default : -return "??" ; - } -} - -const char *get_imx8_rev (u32 rev) -{ -switch (rev) { -case CHIP_REV_A : -return "A" ; -case CHIP_REV_B : -return "B" ; -default : -return "?" ; - } -} - -const char *get_core_name (void ) -{ -if (is_cortex_a35 ()) -return "A35" ; -else -return "?" ; -} - -int print_cpuinfo (void ) -{ -struct udevice *dev; -struct clk cpu_clk; -int ret; - - ret =uclass_get_device (UCLASS_CPU ,0 , &dev); -if (ret) -return 0 ; - - ret =clk_get_by_index (dev,0 , &cpu_clk); -if (ret) { -dev_err (dev,"failed to clk\n" ); -return 0 ; - } - -u32 cpurev; - - cpurev =get_cpu_rev (); - -printf ("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n" , -get_imx8_type ((cpurev &0xFF000 ) >>12 ), -get_imx8_rev ((cpurev &0xFFF )), -get_core_name (), -clk_get_rate (&cpu_clk) /1000000 ); - -return 0 ; -} -#endif -#define BT_PASSOVER_TAG 0x504F struct pass_over_info_t *get_pass_over_info(void) { @@ -581,3 +506,141 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)err:
arch/arm/mach-imx/imx8/cpu.c +125
-0printf ("%s: fuse %d, err: %d\n" , __func__, word[i], ret); } + +#if CONFIG_IS_ENABLED (CPU ) +struct cpu_imx_platdata { +const char *name; +const char *rev; +const char *type; +u32 cpurev; +u32 freq_mhz; +}; + +u32 get_cpu_rev (void ) +{ +u32 id =0 , rev =0 ; +int ret; + + ret =sc_misc_get_control (-1 ,SC_R_SYSTEM ,SC_C_ID , &id); +if (ret) +return 0 ; + + rev = (id >>5 ) &0xf ; + id = (id &0x1f ) +MXC_SOC_IMX8 ;/* Dummy ID for chip */ + +return (id <<12 ) | rev; +} + +const char *get_imx8_type (u32 imxtype) +{ +switch (imxtype) { +case MXC_CPU_IMX8QXP : +case MXC_CPU_IMX8QXP_A0 : +return "QXP" ; +default : +return "??" ; + } +} + +const char *get_imx8_rev (u32 rev) +{ +switch (rev) { +case CHIP_REV_A : +return "A" ; +case CHIP_REV_B : +return "B" ; +default : +return "?" ; + } +} + +const char *get_core_name (void ) +{ +if (is_cortex_a35 ()) +return "A35" ; +else if (is_cortex_a53 ()) +return "A53" ; +else if (is_cortex_a72 ()) +return "A72" ; +else +return "?" ; +} + +int cpu_imx_get_desc (struct udevice *dev,char *buf,int size) { +struct cpu_imx_platdata *plat =dev_get_platdata (dev); + +if (size <100 ) +return -ENOSPC ; + +snprintf (buf, size,"CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n" , + plat->type, plat->rev, plat->name, plat->freq_mhz); + +return 0 ; +} + +static int cpu_imx_get_info (struct udevice *dev,struct cpu_info *info) +{ +struct cpu_imx_platdata *plat =dev_get_platdata (dev); + + info->cpu_freq = plat->freq_mhz *1000 ; + info->features =BIT (CPU_FEAT_L1_CACHE ) |BIT (CPU_FEAT_MMU ); +return 0 ; +} + +static int cpu_imx_get_count (struct udevice *dev) { +return 4 ; +} + +static int cpu_imx_get_vendor (struct udevice *dev,char *buf,int +size) { +snprintf (buf, size,"NXP" ); +return 0 ; +} + +static const struct cpu_ops cpu_imx8_ops = { + .get_desc = cpu_imx_get_desc, + .get_info = cpu_imx_get_info, + .get_count = cpu_imx_get_count, + .get_vendor = cpu_imx_get_vendor, +}; + +static const struct udevice_id cpu_imx8_ids[] = { + { .compatible ="arm,cortex-a35" }, + { } +}; + +static int imx8_cpu_probe (struct udevice *dev) { +struct cpu_imx_platdata *plat =dev_get_platdata (dev); +struct clk cpu_clk; +u32 cpurev; +int ret; + + cpurev =get_cpu_rev (); + plat->cpurev = cpurev; + plat->name =get_core_name (); + plat->rev =get_imx8_rev (cpurev &0xFFF ); + plat->type =get_imx8_type ((cpurev &0xFF000 ) >>12 ); + + ret =clk_get_by_index (dev,0 , &cpu_clk); +if (ret) { +debug ("%s: Failed to get CPU clk: %d\n" , __func__, ret); +return 0 ; + } + + plat->freq_mhz =clk_get_rate (&cpu_clk) /1000000 ; +return 0 ; +} +
arch/arm/mach-imx/imx8/cpu.c void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) · line 646
Quoted 10 lines
arch/arm/mach-imx/imx8/cpu.c +10
-0+U_BOOT_DRIVER (cpu_imx8_drv) = { + .name ="imx8x_cpu" , + .id =UCLASS_CPU , + .of_match = cpu_imx8_ids, + .ops = &cpu_imx8_ops, + .probe = imx8_cpu_probe, + .platdata_auto_alloc_size =sizeof (struct cpu_imx_platdata ), + .flags =DM_FLAG_PRE_RELOC , +}; +#endif
Reviewed-by Peng Fan <[email protected]>
Thanks,
Peng.
Quoted 2 lines
--
2.17.1
PATCH v6 22/34 imx8: add iomux configuration api
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add iomux configuration api.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/iomux.h | 40 ++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/iomux.c | 43 ++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/mach-imx/imx8/iomux.c
arch/arm/include/asm/arch-imx8/iomux.h new file +40 -0
@@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __ASM_ARCH_IMX8_IOMUX_H__ +#define __ASM_ARCH_IMX8_IOMUX_H__ + +/* +* We use 64bits value for iomux settings. +* High 32bits are used for padring register value, +* low 16bits are used for pin index. +*/ +typedef u64 iomux_cfg_t ; + +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK BIT(31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK BIT(30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK GENMASK(29, 27) +#define PADRING_CONFIG_SHIFT 25 +#define PADRING_LPCONFIG_SHIFT 23 +#define PADRING_PULL_SHIFT 5 +#define PADRING_DSE_SHIFT 0 + +#define MUX_PAD_CTRL_SHIFT 32 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL (x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) +#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) +#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) + +/* Valid mux alt0 to alt7 */ +#define MUX_MODE_ALT (x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \ + MUX_MODE_MASK) + +void imx8_iomux_setup_pad (iomux_cfg_t pad); +void imx8_iomux_setup_multiple_pads (iomux_cfg_t const *pad_list,u32 count); +#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */
arch/arm/mach-imx/imx8/Makefile +1 -1
@@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o +obj-y += cpu.o iomux.o
arch/arm/mach-imx/imx8/iomux.c new file +43 -0
43 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH v6 23/34 imx8: add dummy clock
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
This driver is mostly used to avoid build errors. We use uclass clk driver for clk related operations.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/clock.h | 27 ++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/clock.c | 21 ++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/mach-imx/imx8/clock.c
arch/arm/include/asm/arch-imx8/clock.h new file +27 -0
@@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __ASM_ARCH_IMX8_CLOCK_H__ +#define __ASM_ARCH_IMX8_CLOCK_H__ + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { +MXC_ARM_CLK =0 , +MXC_AHB_CLK , +MXC_IPG_CLK , +MXC_UART_CLK , +MXC_CSPI_CLK , +MXC_AXI_CLK , +MXC_DDR_CLK , +MXC_ESDHC_CLK , +MXC_ESDHC2_CLK , +MXC_ESDHC3_CLK , +MXC_I2C_CLK , +MXC_FEC_CLK , +}; + +u32 mxc_get_clock (enum mxc_clock clk); + +#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */
arch/arm/mach-imx/imx8/clock.c new file +21 -0
@@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include <common.h> +#include <linux/errno.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR ; + +u32 mxc_get_clock (enum mxc_clock clk) +{ +switch (clk) { +default : +printf ("Unsupported mxc_clock %d\n" , clk); +break ; + } + +return 0 ; +}
Signature · 1 line
2.17.1
PATCH v6 24/34 gpio: mxc_gpio: add support for i.MX8
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8 support, there are 8 GPIO banks.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/gpio.h | 21 +++++++++++++++++++ drivers/gpio/mxc_gpio.c | 30 +++++++++++++++++++-------- 2 files changed, 42 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h
arch/arm/include/asm/arch-imx8/gpio.h new file +21 -0
@@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __ASM_ARCH_IMX8_GPIO_H +#define __ASM_ARCH_IMX8_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { +u32 gpio_dr;/* data */ +u32 gpio_dir;/* direction */ +u32 gpio_psr;/* pad satus */ +}; +#endif + +/* IMX8 the GPIO index is from 0 not 1 */ +#define IMX_GPIO_NR (port, index) (((port) * 32) + ((index) & 31)) + +#endif /* __ASM_ARCH_IMX8_GPIO_H */
drivers/gpio/mxc_gpio.c +21 -9
@@ -40,21 +40,27 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR,#if defined(CONFIG_MX25 ) || defined(CONFIG_MX27 ) || defined(CONFIG_MX51 ) || \ defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || \ - defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) + defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) || \ + defined(CONFIG_ARCH_IMX8 ) [3] = GPIO4_BASE_ADDR,#endif #if defined(CONFIG_MX27 ) || defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || \ - defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) + defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) || \ + defined(CONFIG_ARCH_IMX8 ) [4] = GPIO5_BASE_ADDR, #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) [5] = GPIO6_BASE_ADDR,#endif #endif -#if defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || defined(CONFIG_MX7 ) +#if defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || defined(CONFIG_MX7 ) || \ + defined(CONFIG_ARCH_IMX8 )#if !(defined(CONFIG_MX6UL ) || defined(CONFIG_MX6ULL )) [6] = GPIO7_BASE_ADDR,#endif #endif +#if defined(CONFIG_ARCH_IMX8 ) + [7] = GPIO8_BASE_ADDR, +#endif }; static int mxc_gpio_direction(unsigned int gpio,
@@ -347,19 +353,22 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, #ifndef CONFIG_MX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8) { 6, (struct gpio_regs *)GPIO7_BASE_ADDR }, #endif +#if defined(CONFIG_ARCH_IMX8) + { 7, (struct gpio_regs *)GPIO8_BASE_ADDR }, +#endif }; U_BOOT_DEVICES(mxc_gpios) = {
@@ -368,19 +377,22 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, #ifndef CONFIG_MX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[6] }, #endif +#if defined(CONFIG_ARCH_IMX8) + { "gpio_mxc", &mxc_plat[7] }, +#endif }; #endif #endif
Signature · 1 line
2.17.1
PATCH v6 25/34 pinctrl: Add pinctrl driver for i.MX8
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configure pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/pinctrl/nxp/Kconfig | 18 +++ drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 209 ++++++++++++++++------------- drivers/pinctrl/nxp/pinctrl-imx.h | 16 +++ drivers/pinctrl/nxp/pinctrl-imx8.c | 40 ++++++ drivers/pinctrl/nxp/pinctrl-scu.c | 66 +++++++++ 6 files changed, 258 insertions(+), 93 deletions(-) create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c
drivers/pinctrl/nxp/Kconfig +18 -0
@@ -1,6 +1,9 @@ config PINCTRL_IMX bool +config PINCTRL_IMX_SCU + bool + config PINCTRL_IMX5 bool "IMX5 pinctrl driver" depends on ARCH_MX5 && PINCTRL_FULL
@@ -56,3 +59,18 @@ config PINCTRL_IMX7ULP is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configure related registers. + +config PINCTRL_IMX8 + bool "IMX8 pinctrl driver" + depends on ARCH_IMX8 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8 pinctrl driver + + This provides a simple pinctrl driver for i.MX8 SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configures related + registers.
drivers/pinctrl/nxp/Makefile +2 -0
@@ -3,3 +3,5 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o +obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o +obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
drivers/pinctrl/nxp/pinctrl-imx.c +116 -93
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drivers/pinctrl/nxp/pinctrl-imx.h +16 -0
@@ -40,13 +40,29 @@ extern const struct pinctrl_ops imx_pinctrl_ops;#define FSL_PIN_SIZE 24#define SHARE_FSL_PIN_SIZE 20 +/* Each pin on imx8qm/qxp consists of 2 u32 PIN_FUNC_ID and 1 u32 CONFIG */ +#define SHARE_IMX8_PIN_SIZE 12 +#define SHARE_MUX_CONF_REG 0x1#define ZERO_OFFSET_VALID 0x2#define CONFIG_IBE_OBE 0x4 +#define IMX8_USE_SCU 0x8#define IOMUXC_CONFIG_SION (0x1 << 4)int imx_pinctrl_probe (struct udevice *dev,struct imx_pinctrl_soc_info *info);int imx_pinctrl_remove (struct udevice *dev); + +#ifdef CONFIG_PINCTRL_IMX_SCU +int imx_pinctrl_scu_conf_pins (struct imx_pinctrl_soc_info *info, +u32 *pin_data,int npins); +#else +static inline int imx_pinctrl_scu_conf_pins (struct imx_pinctrl_soc_info *info, +u32 *pin_data,int npins) +{ +return 0 ; +} +#endif +#endif /* __DRIVERS_PINCTRL_IMX_H */
drivers/pinctrl/nxp/pinctrl-imx8.c new file +40 -0
@@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include <common.h> +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +DECLARE_GLOBAL_DATA_PTR ; + +static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = { + .flags =IMX8_USE_SCU , +}; + +static int imx8_pinctrl_probe (struct udevice *dev) +{ +struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data (dev); + +return imx_pinctrl_probe (dev, info); +} + +static const struct udevice_id imx8_pinctrl_match[] = { + { .compatible ="fsl,imx8qxp-iomuxc" , .data = (ulong)&imx8_pinctrl_soc_info }, + {/* sentinel */ } +}; + +U_BOOT_DRIVER (imx8_pinctrl) = { + .name ="imx8_pinctrl" , + .id =UCLASS_PINCTRL , + .of_match =of_match_ptr (imx8_pinctrl_match), + .probe = imx8_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size =sizeof (struct imx_pinctrl_priv ), + .ops = &imx_pinctrl_ops, + .flags =DM_FLAG_PRE_RELOC , +};
drivers/pinctrl/nxp/pinctrl-scu.c new file +66 -0
66 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH v6 26/34 power: Add power domain driver for i.MX8
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add the power domain DM driver for i.MX8, that it depends on the DTB power domain trees to generate the power domain provider devices. Users need to add power domain trees with property "compatible = "nxp,imx8-pd";"
When power on a PD device, the driver will power on its ancestor PD devices in power domain tree.
When power off a PD device, the driver will check its child PD devices first. Only if all child PD devices are off, then power off the current PD device. Then the driver checks sibling PD devices. If sibling PD devices are off, then it will power off parent PD device.
There is no counter maintained in this driver, but a state to hold current on/off state. So the request and free functions are empty.
The power domain implementation in i.MX8 DTB set the "#power-domain-cells" to 0, so there is no ID binding with each PD device. We don't use "id" variable in struct power_domain. At the same time, we have to set of_xlate to empty to bypass standard of_xlate in uclass driver.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/include/asm/arch-imx8/power-domain.h | 15 + drivers/power/domain/Kconfig | 8 +- drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8-power-domain.c | 315 ++++++++++++++++++ 4 files changed, 338 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h create mode 100644 drivers/power/domain/imx8-power-domain.c
arch/arm/include/asm/arch-imx8/power-domain.h new file +15 -0
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2017 NXP +*/ + +#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8_POWER_DOMAIN_H + +#include <asm/arch/sci/types.h> + +struct imx8_power_domain_platdata { +sc_rsrc_t resource_id; +}; + +#endif
drivers/power/domain/Kconfig +7 -1
@@ -16,6 +16,13 @@ config BCM6328_POWER_DOMAIN Enable support for manipulating BCM6345 power domains via MMIO mapped registers. +config IMX8_POWER_DOMAIN + bool "Enable i.MX8 power domain driver" + depends on ARCH_IMX8 + help + Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC + requests to the SCU. + config MESON_GX_VPU_POWER_DOMAIN bool "Enable Amlogic Meson GX VPU power domain driver" depends on ARCH_MESON
@@ -44,5 +51,4 @@ config TI_SCI_POWER_DOMAIN help Generic power domain implementation for TI devices implementing the TI SCI protocol. - endmenu
drivers/power/domain/Makefile +1 -0
@@ -4,6 +4,7 @@ obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o +obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
drivers/power/domain/imx8-power-domain.c new file +315 -0
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2.17.1
PATCH v6 27/34 clk: imx: add clk driver for i.MX8QXP
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/imx/Kconfig | 6 + drivers/clk/imx/Makefile | 5 + drivers/clk/imx/clk-imx8.c | 393 +++++++++++++++++++++++++++++++++++++ 5 files changed, 406 insertions(+) create mode 100644 drivers/clk/imx/Kconfig create mode 100644 drivers/clk/imx/Makefile create mode 100644 drivers/clk/imx/clk-imx8.c
drivers/clk/Kconfig +1 -0
@@ -100,6 +100,7 @@ config CLK_STM32MP1 source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" +source "drivers/clk/imx/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig"
drivers/clk/Makefile +1 -0
@@ -7,6 +7,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o +obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o
drivers/clk/imx/Kconfig new file +6 -0
@@ -0,0 +1,6 @@ +config CLK_IMX8 + bool "Clock support for i.MX8" + depends on ARCH_IMX8 + select CLK + help + This enables support clock driver for i.MX8 platforms.
drivers/clk/imx/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
drivers/clk/imx/clk-imx8.c new file +393 -0
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2.17.1
PATCH v6 28/34 serial_lpuart: Update lpuart driver to support i.MX8
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8 compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations.
Also, according to RM, the Receive FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 (not 0x40) for i.MX8, otherwise the Receive FIFO is not disabled.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/serial/serial_lpuart.c | 15 ++++++++++++--- include/fsl_lpuart.h | 2 +- 2 files changed, 13 insertions(+), 4 deletions(-)
drivers/serial/serial_lpuart.c +12 -3
@@ -41,7 +41,11 @@#define CTRL_RE (1 << 18)#define FIFO_TXFE 0x80 +#ifdef CONFIG_ARCH_IMX8 +#define FIFO_RXFE 0x08 +#else #define FIFO_RXFE 0x40 +#endif #define WATER_TXWATER_OFF 1#define WATER_RXWATER_OFF 16
@@ -54,7 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;enum lpuart_devtype {DEV_VF610 =1 ,DEV_LS1021A , -DEV_MX7ULP +DEV_MX7ULP , +DEV_IMX8 };struct lpuart_serial_platdata {
@@ -325,7 +330,7 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)lpuart_write32 (plat->flags, &base->match,0 ); -if (plat->devtype ==DEV_MX7ULP ) { +if (plat->devtype ==DEV_MX7ULP || plat->devtype ==DEV_IMX8 ) {_lpuart32_serial_setbrg_7ulp (plat, gd->baudrate); }else {/* provide data bits, parity, stop bit, etc */
@@ -342,7 +347,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)struct lpuart_serial_platdata *plat = dev->platdata;if (is_lpuart32 (dev)) { -if (plat->devtype ==DEV_MX7ULP ) +if (plat->devtype ==DEV_MX7ULP || plat->devtype ==DEV_IMX8 )_lpuart32_serial_setbrg_7ulp (plat, baudrate);else _lpuart32_serial_setbrg (plat, baudrate);
@@ -427,6 +432,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype =DEV_MX7ULP ; else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; + else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + plat->devtype = DEV_IMX8;return 0 ; }
@@ -444,6 +451,8 @@ static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,imx7ulp-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,vf610-lpuart"}, + { .compatible = "fsl,imx8qm-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, { } };
include/fsl_lpuart.h +1 -1
@@ -4,7 +4,7 @@* */ -#ifdef CONFIG_ARCH_MX7ULP +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) struct lpuart_fsl_reg32 { u32 verid; u32 param;
Signature · 1 line
2.17.1
PATCH v6 29/34 serial: lpuart: Enable RX and TX FIFO
In reply to Anatolij GustschinFrom: Ye Li <[email protected]>
Enable the RX and TX FIFO in LPUART driver to avoid the input lost during U-Boot boot up.
Signed-off-by Ye Li <[email protected]>
Acked-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/serial/serial_lpuart.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-)
drivers/serial/serial_lpuart.c +26 -7
@@ -40,6 +40,12 @@#define CTRL_TE (1 << 19)#define CTRL_RE (1 << 18) +#define FIFO_RXFLUSH BIT(14) +#define FIFO_TXFLUSH BIT(15) +#define FIFO_TXSIZE_MASK 0x70 +#define FIFO_TXSIZE_OFF 4 +#define FIFO_RXSIZE_MASK 0x7 +#define FIFO_RXSIZE_OFF 0#define FIFO_TXFE 0x80#ifdef CONFIG_ARCH_IMX8 #define FIFO_RXFE 0x08
@@ -47,7 +53,7 @@#define FIFO_RXFE 0x40#endif -#define WATER_TXWATER_OFF 1 +#define WATER_TXWATER_OFF 0#define WATER_RXWATER_OFF 16DECLARE_GLOBAL_DATA_PTR ;
@@ -318,15 +324,28 @@ static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)static int _lpuart32_serial_init (struct lpuart_serial_platdata *plat) {struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; -u32 ctrl; +u32 val, tx_fifo_size; -lpuart_read32 (plat->flags, &base->ctrl, &ctrl); - ctrl &= ~CTRL_RE ; - ctrl &= ~CTRL_TE ; -lpuart_write32 (plat->flags, &base->ctrl, ctrl); +lpuart_read32 (plat->flags, &base->ctrl, &val); + val &= ~CTRL_RE ; + val &= ~CTRL_TE ; +lpuart_write32 (plat->flags, &base->ctrl, val);lpuart_write32 (plat->flags, &base->modir,0 ); -lpuart_write32 (plat->flags, &base->fifo, ~(FIFO_TXFE |FIFO_RXFE )); + +lpuart_read32 (plat->flags, &base->fifo, &val); + tx_fifo_size = (val &FIFO_TXSIZE_MASK ) >>FIFO_TXSIZE_OFF ; +/* Set the TX water to half of FIFO size */ +if (tx_fifo_size >1 ) + tx_fifo_size = tx_fifo_size >>1 ; + +/* Set RX water to 0, to be triggered by any receive data */ +lpuart_write32 (plat->flags, &base->water, + (tx_fifo_size <<WATER_TXWATER_OFF )); + +/* Enable TX and RX FIFO */ + val |= (FIFO_TXFE |FIFO_RXFE |FIFO_TXFLUSH |FIFO_RXFLUSH ); +lpuart_write32 (plat->flags, &base->fifo, val);lpuart_write32 (plat->flags, &base->match,0 );
Signature · 1 line
2.17.1
PATCH v6 30/34 serial: lpuart: support uclass clk api
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Modify most APIs to use udevice as the first parameter, then it will be easy to get the clk reference by using udevice pointer. Use uclass api to get lpuart clk when CONFIG_CLK is enabled.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/serial/serial_lpuart.c | 80 ++++++++++++++++++++++++++-------- 1 file changed, 61 insertions(+), 19 deletions(-)
drivers/serial/serial_lpuart.c +61 -19
@@ -4,6 +4,7 @@*/ #include <common.h> +#include <clk.h> #include <dm.h> #include <fsl_lpuart.h> #include <watchdog.h>
@@ -104,6 +105,29 @@ u32 __weak get_lpuart_clk(void)return CONFIG_SYS_CLK_FREQ ; } +#if IS_ENABLED (CONFIG_CLK ) +ulong get_lpuart_clk_rate (struct udevice *dev) +{ +struct clk per_clk; +ulong rate; +int ret; + + ret =clk_get_by_name (dev,"per" , &per_clk); +if (ret) { +dev_err (dev,"Failed to get per clk: %d\n" , ret); +return ret; + } + + rate =clk_get_rate (&per_clk); +if ((long )rate <=0 ) { +dev_err (dev,"Failed to get per clk rate: %ld\n" , (long )rate); +return ret; + } + +return rate; +} +#endif +static bool is_lpuart32 (struct udevice *dev) {struct lpuart_serial_platdata *plat = dev->platdata;
@@ -111,13 +135,19 @@ static bool is_lpuart32(struct udevice *dev)return plat->flags &LPUART_FLAG_REGMAP_32BIT_REG ; } -static void _lpuart_serial_setbrg (struct lpuart_serial_platdata *plat, +static void _lpuart_serial_setbrg (struct udevice *dev,int baudrate) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl *base = plat->reg; -u32 clk =get_lpuart_clk (); +u32 clk;u16 sbr; +if (IS_ENABLED (CONFIG_CLK )) + clk =get_lpuart_clk_rate (dev); +else + clk =get_lpuart_clk (); + sbr = (u16)(clk / (16 * baudrate));/* place adjustment later - n/32 BRFA */
@@ -162,8 +192,9 @@ static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)* Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int _lpuart_serial_init (struct lpuart_serial_platdata *plat) +static int _lpuart_serial_init (struct udevice *dev) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;u8 ctrl;
@@ -182,19 +213,25 @@ static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)__raw_writeb (CFIFO_TXFLUSH |CFIFO_RXFLUSH , &base->ucfifo);/* provide data bits, parity, stop bit, etc */ -_lpuart_serial_setbrg (plat, gd->baudrate); +_lpuart_serial_setbrg (dev, gd->baudrate);__raw_writeb (UC2_RE |UC2_TE , &base->uc2);return 0 ; } -static void _lpuart32_serial_setbrg_7ulp (struct lpuart_serial_platdata *plat, +static void _lpuart32_serial_setbrg_7ulp (struct udevice *dev,int baudrate) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl_reg32 *base = plat->reg;u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; -u32 clk =get_lpuart_clk (); +u32 clk; + +if (IS_ENABLED (CONFIG_CLK )) + clk =get_lpuart_clk_rate (dev); +else + clk =get_lpuart_clk (); baud_diff = baudrate; osr =0 ;
@@ -248,13 +285,19 @@ static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,out_le32 (&base->baud, tmp); } -static void _lpuart32_serial_setbrg (struct lpuart_serial_platdata *plat, +static void _lpuart32_serial_setbrg (struct udevice *dev,int baudrate) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl_reg32 *base = plat->reg; -u32 clk =get_lpuart_clk (); +u32 clk;u32 sbr; +if (IS_ENABLED (CONFIG_CLK )) + clk =get_lpuart_clk_rate (dev); +else + clk =get_lpuart_clk (); + sbr = (clk / (16 * baudrate));/* place adjustment later - n/32 BRFA */
@@ -321,8 +364,9 @@ static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)* Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int _lpuart32_serial_init (struct lpuart_serial_platdata *plat) +static int _lpuart32_serial_init (struct udevice *dev) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;u32 val, tx_fifo_size;
@@ -350,10 +394,10 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)lpuart_write32 (plat->flags, &base->match,0 );if (plat->devtype ==DEV_MX7ULP || plat->devtype ==DEV_IMX8 ) { -_lpuart32_serial_setbrg_7ulp (plat, gd->baudrate); +_lpuart32_serial_setbrg_7ulp (dev, gd->baudrate); }else {/* provide data bits, parity, stop bit, etc */ -_lpuart32_serial_setbrg (plat, gd->baudrate); +_lpuart32_serial_setbrg (dev, gd->baudrate); }lpuart_write32 (plat->flags, &base->ctrl,CTRL_RE |CTRL_TE );
@@ -363,15 +407,15 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)static int lpuart_serial_setbrg (struct udevice *dev,int baudrate) { -struct lpuart_serial_platdata *plat = dev->platdata; +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);if (is_lpuart32 (dev)) {if (plat->devtype ==DEV_MX7ULP || plat->devtype ==DEV_IMX8 ) -_lpuart32_serial_setbrg_7ulp (plat, baudrate); +_lpuart32_serial_setbrg_7ulp (dev, baudrate);else -_lpuart32_serial_setbrg (plat, baudrate); +_lpuart32_serial_setbrg (dev, baudrate); }else { -_lpuart_serial_setbrg (plat, baudrate); +_lpuart_serial_setbrg (dev, baudrate); }return 0 ;
@@ -423,12 +467,10 @@ static int lpuart_serial_pending(struct udevice *dev, bool input)static int lpuart_serial_probe (struct udevice *dev) { -struct lpuart_serial_platdata *plat = dev->platdata; -if (is_lpuart32 (dev)) -return _lpuart32_serial_init (plat); +return _lpuart32_serial_init (dev);else -return _lpuart_serial_init (plat); +return _lpuart_serial_init (dev); }static int lpuart_serial_ofdata_to_platdata (struct udevice *dev)
Signature · 1 line
2.17.1
PATCH v7 30/34 serial: lpuart: support uclass clk api
From: Peng Fan <[email protected]>
Modify most APIs to use udevice as the first parameter, then it will be easy to get the clk reference by using udevice pointer. Use uclass api to get lpuart clk when CONFIG_CLK is enabled.
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
---
Changes in v7:
- fixed build error when CONFIG_CLK not defined
- get_lpuart_clk_rate() can return negative value on error, check return value and only proceed with register config when meaningful clock rate returned
drivers/serial/serial_lpuart.c | 95 +++++++++++++++++++++++++++------- 1 file changed, 76 insertions(+), 19 deletions(-)
drivers/serial/serial_lpuart.c +76 -19
@@ -4,6 +4,7 @@*/ #include <common.h> +#include <clk.h> #include <dm.h> #include <fsl_lpuart.h> #include <watchdog.h>
@@ -104,6 +105,32 @@ u32 __weak get_lpuart_clk(void)return CONFIG_SYS_CLK_FREQ ; } +#if IS_ENABLED (CONFIG_CLK ) +static int get_lpuart_clk_rate (struct udevice *dev,u32 *clk) +{ +struct clk per_clk; +ulong rate; +int ret; + + ret =clk_get_by_name (dev,"per" , &per_clk); +if (ret) { +dev_err (dev,"Failed to get per clk: %d\n" , ret); +return ret; + } + + rate =clk_get_rate (&per_clk); +if ((long )rate <=0 ) { +dev_err (dev,"Failed to get per clk rate: %ld\n" , (long )rate); +return ret; + } + *clk = rate; +return 0 ; +} +#else +static inline int get_lpuart_clk_rate (struct udevice *dev,u32 *clk) +{return -ENOSYS ; } +#endif +static bool is_lpuart32 (struct udevice *dev) {struct lpuart_serial_platdata *plat = dev->platdata;
@@ -111,12 +138,22 @@ static bool is_lpuart32(struct udevice *dev)return plat->flags &LPUART_FLAG_REGMAP_32BIT_REG ; } -static void _lpuart_serial_setbrg (struct lpuart_serial_platdata *plat, +static void _lpuart_serial_setbrg (struct udevice *dev,int baudrate) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl *base = plat->reg; -u32 clk =get_lpuart_clk (); +u32 clk;u16 sbr; +int ret; + +if (IS_ENABLED (CONFIG_CLK )) { + ret =get_lpuart_clk_rate (dev, &clk); +if (ret) +return ; + }else { + clk =get_lpuart_clk (); + } sbr = (u16)(clk / (16 * baudrate));
@@ -162,8 +199,9 @@ static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)* Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int _lpuart_serial_init (struct lpuart_serial_platdata *plat) +static int _lpuart_serial_init (struct udevice *dev) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;u8 ctrl;
@@ -182,19 +220,29 @@ static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)__raw_writeb (CFIFO_TXFLUSH |CFIFO_RXFLUSH , &base->ucfifo);/* provide data bits, parity, stop bit, etc */ -_lpuart_serial_setbrg (plat, gd->baudrate); +_lpuart_serial_setbrg (dev, gd->baudrate);__raw_writeb (UC2_RE |UC2_TE , &base->uc2);return 0 ; } -static void _lpuart32_serial_setbrg_7ulp (struct lpuart_serial_platdata *plat, +static void _lpuart32_serial_setbrg_7ulp (struct udevice *dev,int baudrate) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl_reg32 *base = plat->reg;u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; -u32 clk =get_lpuart_clk (); +u32 clk; +int ret; + +if (IS_ENABLED (CONFIG_CLK )) { + ret =get_lpuart_clk_rate (dev, &clk); +if (ret) +return ; + }else { + clk =get_lpuart_clk (); + } baud_diff = baudrate; osr =0 ;
@@ -248,12 +296,22 @@ static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,out_le32 (&base->baud, tmp); } -static void _lpuart32_serial_setbrg (struct lpuart_serial_platdata *plat, +static void _lpuart32_serial_setbrg (struct udevice *dev,int baudrate) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl_reg32 *base = plat->reg; -u32 clk =get_lpuart_clk (); +u32 clk;u32 sbr; +int ret; + +if (IS_ENABLED (CONFIG_CLK )) { + ret =get_lpuart_clk_rate (dev, &clk); +if (ret) +return ; + }else { + clk =get_lpuart_clk (); + } sbr = (clk / (16 * baudrate));
@@ -321,8 +379,9 @@ static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)* Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int _lpuart32_serial_init (struct lpuart_serial_platdata *plat) +static int _lpuart32_serial_init (struct udevice *dev) { +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;u32 val, tx_fifo_size;
@@ -350,10 +409,10 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)lpuart_write32 (plat->flags, &base->match,0 );if (plat->devtype ==DEV_MX7ULP || plat->devtype ==DEV_IMX8 ) { -_lpuart32_serial_setbrg_7ulp (plat, gd->baudrate); +_lpuart32_serial_setbrg_7ulp (dev, gd->baudrate); }else {/* provide data bits, parity, stop bit, etc */ -_lpuart32_serial_setbrg (plat, gd->baudrate); +_lpuart32_serial_setbrg (dev, gd->baudrate); }lpuart_write32 (plat->flags, &base->ctrl,CTRL_RE |CTRL_TE );
@@ -363,15 +422,15 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)static int lpuart_serial_setbrg (struct udevice *dev,int baudrate) { -struct lpuart_serial_platdata *plat = dev->platdata; +struct lpuart_serial_platdata *plat =dev_get_platdata (dev);if (is_lpuart32 (dev)) {if (plat->devtype ==DEV_MX7ULP || plat->devtype ==DEV_IMX8 ) -_lpuart32_serial_setbrg_7ulp (plat, baudrate); +_lpuart32_serial_setbrg_7ulp (dev, baudrate);else -_lpuart32_serial_setbrg (plat, baudrate); +_lpuart32_serial_setbrg (dev, baudrate); }else { -_lpuart_serial_setbrg (plat, baudrate); +_lpuart_serial_setbrg (dev, baudrate); }return 0 ;
@@ -423,12 +482,10 @@ static int lpuart_serial_pending(struct udevice *dev, bool input)static int lpuart_serial_probe (struct udevice *dev) { -struct lpuart_serial_platdata *plat = dev->platdata; -if (is_lpuart32 (dev)) -return _lpuart32_serial_init (plat); +return _lpuart32_serial_init (dev);else -return _lpuart_serial_init (plat); +return _lpuart_serial_init (dev); }static int lpuart_serial_ofdata_to_platdata (struct udevice *dev)
Signature · 1 line
2.17.1
PATCH v6 31/34 fsl_esdhc: Update usdhc driver to support i.MX8
In reply to Anatolij GustschinFrom: Ye Li <[email protected]>
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by Ye Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Jaehoon Chung <[email protected]>
--- drivers/mmc/fsl_esdhc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/mmc/fsl_esdhc.c +4 -4
@@ -257,7 +257,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,int timeout;struct fsl_esdhc *regs = priv->esdhc_regs;#if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M )dma_addr_t addr;#endif uint wml_value;
@@ -271,7 +271,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,esdhc_clrsetbits32 (®s->wml,WML_RD_WML_MASK , wml_value);#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M ) addr =virt_to_phys ((void *)(data->dest));if (upper_32_bits (addr))printf ("Error found for upper 32 bits\n" );
@@ -301,7 +301,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, wml_value << 16);#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M ) addr =virt_to_phys ((void *)(data->src));if (upper_32_bits (addr))printf ("Error found for upper 32 bits\n" );
@@ -367,7 +367,7 @@ static void check_and_invalidate_dcache_rangeunsigned size =roundup (ARCH_DMA_MINALIGN , data->blocks*data->blocksize);#if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M )dma_addr_t addr; addr =virt_to_phys ((void *)(data->dest));
Signature · 1 line
2.17.1
PATCH v6 32/34 mmc: fsl_esdhc: add uclass clk support
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
When CONIFG_CLK is enabled, use uclass clk api to handle the clock.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Jaehoon Chung <[email protected]>
Cc Stefano Babic <[email protected]>
--- drivers/mmc/fsl_esdhc.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-)
drivers/mmc/fsl_esdhc.c +22 -4
@@ -11,6 +11,7 @@#include <config.h> #include <common.h> #include <command.h> +#include <clk.h> #include <errno.h> #include <hwconfig.h> #include <mmc.h>
@@ -121,6 +122,7 @@ struct esdhc_soc_data {struct fsl_esdhc_priv {struct fsl_esdhc *esdhc_regs;unsigned int sdhc_clk; +struct clk per_clk;unsigned int clock;unsigned int mode;unsigned int bus_width;
@@ -1496,10 +1498,26 @@ static int fsl_esdhc_probe(struct udevice *dev)init_clk_usdhc (dev->seq); - priv->sdhc_clk =mxc_get_clock (MXC_ESDHC_CLK + dev->seq); -if (priv->sdhc_clk <=0 ) { -dev_err (dev,"Unable to get clk for %s\n" , dev->name); -return -EINVAL ; +if (IS_ENABLED (CONFIG_CLK )) { +/* Assigned clock already set clock */ + ret =clk_get_by_name (dev,"per" , &priv->per_clk); +if (ret) { +printf ("Failed to get per_clk\n" ); +return ret; + } + ret =clk_enable (&priv->per_clk); +if (ret) { +printf ("Failed to enable per_clk\n" ); +return ret; + } + + priv->sdhc_clk =clk_get_rate (&priv->per_clk); + }else { + priv->sdhc_clk =mxc_get_clock (MXC_ESDHC_CLK + dev->seq); +if (priv->sdhc_clk <=0 ) { +dev_err (dev,"Unable to get clk for %s\n" , dev->name); +return -EINVAL ; + } } ret =fsl_esdhc_init (priv, plat);
Signature · 1 line
2.17.1
PATCH v6 33/34 arm: dts: introduce dtsi for i.MX8QXP
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P), so add them there, because i.MX8QXP includes the dtsi of them.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
--- arch/arm/dts/fsl-imx8-ca35.dtsi | 66 +++++ arch/arm/dts/fsl-imx8dx.dtsi | 499 ++++++++++++++++++++++++++++++++ arch/arm/dts/fsl-imx8dxp.dtsi | 11 + arch/arm/dts/fsl-imx8qxp.dtsi | 51 ++++ 4 files changed, 627 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi
arch/arm/dts/fsl-imx8-ca35.dtsi new file +66 -0
@@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <dt-bindings/clock/imx8qxp-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters having 4 Cortex-A35 cores */ + A35_0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +};
arch/arm/dts/fsl-imx8dx.dtsi new file +499 -0
499 lines not on this page · raw message
arch/arm/dts/fsl-imx8dxp.dtsi new file +11 -0
@@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include "fsl-imx8dx.dtsi" + +/ { + model = "Freescale i.MX8DXP"; + compatible = "fsl,imx8dxp", "fsl,imx8qxp"; +};
arch/arm/dts/fsl-imx8qxp.dtsi new file +51 -0
51 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH v6 34/34 imx: add i.MX8QXP MEK board support
In reply to Anatolij GustschinFrom: Peng Fan <[email protected]>
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file.
Signed-off-by Peng Fan <[email protected]>
Reviewed-by Anatolij Gustschin <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246 ++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 13 ++ board/freescale/imx8qxp_mek/Kconfig | 14 ++ board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 +++++++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 +++++++++++++++ board/freescale/mx8mq_evk/README | 81 +++++++ configs/imx8qxp_mek_defconfig | 51 +++++ include/configs/imx8qxp_mek.h | 157 ++++++++++++++ 11 files changed, 819 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/README create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 include/configs/imx8qxp_mek.h
arch/arm/dts/Makefile +2 -0
@@ -454,6 +454,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ r8a7795-salvator-x.dtb \
arch/arm/dts/fsl-imx8qxp-mek.dts new file +246 -0
246 lines not on this page · raw message
arch/arm/mach-imx/imx8/Kconfig +13 -0
@@ -10,4 +10,17 @@ config IMX8QXP config SYS_SOC default "imx8" +choice + prompt "i.MX8 board select" + optional + +config TARGET_IMX8QXP_MEK + bool "Support i.MX8QXP MEK board" + select BOARD_LATE_INIT + select IMX8QXP + +endchoice + +source "board/freescale/imx8qxp_mek/Kconfig" + endif
board/freescale/imx8qxp_mek/Kconfig new file +14 -0
@@ -0,0 +1,14 @@ +if TARGET_IMX8QXP_MEK + +config SYS_BOARD + default "imx8qxp_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_mek" + +source "board/freescale/common/Kconfig" + +endif
board/freescale/imx8qxp_mek/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +i.MX8QXP MEK BOARD +M: Peng Fan <[email protected]> +S: Maintained +F: board/freescale/imx8qxp_mek/ +F: include/configs/imx8qxp_mek.h +F: configs/imx8qxp_mek_defconfig
board/freescale/imx8qxp_mek/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_mek.o
board/freescale/imx8qxp_mek/README new file +72 -0
72 lines not on this page · raw message
board/freescale/imx8qxp_mek/imx8qxp_mek.c new file +170 -0
170 lines not on this page · raw message
board/freescale/mx8mq_evk/README new file +81 -0
81 lines not on this page · raw message
configs/imx8qxp_mek_defconfig new file +51 -0
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include/configs/imx8qxp_mek.h new file +157 -0
157 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH v6 34/34 imx: add i.MX8QXP MEK board support
Quoted 11 lines · Anatolij Gustschin
From: Peng Fan <[email protected]>
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file.Signed-off-by Peng Fan <[email protected]>Reviewed-by Anatolij Gustschin <[email protected]>Cc Stefano Babic <[email protected]>Cc Fabio Estevam <[email protected]>
Quoted 10 lines
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246 ++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 13 ++ board/freescale/imx8qxp_mek/Kconfig | 14 ++ board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 +++++++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 +++++++++++++++ board/freescale/mx8mq_evk/README | 81 +++++++
Peng,
Was the inclusion of the mx8mq_evk/README a mistake as this patch was centered around adding support for the i.MX8QXP MEK board?
I'm interested in building mainline U-Boot for the NXP i.MX 8M Quad Evaluation Kit (IMX8MQUADEVKQSG) which I assume is what the mx8mq_evk is for. Do you have plans to submit the rest of what's required for this board (configs/mx8mq_evk_defconfig, board/freescale/mx8mq_evk/*, arch/arm/dts/fsl-imx8mq-evk.dts).
It looks like inclusion of imx8mq-evk was was in a patch series early this year and got stalled for some reason?
Regards,
Tim
Peng Fan
reviewerPATCH v6 34/34 imx: add i.MX8QXP MEK board support
Hi Tim,
Quoted 32 lines
-----Original Message-----
From: Tim Harvey [mailto:tharvey at gateworks.com]
Sent: 2018年10月26日 5:10
To: Anatolij Gustschin <[email protected]>; Peng Fan <[email protected]>
Cc: u-boot <[email protected]>; Stefano Babic <[email protected]>; Fabio Estevam <[email protected]>
Subject: Re: [U-Boot] [PATCH v6 34/34] imx: add i.MX8QXP MEK board supportQuoted 7 lines · Anatolij Gustschin
From: Peng Fan <[email protected]>
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file.Quoted 7 lines
Signed-off-by Peng Fan <[email protected]>Reviewed-by Anatolij Gustschin <[email protected]>Cc Stefano Babic <[email protected]>Cc Fabio Estevam <[email protected]>--- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246++++++++++++++++++++++
Quoted 7 lines
arch/arm/mach-imx/imx8/Kconfig | 13 ++ board/freescale/imx8qxp_mek/Kconfig | 14 ++ board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 +++++++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 +++++++++++++++ board/freescale/mx8mq_evk/README | 81 +++++++
Quoted 4 lines
Peng,
Was the inclusion of the mx8mq_evk/README a mistake as this patch was centered around adding support for the i.MX8QXP MEK board?
That file was added by mistaken.
Quoted 9 lines
I'm interested in building mainline U-Boot for the NXP i.MX 8M Quad Evaluation Kit (IMX8MQUADEVKQSG) which I assume is what the
mx8mq_evkis for. Do you have plans to submit the rest of what's required for this board (configs/mx8mq_evk_defconfig, board/freescale/mx8mq_evk/*,arch/arm/dts/fsl-imx8mq-evk.dts).It looks like inclusion of imx8mq-evk was was in a patch series early this year and got stalled for some reason?
The ddr script is not good enough for upstream. I have asked help internal to restructure the code, but seems I have to be the guy working on this again.
My current plan is the board support including ddr and mkimage could be ready in next RC1.
Thanks,
Peng.
Quoted 4 lines
Regards,
Tim
PATCH v6 34/34 imx: add i.MX8QXP MEK board support
Quoted 49 lines · Peng Fan
Hi Tim,
Quoted 32 lines
-----Original Message-----
From: Tim Harvey [mailto:tharvey at gateworks.com]
Sent: 2018年10月26日 5:10
To: Anatolij Gustschin <[email protected]>; Peng Fan <[email protected]>
Cc: u-boot <[email protected]>; Stefano Babic <[email protected]>; Fabio Estevam <[email protected]>
Subject: Re: [U-Boot] [PATCH v6 34/34] imx: add i.MX8QXP MEK board supportQuoted 7 lines · Anatolij Gustschin
From: Peng Fan <[email protected]>
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file.Quoted 7 lines
Signed-off-by Peng Fan <[email protected]>Reviewed-by Anatolij Gustschin <[email protected]>Cc Stefano Babic <[email protected]>Cc Fabio Estevam <[email protected]>--- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8qxp-mek.dts | 246++++++++++++++++++++++
Quoted 7 lines
arch/arm/mach-imx/imx8/Kconfig | 13 ++ board/freescale/imx8qxp_mek/Kconfig | 14 ++ board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 +++++++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 +++++++++++++++ board/freescale/mx8mq_evk/README | 81 +++++++Quoted 4 lines
Peng,
Was the inclusion of the mx8mq_evk/README a mistake as this patch was centered around adding support for the i.MX8QXP MEK board?
That file was added by mistaken.
Quoted 7 lines
I'm interested in building mainline U-Boot for the NXP i.MX 8M Quad Evaluation Kit (IMX8MQUADEVKQSG) which I assume is what the
mx8mq_evkis for. Do you have plans to submit the rest of what's required for this board (configs/mx8mq_evk_defconfig, board/freescale/mx8mq_evk/*,arch/arm/dts/fsl-imx8mq-evk.dts).
Quoted 8 lines
Quoted 2 lines
It looks like inclusion of imx8mq-evk was was in a patch series early this year and got stalled for some reason?
The ddr script is not good enough for upstream. I have asked help internal to restructure the code, but seems I have to be the guy working on this again.
My current plan is the board support including ddr and mkimage could be ready in next RC1.
Peng,
Ok - thanks for the update. If you remember at the time please cc me on the imx8mq-evk patch series and I will be happy to test.
I read through the discussion regarding the ddr init from your v5 submission (https://patchwork.ozlabs.org/patch/857974/). You mention in that discussion that there is a ddr tool developed by NXP much like the one used for i.MX6/7. I remember using a DDR config tool from Freescale which was a spreadsheet and we ended up writing the ddr init code for imx6 SPL that followed the equations in that spreadsheet along with the ddr init sequence from the IMX6 reference manual. Could this be done here as well?
Can you point me to the NXP DDR tool for IMX8? I'm just getting started with the IMX8M and haven't run into it yet. DDR calibration was a huge pain for us for IMX6.
Also, for your next submission for imx8m-evk please think about the following:
- rename mx8mq to imx8mq to be consistent with what you did for imx8qxp_mek
- consider adding a flash map to the README showing where imx-mkimage is putting everything in the flash.bin image
I tried to apply your v5 imx8mq-evk patch on top of the latest master but ran into build issues so I'm anxiously awaiting your next submission!
Best Regards,
Tim
Fabio Estevam
maintainerPATCH v6 34/34 imx: add i.MX8QXP MEK board support
Hi Tim,
Quoted 3 lines · Tim Harvey
Can you point me to the NXP DDR tool for IMX8? I'm just getting started with the IMX8M and haven't run into it yet. DDR calibration was a huge pain for us for IMX6.
You can find it here:
https://community.nxp.com/docs/DOC-340179
PATCH v6 34/34 imx: add i.MX8QXP MEK board support
I have been spending some time on this, at least from the lpddr4 side.
There is a good amount of this that can be abstracted out and made
into general initialization routines. This is all well and good and
you can see that Boundary Devices has already codified some of these
values here. https://github.com/boundarydevices/u-boot-imx6/blob/boundary-v2018.07/board/boundary/nitrogen8m/ddr/ddrphy_train.c
However after you generate the script from the spreadsheet you then need to run it through a calibration routine, which is a Windows program that takes the values from the spreadsheets and runs them against the device and provides some tuned phy values based on the device. I don't see a good way to get around just having this chunk of code be a board specific function that runs the register settings that are spit out by the NXP tool.
As for the initialization I am not sure how much changes depending if the board is using DDR3, DDR4 or LPDDR4. It would be great if we could come up with some general direction on this and move things forward.
-Jon
Quoted 15 lines · Fabio Estevam
Hi Tim,
Quoted 3 lines · Tim Harvey
Can you point me to the NXP DDR tool for IMX8? I'm just getting started with the IMX8M and haven't run into it yet. DDR calibration was a huge pain for us for IMX6.
You can find it here:
https://community.nxp.com/docs/DOC-340179
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Fabio Estevam
maintainerPATCH v6 34/34 imx: add i.MX8QXP MEK board support
+ Peng
Quoted 15 lines · Jon Nettleton
I have been spending some time on this, at least from the lpddr4 side.
There is a good amount of this that can be abstracted out and made
into general initialization routines. This is all well and good and
you can see that Boundary Devices has already codified some of these
values here. https://github.com/boundarydevices/u-boot-imx6/blob/boundary-v2018.07/board/boundary/nitrogen8m/ddr/ddrphy_train.cHowever after you generate the script from the spreadsheet you then need to run it through a calibration routine, which is a Windows program that takes the values from the spreadsheets and runs them against the device and provides some tuned phy values based on the device. I don't see a good way to get around just having this chunk of code be a board specific function that runs the register settings that are spit out by the NXP tool.
Quoted 4 lines
As for the initialization I am not sure how much changes depending if the board is using DDR3, DDR4 or LPDDR4. It would be great if we could come up with some general direction on this and move things forward.
Peng on Cc has been working on this and hopefully will be able to post a new series soon.
Peng Fan
reviewerPATCH v6 34/34 imx: add i.MX8QXP MEK board support
Quoted 42 lines
-----Original Message-----
From: Fabio Estevam [mailto:festevam at gmail.com]
Sent: 2018年11月7日 20:36
To: Jon Nettleton <[email protected]>; Peng Fan <[email protected]>
Cc: tharvey at gateworks.com; Fabio Estevam <[email protected]>; U-Boot-Denx <[email protected]>
Subject: Re: [U-Boot] [PATCH v6 34/34] imx: add i.MX8QXP MEK board support+ Peng
Quoted 8 lines · Jon Nettleton
I have been spending some time on this, at least from the lpddr4 side. There is a good amount of this that can be abstracted out and made into general initialization routines. This is all well and good and you can see that Boundary Devices has already codified some of these values here.
https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fboundarydevices%2Fu-boot-imx6%2Fblob%2Fboundary-v2018.07% 2Fb
Quoted 1 line
oard%2Fboundary%2Fnitrogen8m%2Fddr%2Fddrphy_train.c&data=02%7C 01%7
Quoted 1 line
Cpeng.fan%40nxp.com%7C9ed74670423a422dd7f108d644ad89f0%7C686ea1d 3bc2b4
Quoted 1 line
c6fa92cd99c5c301635%7C0%7C0%7C636771909469703915&sdata=WJtl5 C4Z5YU
Quoted 10 lines
GLLKZUV6AVfGYjwzFIc7GojsBS8S%2BMWg%3D&reserved=0
However after you generate the script from the spreadsheet you then need to run it through a calibration routine, which is a Windows program that takes the values from the spreadsheets and runs them against the device and provides some tuned phy values based on the device. I don't see a good way to get around just having this chunk of code be a board specific function that runs the register settings that are spit out by the NXP tool.
Quoted 7 lines
Quoted 4 lines
As for the initialization I am not sure how much changes depending if the board is using DDR3, DDR4 or LPDDR4. It would be great if we could come up with some general direction on this and move things forward.
Peng on Cc has been working on this and hopefully will be able to post a new series soon.
Yes, the related patches will be sent out after some test, should be soon.
Regards,
Peng.