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Port mxs-dcp to imx6ull and imx6sll

PATCH Applied Leonard Crestez 4 participants 12 messages Oct 17, 2018 – Oct 31, 2018

Subsystems (4)
Device tree bindings Arm (32-bit) Arm i.MX and Layerscape Crypto API
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Leonard Crestez

author
#0 lore raw

v4 cover Port mxs-dcp to imx6ull and imx6sll

The DCP block is present on 6sll and 6ull but not enabled. The hardware is mostly compatible with 6sl, the only important difference is that explicit clock enabling is required.

There were several issues with the functionality of this driver (it didn't even probe properly) but they are fixed in cryptodev/master by this series:

    https://lore.kernel.org/patchwork/cover/994874/

Leonard Crestez (4):
dt-bindings: crypto: Mention clocks for mxs-dcp
crypto: mxs-dcp - Add support for dcp clk
ARM: dts: imx6ull: Add dcp node
ARM: imx_v6_v7_defconfig: Enable CRYPTO_DEV_MXS_DCP

 .../devicetree/bindings/crypto/fsl-dcp.txt    |  2 ++
 arch/arm/boot/dts/imx6ull.dtsi                | 10 +++++++
 arch/arm/configs/imx_v6_v7_defconfig          |  1 +
 drivers/crypto/mxs-dcp.c                      | 28 +++++++++++++++++--
 4 files changed, 38 insertions(+), 3 deletions(-)
Signature · 1 line
2.17.1
author
#1 lore raw

PATCH v4 1/4 dt-bindings: crypto: Mention clocks for mxs-dcp

Explicit clock enabling is required on 6sll and 6ull so mention that standard clock bindings are used.

Signed-off-by Leonard Crestez <[email protected]>
Reviewed-by Fabio Estevam <[email protected]>
---
 Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++
 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/crypto/fsl-dcp.txt +2 -0
index 76a0b4e80e83..4e4d387e38a5 100644
@@ -4,10 +4,12 @@ Required properties:
 - compatible : Should be "fsl,<soc>-dcp"
 - reg : Should contain MXS DCP registers location and length
 - interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
                must be supplied, optionally Secure IRQ can be present, but
 	       is currently not implemented and not used.
+- clocks : Clock reference (only required on some SOCs: 6ull and 6sll).
+- clock-names : Must be "dcp".
 
 Example:
 
 dcp at 80028000 {
 	compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Signature · 1 line
2.17.1
maintainer Reviewed-by on v4 1/4
#2 lore raw

Re: [PATCH v4 1/4] dt-bindings: crypto: Mention clocks for mxs-dcp

Quoted 9 lines · Leonard Crestez

Explicit clock enabling is required on 6sll and 6ull so mention that standard clock bindings are used.

Signed-off-by Leonard Crestez <[email protected]>
Reviewed-by Fabio Estevam <[email protected]>
---
 Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++
 1 file changed, 2 insertions(+)
Reviewed-by Rob Herring <[email protected]>
author
#3 lore raw

PATCH v4 2/4 crypto: mxs-dcp - Add support for dcp clk

In reply to Leonard Crestez

On 6ull and 6sll the DCP block has a clock which needs to be explicitly enabled.

Add minimal handling for this at probe/remove time.

Signed-off-by Leonard Crestez <[email protected]>
---
 drivers/crypto/mxs-dcp.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)
drivers/crypto/mxs-dcp.c +25 -3
index 4e6ff32f8a7e..a2105cf33abb 100644
@@ -18,10 +18,11 @@
 #include <linux/kthread.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/stmp_device.h>
+#include <linux/clk.h>
 
 #include <crypto/aes.h>
 #include <crypto/sha.h>
 #include <crypto/internal/hash.h>
 #include <crypto/internal/skcipher.h>

@@ -80,10 +81,11 @@ struct dcp {
 
 	struct completion		completion[DCP_MAX_CHANS];
 	spinlock_t			lock[DCP_MAX_CHANS];
 	struct task_struct		*thread[DCP_MAX_CHANS];
 	struct crypto_queue		queue[DCP_MAX_CHANS];
+	struct clk			*dcp_clk;
 };
 
 enum dcp_chan {
 	DCP_CHAN_HASH_SHA	= 0,
 	DCP_CHAN_CRYPTO		= 2,

@@ -1051,15 +1053,28 @@ static int mxs_dcp_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	/* Re-align the structure so it fits the DCP constraints. */
 	sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
 
-	/* Restart the DCP block. */
-	ret = stmp_reset_block(sdcp->base);
+	/* DCP clock is optional, only used on some SOCs */
+	sdcp->dcp_clk = devm_clk_get(dev, "dcp");
+	if (IS_ERR(sdcp->dcp_clk)) {
+		if (sdcp->dcp_clk != ERR_PTR(-ENOENT))
+			return PTR_ERR(sdcp->dcp_clk);
+		sdcp->dcp_clk = NULL;
+	}
+	ret = clk_prepare_enable(sdcp->dcp_clk);
 	if (ret)
 		return ret;
 
+	/* Restart the DCP block. */
+	ret = stmp_reset_block(sdcp->base);
+	if (ret) {
+		dev_err(dev, "Failed reset\n");
+		goto err_disable_unprepare_clk;
+	}
+
 	/* Initialize control register. */
 	writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
 	       MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
 	       sdcp->base + MXS_DCP_CTRL);
 

@@ -1092,11 +1107,12 @@ static int mxs_dcp_probe(struct platform_device *pdev)
 	/* Create the SHA and AES handler threads. */
 	sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
 						      NULL, "mxs_dcp_chan/sha");
 	if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
 		dev_err(dev, "Error starting SHA thread!\n");
-		return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
+		ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
+		goto err_disable_unprepare_clk;
 	}
 
 	sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
 						    NULL, "mxs_dcp_chan/aes");
 	if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {

@@ -1149,10 +1165,14 @@ static int mxs_dcp_probe(struct platform_device *pdev)
 err_destroy_aes_thread:
 	kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
 
 err_destroy_sha_thread:
 	kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
+
+err_disable_unprepare_clk:
+	clk_disable_unprepare(sdcp->dcp_clk);
+
 	return ret;
 }
 
 static int mxs_dcp_remove(struct platform_device *pdev)
 {

@@ -1168,10 +1188,12 @@ static int mxs_dcp_remove(struct platform_device *pdev)
 		crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
 
 	kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
 	kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
 
+	clk_disable_unprepare(sdcp->dcp_clk);
+
 	platform_set_drvdata(pdev, NULL);
 
 	global_sdcp = NULL;
 
 	return 0;
Signature · 1 line
2.17.1
reviewer
#4 lore raw

Re: [PATCH v4 2/4] crypto: mxs-dcp - Add support for dcp clk

Hi Leonard,

Quoted 8 lines · Leonard Crestez

On 6ull and 6sll the DCP block has a clock which needs to be explicitly enabled.

Add minimal handling for this at probe/remove time.

Signed-off-by Leonard Crestez <[email protected]>

---

Please always explain what changed from the previous patch version.

drivers/crypto/mxs-dcp.c static int mxs_dcp_probe(struct platform_device *pdev) · line 1074

Quoted 6 lines
drivers/crypto/mxs-dcp.c +6 -0
+       /* Restart the DCP block. */
+       ret = stmp_reset_block(sdcp->base);
+       if (ret) {
+               dev_err(dev, "Failed reset\n");
+               goto err_disable_unprepare_clk;
+       }

This seems like an unrelated change that should be in a separate patch.

Also, this was not present in v3, so it is better to explain that this has been introduced in v4.

author
#5 lore raw

Re: [PATCH v4 2/4] crypto: mxs-dcp - Add support for dcp clk

Quoted 10 lines · Fabio Estevam
Quoted 7 lines · Leonard Crestez

On 6ull and 6sll the DCP block has a clock which needs to be explicitly enabled.

Add minimal handling for this at probe/remove time.

Signed-off-by Leonard Crestez <[email protected]>

Please always explain what changed from the previous patch version.

There is a changelog in the cover letter.

Quoted 11 lines

drivers/crypto/mxs-dcp.c static int mxs_dcp_probe(struct platform_device *pdev) · line 1074

Quoted 6 lines
drivers/crypto/mxs-dcp.c +6 -0
+       /* Restart the DCP block. */
+       ret = stmp_reset_block(sdcp->base);
+       if (ret) {
+               dev_err(dev, "Failed reset\n");
+               goto err_disable_unprepare_clk;
+       }

This seems like an unrelated change that should be in a separate patch.

Also, this was not present in v3, so it is better to explain that this has been introduced in v4.

This only looks slightly odd in git diff but it's not unrelated.

I placed clk get/prepare/enable just before stmp_reset_block and made stmp_reset_block print a message and goto err_disable_unprepare_clk on failure instead of just "if (ret) return ret;"

reviewer Reviewed-by
#6 lore raw

Re: [PATCH v4 2/4] crypto: mxs-dcp - Add support for dcp clk

Quoted 1 line · Leonard Crestez

There is a changelog in the cover letter.

It did not show up:
https://lkml.org/lkml/2018/10/17/673

Quoted 5 lines

This only looks slightly odd in git diff but it's not unrelated.

I placed clk get/prepare/enable just before stmp_reset_block and made stmp_reset_block print a message and goto err_disable_unprepare_clk on failure instead of just "if (ret) return ret;"

Got it! Then it looks fine, thanks:

Reviewed-by Fabio Estevam <[email protected]>
author
#7 lore raw

Re: [PATCH v4 2/4] crypto: mxs-dcp - Add support for dcp clk

Quoted 6 lines · Fabio Estevam
Quoted 1 line · Leonard Crestez

There is a changelog in the cover letter.

It did not show up:
https://lkml.org/lkml/2018/10/17/673

Sorry, I forgot to copy the changelog for v4. The only change is the one we discussed earlier in this thread.

Quoted 9 lines
Quoted 5 lines

This only looks slightly odd in git diff but it's not unrelated.

I placed clk get/prepare/enable just before stmp_reset_block and made stmp_reset_block print a message and goto err_disable_unprepare_clk on failure instead of just "if (ret) return ret;"

Got it! Then it looks fine, thanks:

Reviewed-by Fabio Estevam <[email protected]>

Thanks for looking at this series.

Shawn already applied patches 3/4, I guess parts 1/2 should go through the crypto tree? I don't know how crypto treats patches in the merge window, I can resend with all the ack/review tags after rc1 is out.

author
#8 lore raw

PATCH v4 3/4 ARM: dts: imx6ull: Add dcp node

In reply to Leonard Crestez

The DCP block on 6ull has no major differences other than requiring explicit clock enabling.

Signed-off-by Leonard Crestez <[email protected]>
Reviewed-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx6ull.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)
arch/arm/boot/dts/imx6ull.dtsi +10 -0
index 796ed35d4ac9..f3668fe69eac 100644
@@ -37,10 +37,20 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x02200000 0x100000>;
 			ranges;
 
+			dcp: crypto at 2280000 {
+				compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";
+				reg = <0x02280000 0x4000>;
+				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
+				clock-names = "dcp";
+			};
+
 			iomuxc_snvs: iomuxc-snvs at 2290000 {
 				compatible = "fsl,imx6ull-iomuxc-snvs";
 				reg = <0x02290000 0x4000>;
 			};
Signature · 1 line
2.17.1
author
#10 lore raw

PATCH v4 4/4 ARM: imx_v6_v7_defconfig: Enable CRYPTO_DEV_MXS_DCP

In reply to Leonard Crestez

This block is present in 6sl, 6sll and 6ull so it should be enabled in the default imx kernel config.

Signed-off-by Leonard Crestez <[email protected]>
Reviewed-by Fabio Estevam <[email protected]>
---
 arch/arm/configs/imx_v6_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/configs/imx_v6_v7_defconfig +1 -0
index 1ad5736c8fa6..57928dff9bce 100644
@@ -428,10 +428,11 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
 CONFIG_SECURITYFS=y
 CONFIG_CRYPTO_DEV_FSL_CAAM=y
 CONFIG_CRYPTO_DEV_SAHARA=y
+CONFIG_CRYPTO_DEV_MXS_DCP=y
 CONFIG_CRC_CCITT=m
 CONFIG_CRC_T10DIF=y
 CONFIG_CRC7=m
 CONFIG_LIBCRC32C=m
 CONFIG_FONTS=y
Signature · 1 line
2.17.1