ARM: omap3_logic.c: Optimize DDR timings based on OMAP35 or 36/37
PATCH 1/1 ARM: omap3_logic.c: Optimize DDR timings based on OMAP35 or 36/37
The default timings are assumming an OMAP36 / AM37 / DM37, but the OMAP35 controller is a bit slower, so DDR may operate out of spec when under stress. This patch checks the processor type and sets the DDR timings according to processor type.
Fixes 5ad4212ce0d5 ("ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV
and OMAP35 Torpedo")
Signed-off-by Adam Ford <[email protected]>
board/logicpd/omap3som/omap3logic.c +15 -5
@@ -89,11 +89,21 @@ int spl_start_uboot(void)void get_board_mem_timings (struct board_sdrc_timings *timings) { timings->mr =MICRON_V_MR_165 ; -/* 256MB DDR */ - timings->mcfg =MICRON_V_MCFG_200 (256 <<20 ); - timings->ctrla =MICRON_V_ACTIMA_200 ; - timings->ctrlb =MICRON_V_ACTIMB_200 ; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + +if (get_cpu_family () ==CPU_OMAP36XX ) { +/* 200 MHz works for OMAP36/DM37 */ +/* 256MB DDR */ + timings->mcfg =MICRON_V_MCFG_200 (256 <<20 ); + timings->ctrla =MICRON_V_ACTIMA_200 ; + timings->ctrlb =MICRON_V_ACTIMB_200 ; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + }else { +/* 165 MHz works for OMAP35 */ + timings->mcfg =MICRON_V_MCFG_165 (256 <<20 ); + timings->ctrla =MICRON_V_ACTIMA_165 ; + timings->ctrlb =MICRON_V_ACTIMB_165 ; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } }#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
Signature · 1 line
2.17.1
board/logicpd/omap3som/omap3logic.c
Quoted 12 lines · Adam Ford
The default timings are assumming an OMAP36 / AM37 / DM37, but the OMAP35 controller is a bit slower, so DDR may operate out of spec when under stress. This patch checks the processor type and sets the DDR timings according to processor type.
Fixes 5ad4212ce0d5 ("ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LVand OMAP35 Torpedo")
Signed-off-by Adam Ford <[email protected]>board/logicpd/omap3som/omap3logic.c +0
-0
Applied to u-boot/master, thanks!
Signature · 8 lines
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