driver: net: ti: clean up and code optimization

index 595e3ca..7115d7b 100644
@@ -12,7 +12,7 @@
 #include <net.h>
 #include <dp83848.h>
 #include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 

index 3d02274..bfb7ff2 100644
@@ -9,7 +9,7 @@
 #include <net.h>
 #include <miiphy.h>
 #include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 

index 899cff0..85b0c26 100644
@@ -19,7 +19,7 @@
 #include <net.h>
 #include <asm/arch/emac_defs.h>
 #include <asm/io.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 int ksz8873_is_phy_connected(int phy_addr)
 {

index 170e4a5..b54f67d 100644
@@ -13,7 +13,7 @@
 #include <miiphy.h>
 #include <lxt971a.h>
 #include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 

similarity index 100%
rename from drivers/net/cpsw-common.c
rename to drivers/net/ti/cpsw-common.c

similarity index 100%
rename from drivers/net/cpsw.c
rename to drivers/net/ti/cpsw.c

similarity index 100%
rename from drivers/net/davinci_emac.c
rename to drivers/net/ti/davinci_emac.c

similarity index 100%
rename from drivers/net/davinci_emac.h
rename to drivers/net/ti/davinci_emac.h

similarity index 100%
rename from drivers/net/keystone_net.c
rename to drivers/net/ti/keystone_net.c

index cc823c5..5e504f6 100644
@@ -128,7 +128,6 @@
 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
 
 /* Keystone net */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
 #define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
 #define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE

index f89e043..bef1867 100644
@@ -242,18 +242,4 @@ struct mdio_regs {
 	u32 userphysel1;
 };
 
-struct eth_priv_t {
-	char int_name[32];
-	int rx_flow;
-	int phy_addr;
-	int slave_port;
-	int sgmii_link_type;
-	phy_interface_t phy_if;
-	struct phy_device *phy_dev;
-};
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
 #endif  /* _KEYSTONE_NET_H_ */

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index 250b649..d0cfbf5 100644
@@ -12,8 +12,6 @@
 #include <asm/ti-common/keystone_net.h>
 #include "../common/board_detect.h"
 
-extern struct eth_priv_t eth_priv_cfg[];
-
 #if defined(CONFIG_TI_I2C_BOARD_DETECT)
 static inline int board_is_k2g_gp(void)
 {

@@ -38,7 +36,6 @@ static inline int board_is_k2g_ice(void)
 }
 #endif
 
-int get_num_eth_ports(void);
 void spl_init_keystone_plls(void);
 
 #endif

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index 9bc94fb..87dc4d0 100644
@@ -354,24 +354,6 @@ void spl_init_keystone_plls(void)
 }
 #endif
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
-	{
-		.int_name	= "K2G_EMAC",
-		.rx_flow	= 0,
-		.phy_addr	= 0,
-		.slave_port	= 1,
-		.sgmii_link_type = SGMII_LINK_MAC_PHY,
-		.phy_if          = PHY_INTERFACE_MODE_RGMII,
-	},
-};
-
-int get_num_eth_ports(void)
-{
-	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
-}
-#endif
-
 #ifdef CONFIG_TI_SECURE_DEVICE
 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
 {

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index 8e2a48c..fe43d14 100644
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * CPSW Ethernet Switch Driver
  *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include <common.h>

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new file mode 100644
index 0000000..4a76d4e
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef CPSW_MDIO_H_
+#define CPSW_MDIO_H_
+
+struct cpsw_mdio;
+
+struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base,
+			       u32 bus_freq, int fck_freq);
+void cpsw_mdio_free(struct mii_dev *bus);
+u32 cpsw_mdio_get_alive(struct mii_dev *bus);
+
+#endif /* CPSW_MDIO_H_ */

index fe43d14..f5fd02e 100644
@@ -21,11 +21,11 @@
 #include <dm.h>
 #include <fdt_support.h>
 
+#include "cpsw_mdio.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BITMASK(bits)		(BIT(bits) - 1)
-#define PHY_REG_MASK		0x1f
-#define PHY_ID_MASK		0x1f
 #define NUM_DESCS		(PKTBUFSRX * 2)
 #define PKT_MIN			60
 #define PKT_MAX			(1500 + 14 + 4 + 4)

@@ -76,37 +76,8 @@ DECLARE_GLOBAL_DATA_PTR;
  * unexpected controller lock ups.  Ideally, we should never ever hit this
  * scenario in practice.
  */
-#define MDIO_TIMEOUT            100 /* msecs */
 #define CPDMA_TIMEOUT		100 /* msecs */
 
-struct cpsw_mdio_regs {
-	u32	version;
-	u32	control;
-#define CONTROL_IDLE		BIT(31)
-#define CONTROL_ENABLE		BIT(30)
-
-	u32	alive;
-	u32	link;
-	u32	linkintraw;
-	u32	linkintmasked;
-	u32	__reserved_0[2];
-	u32	userintraw;
-	u32	userintmasked;
-	u32	userintmaskset;
-	u32	userintmaskclr;
-	u32	__reserved_1[20];
-
-	struct {
-		u32		access;
-		u32		physel;
-#define USERACCESS_GO		BIT(31)
-#define USERACCESS_WRITE	BIT(30)
-#define USERACCESS_ACK		BIT(29)
-#define USERACCESS_READ		(0)
-#define USERACCESS_DATA		(0xffff)
-	} user[0];
-};
-
 struct cpsw_regs {
 	u32	id_ver;
 	u32	control;

@@ -484,100 +455,6 @@ static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 	__raw_writel(tmp, priv->ale_regs + offset);
 }
 
-static struct cpsw_mdio_regs *mdio_regs;
-
-/* wait until hardware is ready for another user access */
-static inline u32 wait_for_user_access(void)
-{
-	u32 reg = 0;
-	int timeout = MDIO_TIMEOUT;
-
-	while (timeout-- &&
-	((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
-		udelay(10);
-
-	if (timeout == -1) {
-		printf("wait_for_user_access Timeout\n");
-		return -ETIMEDOUT;
-	}
-	return reg;
-}
-
-/* wait until hardware state machine is idle */
-static inline void wait_for_idle(void)
-{
-	int timeout = MDIO_TIMEOUT;
-
-	while (timeout-- &&
-		((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
-		udelay(10);
-
-	if (timeout == -1)
-		printf("wait_for_idle Timeout\n");
-}
-
-static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
-				int dev_addr, int phy_reg)
-{
-	int data;
-	u32 reg;
-
-	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
-		return -EINVAL;
-
-	wait_for_user_access();
-	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
-	       (phy_id << 16));
-	__raw_writel(reg, &mdio_regs->user[0].access);
-	reg = wait_for_user_access();
-
-	data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
-	return data;
-}
-
-static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
-				int phy_reg, u16 data)
-{
-	u32 reg;
-
-	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
-		return -EINVAL;
-
-	wait_for_user_access();
-	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
-		   (phy_id << 16) | (data & USERACCESS_DATA));
-	__raw_writel(reg, &mdio_regs->user[0].access);
-	wait_for_user_access();
-
-	return 0;
-}
-
-static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
-{
-	struct mii_dev *bus = mdio_alloc();
-
-	mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
-
-	/* set enable and clock divider */
-	__raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
-
-	/*
-	 * wait for scan logic to settle:
-	 * the scan time consists of (a) a large fixed component, and (b) a
-	 * small component that varies with the mii bus frequency.  These
-	 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
-	 * silicon.  Since the effect of (b) was found to be largely
-	 * negligible, we keep things simple here.
-	 */
-	udelay(1000);
-
-	bus->read = cpsw_mdio_read;
-	bus->write = cpsw_mdio_write;
-	strcpy(bus->name, name);
-
-	mdio_register(bus);
-}
-
 /* Set a self-clearing bit in a register, and wait for it to clear */
 static inline void setbit_and_wait_for_clear32(void *addr)
 {

@@ -1003,7 +880,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
 {
 	struct cpsw_platform_data *data = &priv->data;
-	u16 alive = mdio_regs->alive & GENMASK(15, 0);
+	u16 alive = cpsw_mdio_get_alive(priv->bus);
 	int active = data->active_slave;
 	int new_addr = ffs(alive) - 1;
 

@@ -1044,11 +921,12 @@ int _cpsw_register(struct cpsw_priv *priv)
 		idx = idx + 1;
 	}
 
-	cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
+	priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
+	if (!priv->bus)
+		return -EFAULT;
 
 	cpsw_phy_addr_update(priv);
 
-	priv->bus = miiphy_get_dev_by_name(priv->dev->name);
 	for_active_slave(slave, priv)
 		cpsw_phy_init(priv, slave);
 

index bef1867..bba1048 100644
@@ -57,19 +57,6 @@
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ		2500000	/* 2.5 MHz */
 
-/* MII Status Register */
-#define MII_STATUS_REG			1
-#define MII_STATUS_LINK_MASK		0x4
-
-#define MDIO_CONTROL_IDLE		0x80000000
-#define MDIO_CONTROL_ENABLE		0x40000000
-#define MDIO_CONTROL_FAULT_ENABLE	0x40000
-#define MDIO_CONTROL_FAULT		0x80000
-#define MDIO_USERACCESS0_GO		0x80000000
-#define MDIO_USERACCESS0_WRITE_READ	0x0
-#define MDIO_USERACCESS0_WRITE_WRITE	0x40000000
-#define MDIO_USERACCESS0_ACK		0x20000000
-
 #define EMAC_MACCONTROL_MIIEN_ENABLE		0x20
 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	0x1
 #define EMAC_MACCONTROL_GIGABIT_ENABLE		BIT(7)

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