mmc: renesas_sdhi: remove workaround for HS400 clock
Subsystems (2)
PATCH 1/1 mmc: renesas_sdhi: remove workaround for HS400 clock
From: Niklas Söderlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
--- drivers/mmc/host/renesas_sdhi_core.c | 9 --------- 1 file changed, 9 deletions(-)
drivers/mmc/host/renesas_sdhi_core.c +0 -9
@@ -163,15 +163,6 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,if (new_clock ==0 ) goto out; -/* -* Both HS400 and HS200/SD104 set 200MHz, but some devices need to -* set 400MHz to distinguish the CPG settings in HS400. -*/ -if (host->mmc->ios.timing ==MMC_TIMING_MMC_HS400 && - host->pdata->flags &TMIO_MMC_HAVE_4TAP_HS400 && - new_clock ==200000000 ) - new_clock =400000000 ; - clock =renesas_sdhi_clk_update (host, new_clock) /512 ;for (clk =0x80000080 ; new_clock >= (clock <<1 ); clk >>=1 )
Signature · 1 line
2.19.1
Quoted 9 lines · Niklas Söderlund
From: Niklas Söderlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
Signed-off-by Niklas Söderlund <[email protected]>
Quoted 9 lines · Niklas Söderlund
From: Niklas Söderlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
Signed-off-by Niklas Söderlund <[email protected]>
Quoted 9 lines · Niklas Söderlund
From: Niklas Söderlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
Signed-off-by Niklas Söderlund <[email protected]>
Does this change cause a regression pending an update to the clock driver?
Hi Simon,
Quoted 9 lines · Simon Horman
Quoted 8 lines · Niklas S�derlund
From: Niklas S�derlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
Quoted 4 lines
Quoted 1 line
Signed-off-by Niklas S�derlund <[email protected]>Does this change cause a regression pending an update to the clock driver?
No it does not, the corresponding BSP commit to the clock driver [1] was never part of upstream. This change should never have been merged upstream as it uses the hack from the BSP clock driver. Also HS400 have never been enabled upstream for Gen3.
1. 11fca067bde0221d ("clk: renesas: rcar-gen3: Fix SD divider setting")
Signature · 2 lines
Regards, Niklas S�derlund
Simon Horman
Reviewed-byQuoted 17 lines · Niklas Söderlund
Hi Simon,
Quoted 9 lines · Simon Horman
Quoted 8 lines · Niklas Söderlund
From: Niklas Söderlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
Quoted 4 lines
Quoted 1 line
Signed-off-by Niklas Söderlund <[email protected]>Does this change cause a regression pending an update to the clock driver?
Quoted 6 lines
No it does not, the corresponding BSP commit to the clock driver [1] was never part of upstream. This change should never have been merged upstream as it uses the hack from the BSP clock driver. Also HS400 have never been enabled upstream for Gen3.
1.
11fca067bde0221d("clk: renesas: rcar-gen3: Fix SD divider setting")
Thanks, got it.
Quoted 9 lines · Niklas Söderlund
From: Niklas Söderlund <[email protected]>
The driver sets an incorrect clock and depends on the clock driver knowledge of this incorrect setting to still set a 200Mhz SDn clock. Instead of spreading the workaround between the two drivers the clock driver should be made aware of the ES versions where the special clock handling is needed no need to keep this workaround in the SDHI driver.
Signed-off-by Niklas Söderlund <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
Quoted 27 lines
--- drivers/mmc/host/renesas_sdhi_core.c | 9 --------- 1 file changed, 9 deletions(-)drivers/mmc/host/renesas_sdhi_core.c +0
-10@@ -163,15 +163,6 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,if (new_clock ==0 ) goto out; -/* -* Both HS400 and HS200/SD104 set 200MHz, but some devices need to -* set 400MHz to distinguish the CPG settings in HS400. -*/ -if (host->mmc->ios.timing ==MMC_TIMING_MMC_HS400 && - host->pdata->flags &TMIO_MMC_HAVE_4TAP_HS400 && - new_clock ==200000000 ) - new_clock =400000000 ; - clock =renesas_sdhi_clk_update (host, new_clock) /512 ;for (clk =0x80000080 ; new_clock >= (clock <<1 ); clk >>=1 ) --2.19.1