OpenRISC port

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index 8261b796a47..d2beeb52a0e 100644
@@ -100,6 +100,9 @@ __aeabi_idiv0 (int return_value)
 #elif defined (__moxie__)
   /* Not all moxie configurations may raise exceptions.  */
 # define DO_TEST 0
+#elif defined (__or1k__)
+  /* On OpenRISC division by zero does not trap.  */
+# define DO_TEST 0
 #else
 # define DO_TEST 1
 #endif

index 1a8afd81506..e72a5b261ae 100644
@@ -117,6 +117,8 @@ extern void abort (void);
 # if defined (__CK807__) || defined (__CK810__)
 #   define PIC_REG  "r28"
 # endif
+#elif defined (__or1k__)
+/* No pic register.  */
 #else
 # error "Modify the test for your target."
 #endif

index 301a06fd464..e19f81a7624 100644
@@ -47,8 +47,8 @@ typedef __SIZE_TYPE__    size_t;
 
 /* The following tests fail because of missing range information.  The xfail
    exclusions are PR79356.  */
-TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX);   /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-* ia64-*-* mips*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390*-*-* visium-*-* } } } } */
-TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* ia64-*-* mips*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390x-*-* visium-*-* } } } } */
+TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX);   /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390*-*-* visium-*-* } } } } */
+TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390x-*-* visium-*-* } } } } */
 TEST (int, INT_MIN + 2, ALLOC_MAX);    /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
 TEST (int, -3, ALLOC_MAX);             /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
 TEST (int, -2, ALLOC_MAX);             /* { dg-warning "argument 1 range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */

index 3768caa5d5a..dd521973cae 100644
@@ -1,7 +1,7 @@
 /* { dg-do run } */
 /* { dg-require-effective-target untyped_assembly } */
 /* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-*" } } */
-/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-*" } } */
+/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-* or1k*-*-*" } } */
 /* { dg-skip-if "Variadic funcs use Base AAPCS.  Normal funcs use VFP variant." { arm*-*-* && arm_hf_eabi } } */
 
 /* PR target/12503 */

index a0c19a34414..23491a603f5 100644
@@ -2,6 +2,8 @@
 #define NOP "nop 0"
 #elif defined (__MMIX__)
 #define NOP "swym 0"
+#elif defined (__or1k__)
+#define NOP "l.nop"
 #else
 #define NOP "nop"
 #endif

index d033010dc7c..3f8d350ba8f 100644
@@ -9,7 +9,7 @@
 /* arm_hf_eabi: Variadic funcs use Base AAPCS.  Normal funcs use VFP variant.
    avr: Variadic funcs don't pass arguments in registers, while normal funcs
         do.  */
-/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* } } } */
+/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* or1k*-*-* } } } */
 /* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } } */
 /* { dg-require-effective-target untyped_assembly } */
    

index a1237cf839b..bc486e32586 100644
@@ -33,4 +33,4 @@ void test55 (int x, int y)
    that the && should be emitted (based on BRANCH_COST).  Fix this
    by teaching dom to look through && and register all components
    as true.  */
-/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-* sparc*-*-* spu-*-* visium-*-* x86_64-*-* riscv*-*-*" } } } } */
+/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-* sparc*-*-* spu-*-* visium-*-* x86_64-*-* riscv*-*-* or1k*-*-*" } } } } */

index 5572df4ae24..243508c872c 100644
@@ -1,4 +1,4 @@
-/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
+/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k-*-*-*"} } } */
 
 /* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
 /* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

index 9b45f1cd9be..24070046ef2 100644
@@ -1,4 +1,4 @@
-/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
+/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k*-*-*"} } } */
 
 /* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
 /* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

index 9ee3abca04e..e5ba101e001 100644
@@ -1,4 +1,4 @@
-/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
+/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k*-*-*"} } } */
 
 /* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
 /* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

index ac3a04291b7..4df5840859c 100644
@@ -1,4 +1,4 @@
-/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-*"} } } */
+/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k*-*-*"} } } */
 
 /* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details" } */
 /* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

new file mode 100644
index 00000000000..7538705d07f
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct a {
+  long x;
+  long y;
+  long z;
+};
+
+int passlibstruct (int b, struct a aa);
+
+int main() {
+  struct a aa = { 55, 66, 77 };
+
+  return passlibstruct(-1, aa);
+}
+
+/* Ensure we pass a stack reference in the second arg.  */
+/* { dg-final { scan-assembler-times "r4, r1, " 1 } } */

new file mode 100644
index 00000000000..362f7c0c9e9
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct a {
+  long x;
+  long y;
+  long z;
+};
+
+int passstruct (int b, struct a aa) {
+  return aa.z + aa.y + b;
+}
+
+/* Ensure our struct reads are offset from the address in arg 2.  */
+/* { dg-final { scan-assembler-times "l.lwz\\s+r\\d+, \\d+.r4." 2 } } */

new file mode 100644
index 00000000000..c66b67c07c7
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmov -O2" } */
+
+int cond (int a, int b) {
+  return a > b;
+}
+
+/* { dg-final { scan-assembler "l.cmov" } } */

new file mode 100644
index 00000000000..9b3b5529740
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { *-*-* }  { "-mcmov" } { "" } } */
+
+int cond (int a, int b) {
+  return a > b;
+}
+
+/* { dg-final { scan-assembler-not "l.cmov" } } */

new file mode 100644
index 00000000000..a5e8d286545
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msoft-mul -msoft-div" } */
+
+int calc (int a, int b, int c) {
+  return a * b / c;
+}
+
+/* { dg-final { scan-assembler-not "l.mul" } } */
+/* { dg-final { scan-assembler-not "l.div" } } */

new file mode 100644
index 00000000000..a567d7d9f50
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msoft-div" } */
+
+int calc (int a, int b, int c) {
+  return a * b / c;
+}
+
+/* { dg-final { scan-assembler "l.mul" } } */
+/* { dg-final { scan-assembler-not "l.div" } } */

new file mode 100644
index 00000000000..6dd04197164
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long calc (long long a, long long b) {
+  return a * b + 5;
+}
+
+/* Ensure our return value is set in the r11, r12 pair.  */
+/* { dg-final { scan-assembler "r11," } } */
+/* { dg-final { scan-assembler "r12," } } */

new file mode 100644
index 00000000000..c072ae23142
@@ -0,0 +1,19 @@
+/* Large structs are returned at a memory address passed in r3.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct a {
+  long x;
+  long y;
+  long z;
+};
+
+struct a getstruct (long aa) {
+  struct a as = { 22, aa, -5 };
+  return as;
+}
+
+/* Ensure our return value is returned on stack.  */
+/* { dg-final { scan-assembler-not "r12," } } */
+/* { dg-final { scan-assembler "l.or\\s+r11, r3, r3" } } */
+/* { dg-final { scan-assembler-times "l.sw\\s+\\d+.r3.," 3 } } */

new file mode 100644
index 00000000000..5c2e5f5ad91
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct a {
+  long x;
+  long y;
+  long z;
+};
+
+struct a getlibstruct (long aa);
+
+int main() {
+  struct a rs = getlibstruct(123);
+
+  return rs.x;
+}
+
+/* Ensure our return value is read from memory.  */
+/* { dg-final { scan-assembler "l.lwz\\s+r11," } } */

new file mode 100644
index 00000000000..b866f58a307
@@ -0,0 +1,19 @@
+/* Test to ensure small structs are returned in memory too.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct a {
+  long x;
+  long y;
+};
+
+struct a getlibstruct (long aa);
+
+int main() {
+  struct a rs = getlibstruct(123);
+
+  return rs.x;
+}
+
+/* Ensure our return value is read from memory.  */
+/* { dg-final { scan-assembler "l.lwz\\s+r11," } } */

new file mode 100644
index 00000000000..df55a6adfef
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mror -O2" } */
+
+unsigned int rotate (unsigned int a, int b) {
+  return ( a >> b ) | ( a << ( 32 - b ) );
+}
+
+/* { dg-final { scan-assembler "l.ror" } } */

new file mode 100644
index 00000000000..9cd7f35d285
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { *-*-* }  { "-mror" } { "" } } */
+
+unsigned int rotate (unsigned int a, int b) {
+  return ( a >> b ) | ( a << ( 32 - b ) );
+}
+
+/* { dg-final { scan-assembler-not "l.ror" } } */

new file mode 100644
index 00000000000..b0a73b3064d
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mror -O2" } */
+
+unsigned int rotate6 (unsigned int a) {
+  return ( a >> 6 ) | ( a << ( 32 - 6 ) );
+}
+
+/* { dg-final { scan-assembler-not "l.rori" } } */

new file mode 100644
index 00000000000..be8d9e8b895
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mror -mshftimm -O2" } */
+
+unsigned int rotate6 (unsigned int a) {
+  return ( a >> 6 ) | ( a << ( 32 - 6 ) );
+}
+
+/* { dg-final { scan-assembler "l.rori" } } */

new file mode 100644
index 00000000000..ef9b52f2820
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mshftimm -O2" } */
+
+unsigned int shift6 (unsigned int a) {
+  return a >> 6;
+}
+
+/* { dg-final { scan-assembler "l.srli" } } */

new file mode 100644
index 00000000000..8134f0cfe35
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Just create some dummy call that should trigger sibcall, no
+   stack logic.  */
+int calc (int a, int b, int c) {
+  if (c <= 0) return a;
+  return calc (a * b, b, --c);
+}
+
+int main() {
+   return calc (4, 3, 4);
+}
+
+/* Ensure sibcalls do not need to manipulate the stack.  */
+/* { dg-final { scan-assembler-not "r1," } } */
+/* Ensure sibcall maintains the body of the function.  */
+/* { dg-final { scan-assembler "l.mul" } } */

new file mode 100644
index 00000000000..044e843fd19
@@ -0,0 +1,41 @@
+/* Common hooks for OpenRISC
+   Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "diagnostic-core.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+
+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
+static const struct default_options or1k_option_optimization_table[] =
+  {
+    /* Enable section anchors by default at -O1 or higher.  */
+    { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
+  };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE or1k_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

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new file mode 100644
index 00000000000..e18383ae781
@@ -0,0 +1,38 @@
+/* Prototypes for OpenRISC functions used in the md file & elsewhere.
+   Copyright (C) 2018 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+extern HOST_WIDE_INT or1k_initial_elimination_offset (int, int);
+extern void or1k_expand_prologue (void);
+extern void or1k_expand_epilogue (void);
+extern void or1k_expand_eh_return (rtx);
+extern rtx  or1k_initial_frame_addr (void);
+extern rtx  or1k_dynamic_chain_addr (rtx);
+extern rtx  or1k_return_addr (int, rtx);
+extern void or1k_expand_move (machine_mode, rtx, rtx);
+extern void or1k_expand_compare (rtx *);
+extern void or1k_expand_call (rtx, rtx, rtx, bool);
+
+#ifdef RTX_CODE
+void or1k_expand_atomic_compare_and_swap (rtx operands[]);
+void or1k_expand_atomic_compare_and_swap_qihi (rtx operands[]);
+void or1k_expand_atomic_exchange (rtx operands[]);
+void or1k_expand_atomic_exchange_qihi (rtx operands[]);
+void or1k_expand_atomic_op (rtx_code, rtx, rtx, rtx, rtx);
+void or1k_expand_atomic_op_qihi (rtx_code, rtx, rtx, rtx, rtx);
+#endif

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