sunxi-mmc: enable new clock mode on A64

A64 requires new clock mode on SD and eMMC controllers. Not using new clock mode causes stability issues of the driver - SPL may occasionally fail to load u-boot from SD for some particular SD card on some particular devices.

This series depends on "sunxi: add support for automatic delay calibration" from my Pinebook series.

Tested on Pinebook and Pine64-LTS.

Vasily Khoruzhick (3):
sunxi-mmc: introduce new MMC_SUNXI_HAS_NEW_MODE_SWITCH option
sunxi-mmc: don't double clock for new mode unconditionally
sunxi-mmc: use new mode on both controllers on A64

 arch/arm/mach-sunxi/Kconfig |  2 ++
 drivers/mmc/Kconfig         |  4 ++++
 drivers/mmc/sunxi_mmc.c     | 19 +++++++++----------
 3 files changed, 15 insertions(+), 10 deletions(-)

2.19.1

A64 doesn't have a mode switch in CCM, so introduce new MMC_SUNXI_HAS_NEW_MODE_SWITCH option to support new clock mode on A64

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 drivers/mmc/Kconfig         | 4 ++++
 drivers/mmc/sunxi_mmc.c     | 2 ++
 3 files changed, 7 insertions(+)

index 560dc9b25d..66fff6c6d3 100644
@@ -230,6 +230,7 @@ config MACH_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
+	select MMC_SUNXI_HAS_MODE_SWITCH
 	select SUPPORT_SPL
 
 config MACH_SUN8I_H3

index 27246ee465..3f7458d409 100644
@@ -569,6 +569,10 @@ config MMC_SUNXI_HAS_NEW_MODE
 	bool
 	depends on MMC_SUNXI
 
+config MMC_SUNXI_HAS_MODE_SWITCH
+	bool
+	depends on MMC_SUNXI
+
 config GENERIC_ATMEL_MCI
 	bool "Atmel Multimedia Card Interface support"
 	depends on DM_MMC && BLK && ARCH_AT91

index 147eb9b4d5..b3526f5e3f 100644
@@ -176,7 +176,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 
 	if (new_mode) {
 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
 		val = CCM_MMC_CTRL_MODE_SEL_NEW;
+#endif
 		setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 #endif
 	} else if (!calibrate) {

2.19.1

This patch isn't strictly necessary. See

    https://elixir.bootlin.com/linux/v4.20-rc1/source/drivers/mmc/host/sunxi-mmc.c#L831

If the switch doesn't exist, changes to that bit are ignored.

ChenYu

CCM_MMC_CTRL_MODE_SEL_NEW is not defined on A64, so it won't compile unless we define it on A64 which seems to be redundant.

OK. That makes sense then. You should mention that in the commit message, as that is exactly the reason why this patch is needed.

On the other hand, having hardware device registers defined at the arch level is kind of hard to keep track of.

ChenYu

Comment in Linux driver says that clock needs to be doubled only if we use DDR modes, moreover divider has to be set accordingly.

U-boot driver doesn't declare support for any DDR modes and doesn't set divider, so it doubles clock unconditionally when new mode is used.

Some cards can't handle that and as result SPL fails to load u-boot.

---
 drivers/mmc/sunxi_mmc.c | 7 -------
 1 file changed, 7 deletions(-)

index b3526f5e3f..e50b2c3343 100644
@@ -109,13 +109,6 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 	calibrate = true;
 #endif
 
-	/*
-	 * The MMC clock has an extra /2 post-divider when operating in the new
-	 * mode.
-	 */
-	if (new_mode)
-		hz = hz * 2;
-
 	if (hz <= 24000000) {
 		pll = CCM_MMC_CTRL_OSCM24;
 		pll_hz = 24000000;

2.19.1

doesn't set the card clock divider, so the card is running at the module clock's rate. This would be a bit clearer.

ChenYu

Using new mode improves stability of eMMC and SD cards. Without it SPl fails to load u-boot from SD on Pinebook.

---
 arch/arm/mach-sunxi/Kconfig |  1 +
 drivers/mmc/sunxi_mmc.c     | 10 +++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

index 66fff6c6d3..3c54f5106d 100644
@@ -282,6 +282,7 @@ config MACH_SUN50I
 	select SUN6I_PRCM
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
+	select MMC_SUNXI_HAS_NEW_MODE
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT

index e50b2c3343..2b6f3c2234 100644
@@ -98,12 +98,16 @@ static int mmc_resource_init(int sdc_no)
 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
-	bool new_mode = false;
+	bool new_mode = true;
 	bool calibrate = false;
 	u32 val = 0;
 
-	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
-		new_mode = true;
+	if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
+		new_mode = false;
+
+	/* A83 support new mode only on eMMC */
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
+		new_mode = false;
 
 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
 	calibrate = true;

2.19.1