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linux/sizes.h: sync from kernel

PATCH New Baruch Siach 2 participants 3 messages Nov 7, 2018

Subsystems (4)
Arm (32-bit) Arm sub-architectures Tegra architecture support Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support
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Baruch Siach

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#0 lore raw

PATCH v2 1/2 linux/sizes.h: sync from kernel

The kernel added SZ_4G macro in commit f2b9ba871b (arm64/kernel: kaslr:
reduce module randomization range to 4 GB).

Include common.h for _AC() instead of the kernel linux/const.h header.

Drop a local SZ_4G definition in tegra code.

Cc Tom Warren <[email protected]>
Signed-off-by Baruch Siach <[email protected]>

---
v2: No change

---
 arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 3 +--
 include/linux/sizes.h                      | 4 ++++
 2 files changed, 5 insertions(+), 2 deletions(-)
arch/arm/mach-tegra/tegra186/nvtboot_mem.c +1 -2
index 5c9467bfe8be..62142821a595 100644
@@ -6,11 +6,10 @@
 #include <common.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <linux/sizes.h>
 #include <asm/arch/tegra.h>
 #include <asm/armv8/mmu.h>
 
-#define SZ_4G 0x100000000ULL
-
 /*
  * Size of a region that's large enough to hold the relocated U-Boot and all
  * other allocations made around it (stack, heap, page tables, etc.)
include/linux/sizes.h +4 -0
index ce3e8150c174..9f3c13ee459b 100644
@@ -8,6 +8,8 @@
 #ifndef __LINUX_SIZES_H__
 #define __LINUX_SIZES_H__
 
+#include <common.h>
+
 #define SZ_1				0x00000001
 #define SZ_2				0x00000002
 #define SZ_4				0x00000004

@@ -44,4 +46,6 @@
 #define SZ_1G				0x40000000
 #define SZ_2G				0x80000000
 
+#define SZ_4G				_AC(0x100000000, ULL)
+
 #endif /* __LINUX_SIZES_H__ */
Signature · 1 line
2.19.1
author
#1 lore raw

PATCH v2 2/2 arm64: mvebu: a8k: autodetect RAM size

Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from external DIMM. Hard coding the RAM size in the device-tree is not convenient. Fortunately, the ATF that initializes the RAM knows the size of RAM, and U-Boot can query the ATF using a SMC call.

The ATF maps the lower 3G of RAM starting at address 0. Higher RAM is mapped at 4G. This leaves a 1G hole between 3G and 4G for IO peripherals. Use a second bi_dram[] entry to describe the higher RAM area. As a result, CONFIG_NR_DRAM_BANKS must be set to 2 to use more than 3GB RAM.

This code in this commit is mostly taken from downstream Marvell U-Boot code by Grzegorz Jaszczyk.

Cc Grzegorz Jaszczyk <[email protected]>
Signed-off-by Baruch Siach <[email protected]>

---
v2:
Expand memory layout description in code comment and the commit log (Stefan)

---
 arch/arm/mach-mvebu/arm64-common.c | 50 +++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)
arch/arm/mach-mvebu/arm64-common.c +49 -1
index f47273fde9c6..47bbf69944ec 100644
@@ -7,6 +7,7 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <linux/libfdt.h>
+#include <linux/sizes.h>
 #include <pci.h>
 #include <asm/io.h>
 #include <asm/system.h>

@@ -45,15 +46,62 @@ const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
 
 /* DRAM init code ... */
 
+#define MV_SIP_DRAM_SIZE	0x82000010
+
+static u64 a8k_dram_scan_ap_sz(void)
+{
+	struct pt_regs pregs;
+
+	pregs.regs[0] = MV_SIP_DRAM_SIZE;
+	pregs.regs[1] = SOC_REGS_PHY_BASE;
+	smc_call(&pregs);
+
+	return pregs.regs[0];
+}
+
+static void a8k_dram_init_banksize(void)
+{
+	/*
+	 * The firmware (ATF) leaves a 1G whole above the 3G mark for IO
+	 * devices. Higher RAM is mapped at 4G.
+	 *
+	 * Config 2 DRAM banks:
+	 * Bank 0 - max size 4G - 1G
+	 * Bank 1 - ram size - 4G + 1G
+	 */
+	phys_size_t max_bank0_size = SZ_4G - SZ_1G;
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size <= max_bank0_size) {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+		return;
+	}
+
+	gd->bd->bi_dram[0].size = max_bank0_size;
+	if (CONFIG_NR_DRAM_BANKS > 1) {
+		gd->bd->bi_dram[1].start = SZ_4G;
+		gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
+	}
+}
+
 int dram_init_banksize(void)
 {
-	fdtdec_setup_memory_banksize();
+	if (CONFIG_IS_ENABLED(ARMADA_8K))
+		a8k_dram_init_banksize();
+	else
+		fdtdec_setup_memory_banksize();
 
 	return 0;
 }
 
 int dram_init(void)
 {
+	if (CONFIG_IS_ENABLED(ARMADA_8K)) {
+		gd->ram_size = a8k_dram_scan_ap_sz();
+		if (gd->ram_size != 0)
+			return 0;
+	}
+
 	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;
Signature · 1 line
2.19.1
#2 lore raw

PATCH v2 1/2 linux/sizes.h: sync from kernel

In reply to Baruch Siach
Quoted 47 lines · Baruch Siach

The kernel added SZ_4G macro in commit f2b9ba871b (arm64/kernel: kaslr:
reduce module randomization range to 4 GB).

Include common.h for _AC() instead of the kernel linux/const.h header.

Drop a local SZ_4G definition in tegra code.

Cc Tom Warren <[email protected]>
Signed-off-by Baruch Siach <[email protected]>

---
v2: No change

---
 arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 3 +--
 include/linux/sizes.h                      | 4 ++++
 2 files changed, 5 insertions(+), 2 deletions(-)
arch/arm/mach-tegra/tegra186/nvtboot_mem.c +1 -2
index 5c9467bfe8be..62142821a595 100644
@@ -6,11 +6,10 @@
 #include <common.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <linux/sizes.h>
 #include <asm/arch/tegra.h>
 #include <asm/armv8/mmu.h>
 
-#define SZ_4G 0x100000000ULL
-
 /*
  * Size of a region that's large enough to hold the relocated U-Boot and all
  * other allocations made around it (stack, heap, page tables, etc.)
include/linux/sizes.h +2 -0
index ce3e8150c174..9f3c13ee459b 100644
@@ -8,6 +8,8 @@
 #ifndef __LINUX_SIZES_H__
 #define __LINUX_SIZES_H__
 
+#include <common.h>
+
 #define SZ_1				0x00000001
 #define SZ_2				0x00000002
 #define SZ_4				0x00000004

include/linux/sizes.h line 51

Quoted 6 lines
include/linux/sizes.h +2 -0
@@ -44,4 +46,6 @@
 #define SZ_1G				0x40000000
 #define SZ_2G				0x80000000
 
+#define SZ_4G				_AC(0x100000000, ULL)
+
 #endif /* __LINUX_SIZES_H__ */

I think this is moving things in the wrong direction. In fact, 2a6713b09b8da58572338abac276aa764bb6eadd took things in the wrong direction. We need to import linux/const.h (and just combine uapi/linux/const.h with linux/const.h) with the _AC macro and then add in SZ_4G.

Signature · 8 lines
Tom
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