arm64: dts: qcom: qcs404: Add Device tree nodes

PATCH Superseded Vinod Koul 1 participant 20 messages Nov 8, 2018

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Vinod Koul

author

2018-11-08 17:50 UTC #0 lore raw

v3 cover arm64: dts: qcom: qcs404: Add Device tree nodes

This series adds support for various nodes for QCS404-EVB.

Based on v4.20-rc1

Changes in v3:
- Make the DTS files sorted alphabetcially and by node addresses
- Add reviewed by from Bjorn
- Split out the DTS files for EVB 1000 and EVB 4000 boards and add common evb dts files for common part

Changes in v2:
Fix cpu binding

Bjorn Andersson (7):
arm64: dts: qcom: qcs404: Add reserved-memory regions
arm64: dts: qcom: qcs404: Add RPM GLINK related nodes
arm64: dts: qcom: qcs404: Add PMS405 RPM regulators
arm64: dts: qcom: qcs404: Add TLMM pinctrl node
arm64: dts: qcom: qcs404: Add sdcc1 node
arm64: dts: qcom: qcs404: Add scm firmware node
arm64: dts: qcom: qcs404: Add remoteproc nodes

Vinod Koul (11):
arm64: dts: qcom: qcs404: add base dts files
arm64: dts: qcom: qcs404-evb: add dts files for EVBs
arm64: dts: qcom: qcs404: add smp2p nodes
arm64: dts: qcom: pms405: add spmi node
arm64: dts: qcom: qcs404: add spmi node
arm64: dts: qcom: pms405: add rtc node
arm64: dts: qcom: pms405: add gpios
arm64: dts: qcom: qcs404: add prng-ee node
arm64: dts: qcom: qcs404: Add BAM DMA node
arm64: dts: qcom: qcs404: Use BAM DMA for serial uart2
arm64: dts: qcom: pms405: Add pon and pwrkey nodes

 arch/arm64/boot/dts/qcom/Makefile            |   2 +
 arch/arm64/boot/dts/qcom/pms405.dtsi         |  52 +++
 arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts |  11 +
 arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts |  11 +
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi     | 188 ++++++++++
 arch/arm64/boot/dts/qcom/qcs404.dtsi         | 490 +++++++++++++++++++++++++++
 6 files changed, 754 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pms405.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #1 lore raw

PATCH v3 1/18 arm64: dts: qcom: qcs404: add base dts files

Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes.

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++
 1 file changed, 175 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi

arch/arm64/boot/dts/qcom/qcs404.dtsi new file +175 -0

new file mode 100644
index 000000000000..b77d1198ba79
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, Linaro Limited
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x0 0 0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc: soc@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-qcs404";
+			reg = <0x01800000 0x80000>;
+			#clock-cells = <1>;
+
+			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
+			assigned-clock-rates = <19200000>;
+		};
+
+		blsp1_uart2: serial@78b1000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b1000 0x200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "okay";
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0b000000 0x1000>,
+			      <0x0b002000 0x1000>;
+		};
+
+		timer@b120000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b120000 0x1000>;
+			clock-frequency = <19200000>;
+
+			frame@b121000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b121000 0x1000>,
+				      <0x0b122000 0x1000>;
+			};
+
+			frame@b123000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b123000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b124000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b125000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b126000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0xb127000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0b128000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 0xff08>,
+			     <GIC_PPI 3 0xff08>,
+			     <GIC_PPI 4 0xff08>,
+			     <GIC_PPI 1 0xff08>;
+	};
+};

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #2 lore raw

PATCH v3 2/18 arm64: dts: qcom: qcs404-evb: add dts files for EVBs

In reply to Vinod Koul

QCS404 has two EVBs, EVB-1000 and EVB-4000. These boards are mostly similar with few differences in the peripherals used.

So use a common qcs404-evb.dtsi which contains the common parts and use qcs404-evb-1000.dts and qcs404-evb-4000.dts for diffs

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/Makefile            |  2 ++
 arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts | 11 +++++++++++
 arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 11 +++++++++++
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi     | 14 ++++++++++++++
 4 files changed, 38 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi

arch/arm64/boot/dts/qcom/Makefile +2 -0

index a658c07652a7..21d548f02d39 100644
@@ -8,3 +8,5 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-angler-rev-101.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb

arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts new file +11 -0

new file mode 100644
index 000000000000..2c14903d808e
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, Linaro Limited
+
+/dts-v1/;
+
+#include "qcs404-evb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
+	compatible = "qcom,qcs404-evb";
+};

arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts new file +11 -0

new file mode 100644
index 000000000000..11269ad3de0d
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, Linaro Limited
+
+/dts-v1/;
+
+#include "qcs404-evb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
+	compatible = "qcom,qcs404-evb";
+};

arch/arm64/boot/dts/qcom/qcs404-evb.dtsi new file +14 -0

new file mode 100644
index 000000000000..91ecbdf0ecda
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, Linaro Limited
+
+#include "qcs404.dtsi"
+
+/ {
+	aliases {
+		serial0 = &blsp1_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #3 lore raw

PATCH v3 3/18 arm64: dts: qcom: qcs404: Add reserved-memory regions

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add the reserved memory regions in QCS404

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 41 ++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +41 -0

index b77d1198ba79..58aa1f989089 100644
@@ -73,6 +73,47 @@
 		method = "smc";
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		memory@85600000 {
+			reg = <0 0x85600000 0 0x90000>;
+			no-map;
+		};
+
+		smem_region: memory@85f00000 {
+			reg = <0 0x85f00000 0 0x200000>;
+			no-map;
+		};
+
+		memory@86100000 {
+			reg = <0 0x86100000 0 0x300000>;
+			no-map;
+		};
+
+		wlan_fw_mem: memory@86400000 {
+			reg = <0 0x86400000 0 0x1c00000>;
+			no-map;
+		};
+
+		adsp_fw_mem: memory@88000000 {
+			reg = <0 0x88000000 0 0x1a00000>;
+			no-map;
+		};
+
+		cdsp_fw_mem: memory@89a00000 {
+			reg = <0 0x89a00000 0 0x600000>;
+			no-map;
+		};
+
+		wlan_msa_mem: memory@8a000000 {
+			reg = <0 0x8a000000 0 0x100000>;
+			no-map;
+		};
+	};
+
 	soc: soc@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #4 lore raw

PATCH v3 4/18 arm64: dts: qcom: qcs404: Add RPM GLINK related nodes

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add RPM GLINK node and the RPM message ram, hwspinlock, APCS apps global and smem nodes it depends on.

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 44 ++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +44 -0

index 58aa1f989089..e21b4a549e75 100644
@@ -114,12 +114,45 @@
 		};
 	};
 
+	rpm-glink {
+		compatible = "qcom,glink-rpm";
+
+		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		mboxes = <&apcs_glb 0>;
+
+		rpm_requests: glink-channel {
+			compatible = "qcom,rpm-qcs404";
+			qcom,glink-channels = "rpm_requests";
+		};
+	};
+
+	smem {
+		compatible = "qcom,smem";
+
+		memory-region = <&smem_region>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_regs 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
 	soc: soc@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 		compatible = "simple-bus";
 
+		rpm_msg_ram: memory@60000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00060000 0x6000>;
+		};
+
 		gcc: clock-controller@1800000 {
 			compatible = "qcom,gcc-qcs404";
 			reg = <0x01800000 0x80000>;

@@ -129,6 +162,11 @@
 			assigned-clock-rates = <19200000>;
 		};
 
+		tcsr_mutex_regs: syscon@1905000 {
+			compatible = "syscon";
+			reg = <0x01905000 0x20000>;
+		};
+
 		blsp1_uart2: serial@78b1000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x078b1000 0x200>;

@@ -146,6 +184,12 @@
 			      <0x0b002000 0x1000>;
 		};
 
+		apcs_glb: mailbox@b011000 {
+			compatible = "qcom,qcs404-apcs-apps-global", "syscon";
+			reg = <0x0b011000 0x1000>;
+			#mbox-cells = <1>;
+		};
+
 		timer@b120000 {
 			#address-cells = <1>;
 			#size-cells = <1>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #5 lore raw

PATCH v3 5/18 arm64: dts: qcom: qcs404: Add PMS405 RPM regulators

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add the RPM regulators found in PMS405 which is used in qcs404-evb

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 97 ++++++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)

arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +97 -0

index 91ecbdf0ecda..fc83e935aaa1 100644
@@ -11,4 +11,101 @@
 	chosen {
 		stdout-path = "serial0";
 	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&rpm_requests {
+	pms405-regulators {
+		compatible = "qcom,rpm-pms405-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+		vdd_s5-supply = <&vph_pwr>;
+		vdd_l1_l2-supply = <&vreg_s5_1p35>;
+		vdd_l3_l8-supply = <&vreg_s5_1p35>;
+		vdd_l4-supply = <&vreg_s5_1p35>;
+		vdd_l5_l6-supply = <&vreg_s4_1p8>;
+		vdd_l7-supply = <&vph_pwr>;
+		vdd_l9-supply = <&vreg_s5_1p35>;
+		vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
+
+		vreg_s4_1p8: s4 {
+			regulator-min-microvolt = <1728000>;
+			regulator-max-microvolt = <1920000>;
+		};
+
+		vreg_s5_1p35: s5 {
+			regulator-min-microvolt = <>;
+			regulator-max-microvolt = <>;
+		};
+
+		vreg_l1_1p3: l1 {
+			regulator-min-microvolt = <1240000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_l2_1p275: l2 {
+			regulator-min-microvolt = <1048000>;
+			regulator-max-microvolt = <1280000>;
+		};
+
+		vreg_l3_1p05: l3 {
+			regulator-min-microvolt = <976000>;
+			regulator-max-microvolt = <1160000>;
+		};
+
+		vreg_l4_1p2: l4 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1256000>;
+		};
+
+		vreg_l5_1p8: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vreg_l6_1p8: l6 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vreg_l7_1p8: l7 {
+			regulator-min-microvolt = <1616000>;
+			regulator-max-microvolt = <3000000>;
+		};
+
+		vreg_l8_1p2: l8 {
+			regulator-min-microvolt = <1136000>;
+			regulator-max-microvolt = <1352000>;
+		};
+
+		vreg_l10_3p3: l10 {
+			regulator-min-microvolt = <2936000>;
+			regulator-max-microvolt = <3088000>;
+		};
+
+		vreg_l11_sdc2: l11 {
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+		};
+
+		vreg_l12_3p3: l12 {
+			regulator-min-microvolt = <2968000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		vreg_l13_3p3: l13 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
 };

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #6 lore raw

PATCH v3 6/18 arm64: dts: qcom: qcs404: add smp2p nodes

In reply to Vinod Koul

Add the smp2p-adsp, smp2p-cdsp and smp2p-wcss nodes found in QCS404.

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 60 ++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +60 -0

index e21b4a549e75..cc4dd3186ae9 100644
@@ -257,4 +257,64 @@
 			     <GIC_PPI 4 0xff08>,
 			     <GIC_PPI 1 0xff08>;
 	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 10>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wcss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 18>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		wcss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wcss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
 };

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #7 lore raw

PATCH v3 7/18 arm64: dts: qcom: qcs404: Add TLMM pinctrl node

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add the QCS404 TLMM pinctrl node with its three tiles.

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +14 -0

index cc4dd3186ae9..3b6e659e3d1f 100644
@@ -153,6 +153,20 @@
 			reg = <0x00060000 0x6000>;
 		};
 
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,qcs404-pinctrl";
+			reg = <0x01000000 0x200000>,
+			      <0x01300000 0x200000>,
+			      <0x07b00000 0x200000>;
+			reg-names = "south", "north", "east";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-ranges = <&tlmm 0 0 120>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
 		gcc: clock-controller@1800000 {
 			compatible = "qcom,gcc-qcs404";
 			reg = <0x01800000 0x80000>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #8 lore raw

PATCH v3 8/18 arm64: dts: qcom: qcs404: Add sdcc1 node

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add the sdcc1 node and enable it for the QCS404-EVB.

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 64 ++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs404.dtsi     | 17 +++++++++
 2 files changed, 81 insertions(+)

arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +64 -0

index fc83e935aaa1..4d2ada8dec5d 100644
@@ -109,3 +109,67 @@
 		};
 	};
 };
+
+&sdcc1 {
+	status = "ok";
+
+	mmc-ddr-1_8v;
+	bus-width = <8>;
+	non-removable;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
+
+&tlmm {
+	sdc1_on: sdc1-on {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			dreive-strength = <10>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	sdc1_off: sdc1-off {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			dreive-strength = <2>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+};

arch/arm64/boot/dts/qcom/qcs404.dtsi +17 -0

index 3b6e659e3d1f..e83b7c233099 100644
@@ -181,6 +181,23 @@
 			reg = <0x01905000 0x20000>;
 		};
 
+		sdcc1: sdcc@7804000 {
+			compatible = "qcom,sdhci-msm-v5";
+			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
+			reg-names = "hc_mem", "cmdq_mem";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&xo_board>;
+			clock-names = "core", "iface", "xo";
+
+			status = "disabled";
+		};
+
 		blsp1_uart2: serial@78b1000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x078b1000 0x200>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #9 lore raw

PATCH v3 9/18 arm64: dts: qcom: pms405: add spmi node

In reply to Vinod Koul

Add the pms405 DT file with spmi node.

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/pms405.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pms405.dtsi

arch/arm64/boot/dts/qcom/pms405.dtsi new file +14 -0

new file mode 100644
index 000000000000..7b8104e21507
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, Linaro Limited
+
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	pms405_0: pms405@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+	};
+};

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #10 lore raw

PATCH v3 10/18 arm64: dts: qcom: qcs404: add spmi node

In reply to Vinod Koul

PMS405 is used in QCS405-EVB so include that with SPMI nodes

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi |  1 +
 arch/arm64/boot/dts/qcom/qcs404.dtsi     | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +1 -0

index 4d2ada8dec5d..cc5dfb319af8 100644
@@ -2,6 +2,7 @@
 // Copyright (c) 2018, Linaro Limited
 
 #include "qcs404.dtsi"
+#include "pms405.dtsi"
 
 / {
 	aliases {

arch/arm64/boot/dts/qcom/qcs404.dtsi +18 -0

index e83b7c233099..df07c494c47b 100644
@@ -181,6 +181,24 @@
 			reg = <0x01905000 0x20000>;
 		};
 
+		spmi_bus: spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x800000>,
+			      <0x02c00000 0x800000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x002100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
 		sdcc1: sdcc@7804000 {
 			compatible = "qcom,sdhci-msm-v5";
 			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #11 lore raw

PATCH v3 11/18 arm64: dts: qcom: pms405: add rtc node

In reply to Vinod Koul

RTC is found on PMIC PMS405 and is same as other PMIC used, so add the rtc node with compatible as qcom,pm8941-rtc

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/pms405.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm64/boot/dts/qcom/pms405.dtsi +6 -0

index 7b8104e21507..2b275bbdafa3 100644
@@ -10,5 +10,11 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+		};
 	};
 };

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #12 lore raw

PATCH v3 12/18 arm64: dts: qcom: pms405: add gpios

In reply to Vinod Koul

Add the GPIOs present on PMS405 chip.

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

arch/arm64/boot/dts/qcom/pms405.dtsi +16 -0

index 2b275bbdafa3..02b758cfd758 100644
@@ -10,6 +10,22 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		pms405_gpios: gpios@c000 {
+			compatible = "qcom,pms405-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <0 0xc1 0 IRQ_TYPE_NONE>,
+				<0 0xc2 0 IRQ_TYPE_NONE>,
+				<0 0xc3 0 IRQ_TYPE_NONE>,
+				<0 0xc4 0 IRQ_TYPE_NONE>,
+				<0 0xc5 0 IRQ_TYPE_NONE>,
+				<0 0xc6 0 IRQ_TYPE_NONE>,
+				<0 0xc7 0 IRQ_TYPE_NONE>,
+				<0 0xca 0 IRQ_TYPE_NONE>,
+				<0 0xcb 0 IRQ_TYPE_NONE>;
+		};
+
 		rtc@6000 {
 			compatible = "qcom,pm8941-rtc";
 			reg = <0x6000>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #13 lore raw

PATCH v3 13/18 arm64: dts: qcom: qcs404: Add scm firmware node

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add the scm firmware node to QCS404

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +7 -0

index df07c494c47b..373d514eb147 100644
@@ -62,6 +62,13 @@
 		};
 	};
 
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-qcs404", "qcom,scm";
+			#reset-cells = <1>;
+		};
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		/* We expect the bootloader to fill in the reg */

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #14 lore raw

PATCH v3 14/18 arm64: dts: qcom: qcs404: Add remoteproc nodes

In reply to Vinod Koul

From: Bjorn Andersson <[email protected]>

Add the TrustZone based remoteproc nodes and their glink edges for adsp, cdsp and wcss. Enable them for EVB common DTS.

Signed-off-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 +++++
 arch/arm64/boot/dts/qcom/qcs404.dtsi     | 93 ++++++++++++++++++++++++++++++++
 2 files changed, 105 insertions(+)

arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +12 -0

index cc5dfb319af8..d4182756980b 100644
@@ -21,6 +21,18 @@
 	};
 };
 
+&rproc_adsp {
+	status = "ok";
+};
+
+&rproc_cdsp {
+	status = "ok";
+};
+
+&rproc_wcss {
+	status = "ok";
+};
+
 &rpm_requests {
 	pms405-regulators {
 		compatible = "qcom,rpm-pms405-regulators";

arch/arm64/boot/dts/qcom/qcs404.dtsi +93 -0

99 lines not on this page · raw message

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #15 lore raw

PATCH v3 15/18 arm64: dts: qcom: qcs404: add prng-ee node

In reply to Vinod Koul

RNG hardware in QCS404 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for QCS404.

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +7 -0

index a9d6d3dd5945..125d9b9b5ffc 100644
@@ -253,6 +253,13 @@
 			reg = <0x00060000 0x6000>;
 		};
 
+		rng: rng@e3000 {
+			compatible = "qcom,prng-ee";
+			reg = <0x000e3000 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,qcs404-pinctrl";
 			reg = <0x01000000 0x200000>,

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #16 lore raw

PATCH v3 16/18 arm64: dts: qcom: qcs404: Add BAM DMA node

In reply to Vinod Koul

Add the BAM DMA instance found in BLSP1 node of the QCS404

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +12 -0

index 125d9b9b5ffc..f7ac3d0662b4 100644
@@ -323,6 +323,18 @@
 			status = "disabled";
 		};
 
+		blsp1_dma: dma@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x25000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,controlled-remotely = <1>;
+			qcom,ee = <0>;
+			status = "okay";
+		};
+
 		blsp1_uart2: serial@78b1000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x078b1000 0x200>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #17 lore raw

PATCH v3 17/18 arm64: dts: qcom: qcs404: Use BAM DMA for serial uart2

In reply to Vinod Koul

We can use BAM DAM for serial UART data transfers, so add it

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/arm64/boot/dts/qcom/qcs404.dtsi +2 -0

index f7ac3d0662b4..46a4608db214 100644
@@ -341,6 +341,8 @@
 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
+			dma-names = "rx", "tx";
 			status = "okay";
 		};

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:50 UTC #18 lore raw

PATCH v3 18/18 arm64: dts: qcom: pms405: Add pon and pwrkey nodes

In reply to Vinod Koul

PMS405 also features PON block, so add PON and PWRKEY nodes

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

arch/arm64/boot/dts/qcom/pms405.dtsi +16 -0

index 02b758cfd758..a1272a444e02 100644
@@ -2,6 +2,7 @@
 // Copyright (c) 2018, Linaro Limited
 
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/input/linux-event-codes.h>
 
 &spmi_bus {
 	pms405_0: pms405@0 {

@@ -26,6 +27,21 @@
 				<0 0xcb 0 IRQ_TYPE_NONE>;
 		};
 
+		pon@800 {
+			compatible = "qcom,pms405-pon";
+			reg = <0x0800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+		};
+
 		rtc@6000 {
 			compatible = "qcom,pm8941-rtc";
 			reg = <0x6000>;

Signature · 1 line

2.14.4

Vinod Koul

author

2018-11-08 17:57 UTC #19 lore raw

In reply to Vinod Koul

Quoted 9 lines · Vinod Koul

This series adds support for various nodes for QCS404-EVB.
Based on v4.20-rc1
Changes in v3:
- Make the DTS files sorted alphabetcially and by node addresses
- Add reviewed by from Bjorn
- Split out the DTS files for EVB 1000 and EVB 4000 boards and add common evb dts files for common part

Sorry I sent out the wrong branch :( will send updated one shortly, apologies for the noise

Signature · 1 line

~Vinod