Introduce CONFIG_FIT_EXTERNAL_OFFSET
Subsystems (9)
PATCH 1/15 Introduce CONFIG_FIT_EXTERNAL_OFFSET
Introduce CONFIG_FIT_EXTERNAL_OFFSET to give user a choice to choose where to put the external data.
Signed-off-by Peng Fan <[email protected]>
--- Kconfig | 6 ++++++ Makefile | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-)
Kconfig +6 -0
@@ -248,6 +248,12 @@ config FIT if FIT +config FIT_EXTERNAL_OFFSET + hex "Text Base" + default 0x0 + help + This specifics a data offset in fit image. + config FIT_ENABLE_SHA256_SUPPORT bool "Support SHA256 checksum of FIT image contents" default y
Makefile +1 -1
@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_mkfitimage = MKIMAGE $@ -cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ +cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_cat = CAT $@
Signature · 1 line
2.14.1
PATCH 2/15 imx8m: Enable CONFIG_SPL_FIT_IMAGE_TINY for iMX8M
From: Ye Li <[email protected]>
If we don't define CONFIG_SPL_FIT_IMAGE_TINY, when loading images from FIT, the SPL will record all loadables' info to u-boot's FDT. This causes problem when HAB is enabled, because FDT's content is modified before we authenticate it.
Signed-off-by Ye Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
--- common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+)
common/spl/Kconfig +1 -0
@@ -257,6 +257,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 + default y if ARCH_IMX8M help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight.
Signature · 1 line
2.14.1
PATCH 3/15 imx: cpu: add CHIP_REV_2_1 macro
In reply to Peng FanIntroduce CHIP_REV_2_1 macro.
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/include/asm/arch-imx/cpu.h | 1 + 1 file changed, 1 insertion(+)
arch/arm/include/asm/arch-imx/cpu.h +1 -0
@@ -41,6 +41,7 @@#define CHIP_REV_1_2 0x12#define CHIP_REV_1_5 0x15#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21#define CHIP_REV_2_5 0x25#define CHIP_REV_3_0 0x30
Signature · 1 line
2.14.1
PATCH 4/15 imx: introduce is_imx8mq helper
In reply to Peng FanIntroduce is_imx8mq header macro
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/include/asm/mach-imx/sys_proto.h | 1 + 1 file changed, 1 insertion(+)
arch/arm/include/asm/mach-imx/sys_proto.h +1 -0
@@ -42,6 +42,7 @@#define is_mx7ulp () (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8mq () (is_cpu_type(MXC_CPU_IMX8MQ))#define is_imx8qxp () (is_cpu_type(MXC_CPU_IMX8QXP))#ifdef CONFIG_MX6
Signature · 1 line
2.14.1
PATCH 5/15 imx: rename mx8m,MX8M to imx8m,IMX8M
In reply to Peng FanRename mx8m,MX8M to imx8m,IMX8M
Signed-off-by Peng Fan <[email protected]>
---
arch/arm/Kconfig | 4 ++--
arch/arm/Makefile | 4 ++--
arch/arm/include/asm/arch-imx/cpu.h | 4 ++--
arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h | 0
.../include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h | 4 ++--
arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h | 4 ++--
arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h | 4 ++--
.../include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h | 4 ++--
.../mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} | 4 ++--
.../include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h | 4 ++--
arch/arm/include/asm/mach-imx/iomux-v3.h | 2 +-
arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +++---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 +-
arch/arm/mach-imx/Makefile | 8 ++++----
arch/arm/mach-imx/cpu.c | 16 ++++++++--------
arch/arm/mach-imx/{mx8m => imx8m}/Kconfig | 6 +++---
arch/arm/mach-imx/{mx8m => imx8m}/Makefile | 0
arch/arm/mach-imx/{mx8m => imx8m}/clock.c | 4 ++--
arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c | 0
arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S | 0
arch/arm/mach-imx/{mx8m => imx8m}/soc.c | 0
arch/arm/mach-imx/imx_bootaux.c | 4 ++--
arch/arm/mach-imx/spl.c | 6 +++---
drivers/gpio/mxc_gpio.c | 18 +++++++++---------
drivers/misc/mxc_ocotp.c | 6 +++---
drivers/mmc/fsl_esdhc.c | 8 ++++----
drivers/net/fec_mxc.c | 2 +-
27 files changed, 62 insertions(+), 62 deletions(-)
rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h (100%)
rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h (65%)
rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h (98%)
rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h (63%)
rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h (99%)
rename arch/arm/include/asm/{arch-mx8m/mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} (99%)
rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h (82%)
rename arch/arm/mach-imx/{mx8m => imx8m}/Kconfig (57%)
rename arch/arm/mach-imx/{mx8m => imx8m}/Makefile (100%)
rename arch/arm/mach-imx/{mx8m => imx8m}/clock.c (99%)
rename arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c (100%)
rename arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S (100%)
rename arch/arm/mach-imx/{mx8m => imx8m}/soc.c (100%)arch/arm/Kconfig +2 -2
@@ -674,7 +674,7 @@ config ARCH_IMX8 select DM select OF_CONTROL -config ARCH_MX8M +config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 select DM
@@ -1426,7 +1426,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig" source "arch/arm/mach-imx/imx8/Kconfig" -source "arch/arm/mach-imx/mx8m/Kconfig" +source "arch/arm/mach-imx/imx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig"
arch/arm/Makefile +2 -2
@@ -102,11 +102,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif
arch/arm/include/asm/arch-imx/cpu.h +2 -2
@@ -24,7 +24,7 @@#define MXC_CPU_MX6QP 0x69#define MXC_CPU_MX7S 0x71/* dummy ID */ #define MXC_CPU_MX7D 0x72 -#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8MQ 0x82#define MXC_CPU_IMX8QXP_A0 0x90/* dummy ID */ #define MXC_CPU_IMX8QXP 0x92/* dummy ID */ #define MXC_CPU_MX7ULP 0xE1/* Temporally hard code */
@@ -32,7 +32,7 @@#define MXC_SOC_MX6 0x60#define MXC_SOC_MX7 0x70 -#define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8M 0x80#define MXC_SOC_IMX8 0x90/* dummy */ #define MXC_SOC_MX7ULP 0xE0/* dummy */
arch/arm/include/asm/arch-imx8m/clock.h renamed from arch/arm/include/asm/arch-mx8m/clock.h +0 -0
arch/arm/include/asm/arch-imx8m/crm_regs.h renamed from arch/arm/include/asm/arch-mx8m/crm_regs.h +2 -2
@@ -3,7 +3,7 @@* Copyright 2017 NXP */ -#ifndef _ASM_ARCH_MX8M_CRM_REGS_H -#define _ASM_ARCH_MX8M_CRM_REGS_H +#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H +#define _ASM_ARCH_IMX8M_CRM_REGS_H/* Dummy header, some imx-common code needs this file */ #endif
arch/arm/include/asm/arch-imx8m/ddr.h renamed from arch/arm/include/asm/arch-mx8m/ddr.h +2 -2
@@ -3,8 +3,8 @@* Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_DDR_H -#define __ASM_ARCH_MX8M_DDR_H +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H#define DDRC_DDR_SS_GPR0 0x3d000000#define DDRC_IPS_BASE_ADDR_0 0x3f400000
arch/arm/include/asm/arch-imx8m/gpio.h renamed from arch/arm/include/asm/arch-mx8m/gpio.h +2 -2
@@ -3,8 +3,8 @@* Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_GPIO_H -#define __ASM_ARCH_MX8M_GPIO_H +#ifndef __ASM_ARCH_IMX8M_GPIO_H +#define __ASM_ARCH_IMX8M_GPIO_H#include <asm/mach-imx/gpio.h>
arch/arm/include/asm/arch-imx8m/imx-regs.h renamed from arch/arm/include/asm/arch-mx8m/imx-regs.h +2 -2
@@ -3,8 +3,8 @@* Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_REGS_H__ -#define __ASM_ARCH_MX8M_REGS_H__ +#ifndef __ASM_ARCH_IMX8M_REGS_H__ +#define __ASM_ARCH_IMX8M_REGS_H__#include <asm/mach-imx/regs-lcdif.h>
arch/arm/include/asm/arch-imx8m/imx8mq_pins.h renamed from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h +2 -2
@@ -3,8 +3,8 @@* Copyright (C) 2017 NXP */ -#ifndef __ASM_ARCH_MX8MQ_PINS_H__ -#define __ASM_ARCH_MX8MQ_PINS_H__ +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ +#define __ASM_ARCH_IMX8MQ_PINS_H__#include <asm/mach-imx/iomux-v3.h>
arch/arm/include/asm/arch-imx8m/sys_proto.h renamed from arch/arm/include/asm/arch-mx8m/sys_proto.h +2 -2
@@ -3,8 +3,8 @@* Copyright (C) 2017 NXP */ -#ifndef __ARCH_MX8M_SYS_PROTO_H -#define __ARCH_MX8M_SYS_PROTO_H +#ifndef __ARCH_IMX8M_SYS_PROTO_H +#define __ARCH_NMX8M_SYS_PROTO_H#include <asm/mach-imx/sys_proto.h>
arch/arm/include/asm/mach-imx/iomux-v3.h +1 -1
@@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;#define IOMUX_CONFIG_LPSR 0x20#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M #define PAD_CTL_DSE0 (0x0 << 0)#define PAD_CTL_DSE1 (0x1 << 0)#define PAD_CTL_DSE2 (0x2 << 0)
arch/arm/include/asm/mach-imx/regs-lcdif.h +3 -3
@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {defined (CONFIG_MX6SL ) ||defined (CONFIG_MX6SLL ) || \defined (CONFIG_MX6UL ) ||defined (CONFIG_MX6ULL ) || \defined (CONFIG_MX7 ) ||defined (CONFIG_MX7ULP ) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */#endif mxs_reg_32 (hw_lcdif_transfer_count)/* 0x20/0x30 */
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {defined (CONFIG_MX6SL ) ||defined (CONFIG_MX6SLL ) || \defined (CONFIG_MX6UL ) ||defined (CONFIG_MX6ULL ) || \defined (CONFIG_MX7 ) ||defined (CONFIG_MX7ULP ) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */#endif mxs_reg_32 (hw_lcdif_lcdif_stat)/* 0x1d0/0x1b0 */
@@ -73,7 +73,7 @@ struct mxs_lcdif_regs {defined (CONFIG_MX6SL ) ||defined (CONFIG_MX6SLL ) || \defined (CONFIG_MX6UL ) ||defined (CONFIG_MX6ULL ) || \defined (CONFIG_MX7 ) ||defined (CONFIG_MX7ULP ) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf)
arch/arm/include/asm/mach-imx/sys_proto.h +1 -1
@@ -26,7 +26,7 @@#define is_mx6 () (is_soc_type(MXC_SOC_MX6))#define is_mx7 () (is_soc_type(MXC_SOC_MX7)) -#define is_mx8m () (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8m () (is_soc_type(MXC_SOC_IMX8M))#define is_imx8 () (is_soc_type(MXC_SOC_IMX8))#define is_mx6dqp () (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
arch/arm/mach-imx/Makefile +4 -4
@@ -5,11 +5,11 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc. -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) obj-y = iomux-v3.o endif -ifeq ($(SOC),$(filter $(SOC),mx8m)) +ifeq ($(SOC),$(filter $(SOC),imx8m)) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o
@@ -22,7 +22,7 @@ obj-y += cpu.o speed.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m)) obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif
@@ -153,5 +153,5 @@ obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ -obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/
arch/arm/mach-imx/cpu.c +8 -8
@@ -62,7 +62,7 @@ static char *get_reset_cause(void)return "WDOG4" ;case 0x00200 :return "TEMPSENSE" ; -#elif defined(CONFIG_MX8M ) +#elif defined(CONFIG_IMX8M )case 0x00100 :return "WDOG2" ;case 0x00200 :
@@ -142,8 +142,8 @@ unsigned imx_ddr_size(void)const char *get_imx_type (u32 imxtype) {switch (imxtype) { -case MXC_CPU_MX8MQ : -return "8MQ" ;/* Quad-core version of the mx8m */ +case MXC_CPU_IMX8MQ : +return "8MQ" ;/* Quad-core version of the imx8m */ case MXC_CPU_MX7S :return "7S" ;/* Single-core version of the mx7 */ case MXC_CPU_MX7D :
@@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis) }#endif -#if !(defined(CONFIG_MX7 ) || defined(CONFIG_MX8M )) +#if !(defined(CONFIG_MX7 ) || defined(CONFIG_IMX8M ))u32 get_ahb_clk (void ) {struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR ;
@@ -300,7 +300,7 @@ void arch_preboot_os(void)#endif } -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M void set_chipselect_size (int const cs_size) {unsigned int reg;
@@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size) }#endif -#if defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) +#if defined(CONFIG_MX7 ) || defined(CONFIG_IMX8M )/* * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) * defines a 2-bit SPEED_GRADING
@@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) }#endif -#if defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) +#if defined(CONFIG_MX7 ) || defined(CONFIG_IMX8M )enum boot_device get_boot_device (void ) { struct bootrom_sw_info **p =
@@ -438,7 +438,7 @@ enum boot_device get_boot_device(void)case BOOT_TYPE_SPINOR : boot_dev =SPI_NOR_BOOT ;break ; -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M case BOOT_TYPE_USB : boot_dev =USB_BOOT ;break ;
arch/arm/mach-imx/imx8m/Kconfig renamed from arch/arm/mach-imx/mx8m/Kconfig +3 -3
@@ -1,10 +1,10 @@ -if ARCH_MX8M +if ARCH_IMX8M -config MX8M +config IMX8M bool select ROM_UNIFIED_SECTIONS config SYS_SOC - default "mx8m" + default "imx8m" endif
arch/arm/mach-imx/imx8m/Makefile renamed from arch/arm/mach-imx/mx8m/Makefile +0 -0
arch/arm/mach-imx/imx8m/clock.c renamed from arch/arm/mach-imx/mx8m/clock.c +2 -2
@@ -730,7 +730,7 @@ int clock_init(void)* Dump some clockes. */ #ifndef CONFIG_SPL_BUILD -int do_mx8m_showclocks (cmd_tbl_t *cmdtp,int flag,int argc, +int do_imx8m_showclocks (cmd_tbl_t *cmdtp,int flag,int argc,char *const argv[]) {u32 freq;
@@ -785,7 +785,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, }U_BOOT_CMD ( - clocks,CONFIG_SYS_MAXARGS ,1 , do_mx8m_showclocks, + clocks,CONFIG_SYS_MAXARGS ,1 , do_imx8m_showclocks,"display clocks" ,"" );
arch/arm/mach-imx/imx8m/clock_slice.c renamed from arch/arm/mach-imx/mx8m/clock_slice.c +0 -0
arch/arm/mach-imx/imx8m/lowlevel_init.S renamed from arch/arm/mach-imx/mx8m/lowlevel_init.S +0 -0
arch/arm/mach-imx/imx8m/soc.c renamed from arch/arm/mach-imx/mx8m/soc.c +0 -0
arch/arm/mach-imx/imx_bootaux.c +2 -2
@@ -25,7 +25,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)writel (pc,M4_BOOTROM_BASE_ADDR +4 );/* Enable M4 */ -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M call_imx_sip (IMX_SIP_SRC ,IMX_SIP_SRC_M4_START ,0 ,0 );#else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)int arch_auxiliary_core_check_up (u32 core_id) { -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M return call_imx_sip (IMX_SIP_SRC ,IMX_SIP_SRC_M4_STARTED ,0 ,0 );#else unsigned int val;
arch/arm/mach-imx/spl.c +3 -3
@@ -96,8 +96,8 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) -/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) +/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device (void ) {#if defined(CONFIG_MX7 )
@@ -143,7 +143,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } } -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ +#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M */ #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup (struct usb_device_descriptor *dev,const char *name)
drivers/gpio/mxc_gpio.c +9 -9
@@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR,#if defined(CONFIG_MX25 ) || defined(CONFIG_MX27 ) || defined(CONFIG_MX51 ) || \ defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || \ - defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) || \ + defined(CONFIG_MX7 ) || defined(CONFIG_IMX8M ) || \ defined(CONFIG_ARCH_IMX8 ) [3] = GPIO4_BASE_ADDR,#endif #if defined(CONFIG_MX27 ) || defined(CONFIG_MX53 ) || defined(CONFIG_MX6 ) || \ - defined(CONFIG_MX7 ) || defined(CONFIG_MX8M ) || \ + defined(CONFIG_MX7 ) || defined(CONFIG_IMX8M ) || \ defined(CONFIG_ARCH_IMX8 ) [4] = GPIO5_BASE_ADDR, -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M)) [5] = GPIO6_BASE_ADDR,#endif #endif
@@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif
@@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif
drivers/misc/mxc_ocotp.c +3 -3
@@ -34,7 +34,7 @@#define BM_OUT_STATUS_DED 0x00000400#define BM_OUT_STATUS_LOCKED 0x00000800#define BM_OUT_STATUS_PROGFAIL 0x00001000 -#elif defined(CONFIG_MX8M ) +#elif defined(CONFIG_IMX8M )#define BM_CTRL_ADDR 0x000000ff#else #define BM_CTRL_ADDR 0x0000007f
@@ -80,7 +80,7 @@#elif defined(CONFIG_MX7ULP )#define FUSE_BANK_SIZE 0x80#define FUSE_BANKS 31 -#elif defined(CONFIG_MX8M ) +#elif defined(CONFIG_IMX8M )#define FUSE_BANK_SIZE 0x40#define FUSE_BANKS 64#else
@@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,u32 wr_unlock = write ?BV_CTRL_WR_UNLOCK_KEY :0 ;#ifdef CONFIG_MX7 u32 addr = bank; -#elif definedCONFIG_MX8M +#elif definedCONFIG_IMX8M u32 addr = bank <<2 | word;#else u32 addr;
drivers/mmc/fsl_esdhc.c +4 -4
@@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,int timeout;struct fsl_esdhc *regs = priv->esdhc_regs;#if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_IMX8M )dma_addr_t addr;#endif uint wml_value;
@@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,esdhc_clrsetbits32 (®s->wml,WML_RD_WML_MASK , wml_value);#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_IMX8M ) addr =virt_to_phys ((void *)(data->dest));if (upper_32_bits (addr))printf ("Error found for upper 32 bits\n" );
@@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, wml_value << 16);#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_IMX8M ) addr =virt_to_phys ((void *)(data->src));if (upper_32_bits (addr))printf ("Error found for upper 32 bits\n" );
@@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_rangeunsigned size =roundup (ARCH_DMA_MINALIGN , data->blocks*data->blocksize);#if defined(CONFIG_FSL_LAYERSCAPE ) || defined(CONFIG_S32V234 ) || \ - defined(CONFIG_IMX8 ) || defined(CONFIG_MX8M ) + defined(CONFIG_IMX8 ) || defined(CONFIG_IMX8M )dma_addr_t addr; addr =virt_to_phys ((void *)(data->dest));
drivers/net/fec_mxc.c +1 -1
@@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)writel (0x00000000 , &fec->eth->gaddr2);/* Do not access reserved register */ -if (!is_mx6ul () && !is_mx6ull () && !is_mx8m ()) { +if (!is_mx6ul () && !is_mx6ull () && !is_imx8m ()) {/* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr +0xfc ; i +=4 )writel (0 , i);
Signature · 1 line
2.14.1
PATCH 6/15 imx: spl: add MMC BOOT Device for i.MX8M
In reply to Peng FanAdd MMC BOOT Device for i.MX8M
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/mach-imx/spl.c | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/mach-imx/spl.c +9 -0
@@ -126,6 +126,7 @@ u32 spl_boot_device(void)enum boot_device boot_device_spl =get_boot_device ();switch (boot_device_spl) { +#if defined(CONFIG_MX7 )case SD1_BOOT :case MMC1_BOOT :case SD2_BOOT :
@@ -133,6 +134,14 @@ u32 spl_boot_device(void)case SD3_BOOT :case MMC3_BOOT :return BOOT_DEVICE_MMC1 ; +#elif defined(CONFIG_IMX8M ) +case SD1_BOOT : +case MMC1_BOOT : +return BOOT_DEVICE_MMC1 ; +case SD2_BOOT : +case MMC2_BOOT : +return BOOT_DEVICE_MMC2 ; +#endif case NAND_BOOT :return BOOT_DEVICE_NAND ;case SPI_NOR_BOOT :
Signature · 1 line
2.14.1
PATCH 6/15 imx: spl: add MMC BOOT Device for i.MX8M
Quoted 12 lines · Peng Fan
Add MMC BOOT Device for i.MX8M
Signed-off-by Peng Fan <[email protected]>--- arch/arm/mach-imx/spl.c | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm/mach-imx/spl.c +0
-0
arch/arm/mach-imx/spl.c u32 spl_boot_device(void) · line 129
Quoted 4 lines
arch/arm/mach-imx/spl.c +1
-0@@ -126,6 +126,7 @@ u32 spl_boot_device(void)enum boot_device boot_device_spl =get_boot_device ();switch (boot_device_spl) { +#if defined(CONFIG_MX7 )
This looks weird. Can imx6 no longer boot from SD1_BOOT/MMC1_BOOT ?
Quoted 19 lines
arch/arm/mach-imx/spl.c +8
-0case SD1_BOOT :case MMC1_BOOT :case SD2_BOOT :@@ -133,6 +134,14 @@ u32 spl_boot_device(void)case SD3_BOOT :case MMC3_BOOT :return BOOT_DEVICE_MMC1 ; +#elif defined(CONFIG_IMX8M ) +case SD1_BOOT : +case MMC1_BOOT : +return BOOT_DEVICE_MMC1 ; +case SD2_BOOT : +case MMC2_BOOT : +return BOOT_DEVICE_MMC2 ; +#endif case NAND_BOOT :return BOOT_DEVICE_NAND ;case SPI_NOR_BOOT :
PATCH 6/15 imx: spl: add MMC BOOT Device for i.MX8M
Quoted 15 lines · Troy Kisky
Quoted 14 lines · Peng Fan
Add MMC BOOT Device for i.MX8M
Signed-off-by Peng Fan <[email protected]>--- arch/arm/mach-imx/spl.c | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm/mach-imx/spl.c +0
-0@@ -126,6 +126,7 @@ u32 spl_boot_device(void)enum boot_device boot_device_spl =get_boot_device ();
Quoted 5 lines
arch/arm/mach-imx/spl.c u32 spl_boot_device(void) · line 129
Quoted 2 lines
arch/arm/mach-imx/spl.c +1
-0switch (boot_device_spl) { +#if defined(CONFIG_MX7 )This looks weird. Can imx6 no longer boot from SD1_BOOT/MMC1_BOOT ?
Sorry, only MX7 and MX8 are in this block of code.
The endif confused me.
|#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
PATCH 7/15 imx: imx8m: clock refactor dram pll part
In reply to Peng FanRefactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/include/asm/arch-imx8m/clock.h | 44 +++++++++++ arch/arm/mach-imx/imx8m/clock.c | 134 ++++++++++++++++++++++++++------ 2 files changed, 154 insertions(+), 24 deletions(-)
arch/arm/include/asm/arch-imx8m/clock.h +44 -0
@@ -631,6 +631,50 @@ enum frac_pll_out_val { FRAC_PLL_OUT_1600M, }; +enum sscg_pll_out_val { +SSCG_PLL_OUT_400M , +SSCG_PLL_OUT_600M , +SSCG_PLL_OUT_800M , +}; + +enum dram_pll_out_val { +DRAM_PLL_OUT_100M , +DRAM_PLL_OUT_167M , +DRAM_PLL_OUT_266M , +DRAM_PLL_OUT_667M , +DRAM_PLL_OUT_400M , +DRAM_PLL_OUT_600M , +DRAM_PLL_OUT_700M , +DRAM_PLL_OUT_750M , +DRAM_PLL_OUT_800M , +}; + +enum dram_bypassclk_val { +DRAM_BYPASSCLK_100M , +DRAM_BYPASSCLK_250M , +DRAM_BYPASSCLK_400M , +}; + +#define DRAM_BYPASS_ROOT_CONFIG (_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { +enum dram_bypassclk_val clk; +int alt_root_sel; +enum root_pre_div alt_pre_div; +int apb_root_sel; +enum root_pre_div apb_pre_div; +}; + +void dram_pll_init (enum dram_pll_out_val pll_val); +void dram_enable_bypass (enum dram_bypassclk_val clk_val); +void dram_disable_bypass (void );u32 imx_get_fecclk (void );u32 imx_get_uartclk (void );int clock_init (void );
arch/arm/mach-imx/imx8m/clock.c +110 -24
151 lines not on this page · raw message
Signature · 1 line
2.14.1
PATCH 7/15 imx: imx8m: clock refactor dram pll part
Quoted 14 lines · Peng Fan
Refactor
dram_pll_initto accept args to configure different pll freq. Introducedram_enable_bypassanddram_disable_bypassSigned-off-by Peng Fan <[email protected]>--- arch/arm/include/asm/arch-imx8m/clock.h | 44 +++++++++++ arch/arm/mach-imx/imx8m/clock.c | 134 ++++++++++++++++++++++++++------ 2 files changed, 154 insertions(+), 24 deletions(-)arch/arm/include/asm/arch-imx8m/clock.h +0
-0
arch/arm/include/asm/arch-imx8m/clock.h enum frac_pll_out_val { · line 639
Quoted 9 lines
arch/arm/include/asm/arch-imx8m/clock.h +6
-0@@ -631,6 +631,50 @@ enum frac_pll_out_val { FRAC_PLL_OUT_1600M, }; +enum sscg_pll_out_val { +SSCG_PLL_OUT_400M , +SSCG_PLL_OUT_600M , +SSCG_PLL_OUT_800M , +}; +
Can we just pass frequencies we want instead of this enum
arch/arm/include/asm/arch-imx8m/clock.h enum frac_pll_out_val { · line 650
Quoted 11 lines
arch/arm/include/asm/arch-imx8m/clock.h +11
-0+enum dram_pll_out_val { +DRAM_PLL_OUT_100M , +DRAM_PLL_OUT_167M , +DRAM_PLL_OUT_266M , +DRAM_PLL_OUT_667M , +DRAM_PLL_OUT_400M , +DRAM_PLL_OUT_600M , +DRAM_PLL_OUT_700M , +DRAM_PLL_OUT_750M , +DRAM_PLL_OUT_800M , +};
Ditto
arch/arm/include/asm/arch-imx8m/clock.h enum frac_pll_out_val { · line 657
Quoted 7 lines
arch/arm/include/asm/arch-imx8m/clock.h +7
-0+ +enum dram_bypassclk_val { +DRAM_BYPASSCLK_100M , +DRAM_BYPASSCLK_250M , +DRAM_BYPASSCLK_400M , +}; +
Ditto
Quoted 180 lines
arch/arm/include/asm/arch-imx8m/clock.h +20
-0+#define DRAM_BYPASS_ROOT_CONFIG (_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { +enum dram_bypassclk_val clk; +int alt_root_sel; +enum root_pre_div alt_pre_div; +int apb_root_sel; +enum root_pre_div apb_pre_div; +}; + +void dram_pll_init (enum dram_pll_out_val pll_val); +void dram_enable_bypass (enum dram_bypassclk_val clk_val); +void dram_disable_bypass (void );u32 imx_get_fecclk (void );u32 imx_get_uartclk (void );int clock_init (void );arch/arm/mach-imx/imx8m/clock.c +110
-24@@ -525,41 +525,127 @@ u32 imx_get_fecclk(void)return get_root_clk (ENET_AXI_CLK_ROOT ); } -#ifdef CONFIG_SPL_BUILD -void dram_pll_init (void ) +static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { +DRAM_BYPASS_ROOT_CONFIG (DRAM_BYPASSCLK_100M ,2 ,CLK_ROOT_PRE_DIV1 ,2 , +CLK_ROOT_PRE_DIV2 ), +DRAM_BYPASS_ROOT_CONFIG (DRAM_BYPASSCLK_250M ,3 ,CLK_ROOT_PRE_DIV2 ,2 , +CLK_ROOT_PRE_DIV2 ), +DRAM_BYPASS_ROOT_CONFIG (DRAM_BYPASSCLK_400M ,1 ,CLK_ROOT_PRE_DIV2 ,3 , +CLK_ROOT_PRE_DIV2 ), +}; + +void dram_enable_bypass (enum dram_bypassclk_val clk_val) { -struct src *src = (struct src *)SRC_BASE_ADDR ; -void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; -u32 pwdn_mask =0 , pll_clke =0 , bypass1 =0 , bypass2 =0 ; -u32 val; -int ret; +int i; +struct dram_bypass_clk_setting *config; -setbits_le32 (GPC_BASE_ADDR +0xEC ,BIT (7 )); -setbits_le32 (GPC_BASE_ADDR +0xF8 ,BIT (5 )); +for (i =0 ; i <ARRAY_SIZE (imx8mq_dram_bypass_tbl); i++) { +if (clk_val == imx8mq_dram_bypass_tbl[i].clk) +break ; + } + +if (i ==ARRAY_SIZE (imx8mq_dram_bypass_tbl)) { +printf ("No matched freq table %u\n" , clk_val); +return ; + } - pwdn_mask =SSCG_PLL_PD_MASK ; - pll_clke =SSCG_PLL_DRAM_PLL_CLKE_MASK ; - bypass1 =SSCG_PLL_BYPASS1_MASK ; - bypass2 =SSCG_PLL_BYPASS2_MASK ; + config = &imx8mq_dram_bypass_tbl[i]; -/* Enable DDR1 and DDR2 domain */ -writel (SRC_DDR1_ENABLE_MASK , &src->ddr1_rcr); -writel (SRC_DDR1_ENABLE_MASK , &src->ddr2_rcr); +clock_set_target_val (DRAM_ALT_CLK_ROOT ,CLK_ROOT_ON | +CLK_ROOT_SOURCE_SEL (config->alt_root_sel) | +CLK_ROOT_PRE_DIV (config->alt_pre_div)); +clock_set_target_val (DRAM_APB_CLK_ROOT ,CLK_ROOT_ON | +CLK_ROOT_SOURCE_SEL (config->apb_root_sel) | +CLK_ROOT_PRE_DIV (config->apb_pre_div)); +clock_set_target_val (DRAM_SEL_CFG ,CLK_ROOT_ON | +CLK_ROOT_SOURCE_SEL (1 )); +} + +void dram_disable_bypass (void ) +{ +clock_set_target_val (DRAM_SEL_CFG ,CLK_ROOT_ON | +CLK_ROOT_SOURCE_SEL (0 )); +clock_set_target_val (DRAM_APB_CLK_ROOT ,CLK_ROOT_ON | +CLK_ROOT_SOURCE_SEL (4 ) | +CLK_ROOT_PRE_DIV (CLK_ROOT_PRE_DIV5 )); +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init (enum dram_pll_out_val pll_val) +{ +u32 val; +void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; +void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; + +/* Bypass */ +setbits_le32 (pll_control_reg,SSCG_PLL_BYPASS1_MASK ); +setbits_le32 (pll_control_reg,SSCG_PLL_BYPASS2_MASK ); + +switch (pll_val) { +case DRAM_PLL_OUT_800M : + val =readl (pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | +SSCG_PLL_FEEDBACK_DIV_F2_MASK | +SSCG_PLL_FEEDBACK_DIV_F1_MASK | +SSCG_PLL_REF_DIVR2_MASK ); + val |=SSCG_PLL_OUTPUT_DIV_VAL (0 ); + val |=SSCG_PLL_FEEDBACK_DIV_F2_VAL (11 ); + val |=SSCG_PLL_FEEDBACK_DIV_F1_VAL (39 ); + val |=SSCG_PLL_REF_DIVR2_VAL (29 ); +writel (val, pll_cfg_reg2); +break ; +case DRAM_PLL_OUT_600M : + val =readl (pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | +SSCG_PLL_FEEDBACK_DIV_F2_MASK | +SSCG_PLL_FEEDBACK_DIV_F1_MASK | +SSCG_PLL_REF_DIVR2_MASK ); + val |=SSCG_PLL_OUTPUT_DIV_VAL (1 ); + val |=SSCG_PLL_FEEDBACK_DIV_F2_VAL (17 ); + val |=SSCG_PLL_FEEDBACK_DIV_F1_VAL (39 ); + val |=SSCG_PLL_REF_DIVR2_VAL (29 ); +writel (val, pll_cfg_reg2); +break ; +case DRAM_PLL_OUT_400M : + val =readl (pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | +SSCG_PLL_FEEDBACK_DIV_F2_MASK | +SSCG_PLL_FEEDBACK_DIV_F1_MASK | +SSCG_PLL_REF_DIVR2_MASK ); + val |=SSCG_PLL_OUTPUT_DIV_VAL (1 ); + val |=SSCG_PLL_FEEDBACK_DIV_F2_VAL (11 ); + val |=SSCG_PLL_FEEDBACK_DIV_F1_VAL (39 ); + val |=SSCG_PLL_REF_DIVR2_VAL (29 ); +writel (val, pll_cfg_reg2); +break ; +case DRAM_PLL_OUT_167M : + val =readl (pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | +SSCG_PLL_FEEDBACK_DIV_F2_MASK | +SSCG_PLL_FEEDBACK_DIV_F1_MASK | +SSCG_PLL_REF_DIVR2_MASK ); + val |=SSCG_PLL_OUTPUT_DIV_VAL (3 ); + val |=SSCG_PLL_FEEDBACK_DIV_F2_VAL (8 ); + val |=SSCG_PLL_FEEDBACK_DIV_F1_VAL (45 ); + val |=SSCG_PLL_REF_DIVR2_VAL (30 ); +writel (val, pll_cfg_reg2); +break ; +default : +break ; + }/* Clear power down bit */ -clrbits_le32 (pll_control_reg, pwdn_mask); +clrbits_le32 (pll_control_reg,SSCG_PLL_PD_MASK );/* Eanble ARM_PLL/SYS_PLL */ -setbits_le32 (pll_control_reg, pll_clke); +setbits_le32 (pll_control_reg,SSCG_PLL_DRAM_PLL_CLKE_MASK );/* Clear bypass */ -clrbits_le32 (pll_control_reg, bypass1); +clrbits_le32 (pll_control_reg,SSCG_PLL_BYPASS1_MASK );__udelay (100 ); -clrbits_le32 (pll_control_reg, bypass2); +clrbits_le32 (pll_control_reg,SSCG_PLL_BYPASS2_MASK );/* Wait lock */ - ret =readl_poll_timeout (pll_control_reg, val, - val &SSCG_PLL_LOCK_MASK ,1 ); -if (ret) -printf ("%s timeout\n" , __func__); +while (!(readl (pll_control_reg) &SSCG_PLL_LOCK_MASK )) + ; }int frac_pll_init (u32 pll,enum frac_pll_out_val val)
PATCH 8/15 tools: add i.MX8M image support
In reply to Peng Fani.MX8M bootable image type is like i.MX6/7, but there is signed HDMI firmware image in front of A53 bootable image, which is also has an IVT header.
Here we also include fit image to generate a bootable image.
Signed-off-by Peng Fan <[email protected]>
--- common/image.c | 1 + include/image.h | 1 + include/imximage.h | 17 +- tools/Makefile | 1 + tools/imagetool.h | 1 + tools/imx8mimage.c | 623 +++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/mkimage.c | 7 + 7 files changed, 650 insertions(+), 1 deletion(-) create mode 100644 tools/imx8mimage.c
common/image.c +1 -0
@@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",}, + { IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",}, { IH_TYPE_INVALID, "invalid", "Invalid Image", }, { IH_TYPE_MULTI, "multi", "Multi-File Image", }, { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",},
include/image.h +1 -0
@@ -252,6 +252,7 @@ enum {IH_TYPE_KWBIMAGE ,/* Kirkwood Boot Image */ IH_TYPE_IMXIMAGE ,/* Freescale IMXBoot Image */ IH_TYPE_IMX8IMAGE ,/* Freescale IMX8Boot Image */ +IH_TYPE_IMX8MIMAGE ,/* Freescale IMX8MBoot Image */ IH_TYPE_UBLIMAGE ,/* Davinci UBL Image */ IH_TYPE_OMAPIMAGE ,/* TI OMAP Config Header Image */ IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */
include/imximage.h +16 -1
@@ -33,6 +33,7 @@#define FLASH_OFFSET_NOR 0x1000#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD#define FLASH_OFFSET_QSPI 0x1000 +#define FLASH_OFFSET_FLEXSPI 0x1000/* Initial Load Region Size */ #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
@@ -48,6 +49,7 @@/* Command tags and parameters */ #define IVT_HEADER_TAG 0xD1#define IVT_VERSION 0x40 +#define IVT_VERSION_V3 0x41#define DCD_HEADER_TAG 0xD2#define DCD_VERSION 0x40#define DCD_WRITE_DATA_COMMAND_TAG 0xCC
@@ -71,6 +73,12 @@ enum imximage_cmd {CMD_CHECK_BITS_CLR ,CMD_CSF ,CMD_PLUGIN , +/* Follwoing on i.MX8MQ/MM */ +CMD_FIT , +CMD_SIGNED_HDMI , +CMD_LOADER , +CMD_SECOND_LOADER , + CMD_DDR_FW, }; enum imximage_fld_types {
@@ -84,7 +92,8 @@ enum imximage_fld_types {enum imximage_version {IMXIMAGE_VER_INVALID =-1 ,IMXIMAGE_V1 =1 , -IMXIMAGE_V2 +IMXIMAGE_V2 , +IMXIMAGE_V3 }; typedef struct {
@@ -177,6 +186,12 @@ typedef struct { } data; } imx_header_v2_t; +typedef struct { +flash_header_v2_t fhdr; +boot_data_t boot_data; +uint32_t padding[5 ]; +}imx_header_v3_t ; +/* The header must be aligned to 4k on MX53 for NAND boot */ struct imx_header { union {
tools/Makefile +1 -0
@@ -94,6 +94,7 @@ dumpimage-mkimage-objs := aisimage.o \ imagetool.o \ imximage.o \ imx8image.o \ + imx8mimage.o \ kwbimage.o \ lib/md5.o \ lpc32xximage.o \
tools/imagetool.h +1 -0
@@ -233,6 +233,7 @@ time_t imagetool_get_source_date(void pbl_load_uboot (int fd,struct image_tool_params *mparams);int zynqmpbif_copy_image (int fd,struct image_tool_params *mparams);int imx8image_copy_image (int fd,struct image_tool_params *mparams); +int imx8mimage_copy_image (int fd,struct image_tool_params *mparams);#define ___cat (a, b) a ## b#define __cat (a, b) ___cat(a, b)
tools/imx8mimage.c new file +623 -0
623 lines not on this page · raw message
tools/mkimage.c +7 -0
@@ -530,6 +530,13 @@ int main(int argc, char **argv) ret =imx8image_copy_image (ifd, ¶ms);if (ret)return ret; + }else if (params.type ==IH_TYPE_IMX8MIMAGE ) { +/* i.MX8M has special Image format */ +int ret; + + ret =imx8mimage_copy_image (ifd, ¶ms); +if (ret) +return ret; }else {copy_file (ifd, params.datafile, pad_len); }
Signature · 1 line
2.14.1
PATCH 9/15 imx: imx8m: introduce script to generate fit image
In reply to Peng FanIntroduce script to generate fit image for i.MX8M
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/mach-imx/mkimage_fit_atf.sh | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100755 arch/arm/mach-imx/mkimage_fit_atf.sh
arch/arm/mach-imx/mkimage_fit_atf.sh new file +137 -0
@@ -0,0 +1,137 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to generate FIT image source for i.MX8MQ boards with +# ARM Trusted Firmware and multiple device trees (given on the command line) +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" +[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000" +[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000" + +if [ ! -f $BL31 ]; then + echo "ERROR: BL31 file $BL31 NOT found" >&2 + exit 0 +else + echo "bl31.bin size: " >&2 + ls -lct bl31.bin | awk '{print $5}' >&2 +fi + +BL32="tee.bin" + +if [ ! -f $BL32 ]; then + BL32=/dev/null +else + echo "Building with TEE support, make sure your bl31 is compiled with spd. If you do not want tee, please delete tee.bin" >&2 + echo "tee.bin size: " >&2 + ls -lct tee.bin | awk '{print $5}' >&2 +fi + +BL33="u-boot-nodtb.bin" + +if [ ! -f $BL33 ]; then + echo "ERROR: $BL33 file NOT found" >&2 + exit 0 +else + echo "u-boot-nodtb.bin size: " >&2 + ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2 +fi + +for dtname in $* +do + echo "$dtname size: " >&2 + ls -lct $dtname | awk '{print $5}' >&2 +done + + +cat << __HEADER_EOF +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("$BL33"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x40200000>; + }; + atf at 1 { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$ATF_LOAD_ADDR>; + entry = <$ATF_LOAD_ADDR>; + }; +__HEADER_EOF + +if [ -f $BL32 ]; then +cat << __HEADER_EOF + tee@1 { + description = "TEE firmware"; + data = /incbin/("$BL32"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$TEE_LOAD_ADDR>; + entry = <$TEE_LOAD_ADDR>; + }; +__HEADER_EOF +fi + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config at 1"; + +__CONF_HEADER_EOF + +cnt=1 +for dtname in $* +do +if [ -f $BL32 ]; then +cat << __CONF_SECTION_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot at 1"; + loadables = "atf at 1", "tee at 1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION_EOF +else +cat << __CONF_SECTION1_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot at 1"; + loadables = "atf@1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION1_EOF +fi +cnt=$((cnt+1)) +done + +cat << __ITS_EOF + }; +}; +__ITS_EOF
Signature · 1 line
2.14.1
PATCH 9/15 imx: imx8m: introduce script to generate fit image
Quoted 22 lines · Peng Fan
Introduce script to generate fit image for i.MX8M
Signed-off-by Peng Fan <[email protected]>--- arch/arm/mach-imx/mkimage_fit_atf.sh | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100755 arch/arm/mach-imx/mkimage_fit_atf.sharch/arm/mach-imx/mkimage_fit_atf.sh new file +8
-0@@ -0,0 +1,137 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to generate FIT image source for i.MX8MQ boards with +# ARM Trusted Firmware and multiple device trees (given on the command line) +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] +
arch/arm/mach-imx/mkimage_fit_atf.sh line 18
Quoted 10 lines
arch/arm/mach-imx/mkimage_fit_atf.sh new file +10
-0+[ -z "$BL31" ] && BL31="bl31.bin" +[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000" +[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000" + +if [ ! -f $BL31 ]; then + echo "ERROR: BL31 file $BL31 NOT found" >&2 + exit 0 +else + echo "bl31.bin size: " >&2 + ls -lct bl31.bin | awk '{print $5}' >&2
s/bl31.bin/$BL31/
Quoted 120 lines
arch/arm/mach-imx/mkimage_fit_atf.sh new file +119
-0+fi + +BL32="tee.bin" + +if [ ! -f $BL32 ]; then + BL32=/dev/null +else + echo "Building with TEE support, make sure your bl31 is compiled with spd. If you do not want tee, please delete tee.bin" >&2 + echo "tee.bin size: " >&2 + ls -lct tee.bin | awk '{print $5}' >&2 +fi + +BL33="u-boot-nodtb.bin" + +if [ ! -f $BL33 ]; then + echo "ERROR: $BL33 file NOT found" >&2 + exit 0 +else + echo "u-boot-nodtb.bin size: " >&2 + ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2 +fi + +for dtname in $* +do + echo "$dtname size: " >&2 + ls -lct $dtname | awk '{print $5}' >&2 +done + + +cat << __HEADER_EOF +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + + images { + uboot at 1 { + description = "U-Boot (64-bit)"; + data = /incbin/("$BL33"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x40200000>; + }; + atf at 1 { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$ATF_LOAD_ADDR>; + entry = <$ATF_LOAD_ADDR>; + }; +__HEADER_EOF + +if [ -f $BL32 ]; then +cat << __HEADER_EOF + tee at 1 { + description = "TEE firmware"; + data = /incbin/("$BL32"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$TEE_LOAD_ADDR>; + entry = <$TEE_LOAD_ADDR>; + }; +__HEADER_EOF +fi + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config at 1"; + +__CONF_HEADER_EOF + +cnt=1 +for dtname in $* +do +if [ -f $BL32 ]; then +cat << __CONF_SECTION_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot at 1"; + loadables = "atf at 1", "tee at 1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION_EOF +else +cat << __CONF_SECTION1_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot at 1"; + loadables = "atf at 1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION1_EOF +fi +cnt=$((cnt+1)) +done + +cat << __ITS_EOF + }; +}; +__ITS_EOF
PATCH 10/15 imx: imx8m: introduce imximage cfg file
In reply to Peng Fanimximage.cfg will be used to generate the flash.bin
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/mach-imx/imx8m/imximage.cfg | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/arm/mach-imx/imx8m/imximage.cfg
arch/arm/mach-imx/imx8m/imximage.cfg new file +17 -0
@@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +SIGNED_HDMI signed_hdmi_imx8m.bin +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin
Signature · 1 line
2.14.1
PATCH 11/15 imx: imx8mq: build flash.bin
In reply to Peng FanBuild flash.bin for i.MX8MQ, it will include signed hdmi firmware, spl, ddr firmware, fit image(bl31.bin, u-boot-nodtb.bin, dtb). Burn it to 33KB offset of SD card.
Signed-off-by Peng Fan <[email protected]>
fix flash
Signed-off-by Peng Fan <[email protected]>
--- Makefile | 3 +++ arch/arm/mach-imx/Makefile | 31 +++++++++++++++++++++++++++++++ tools/imx8m_image.sh | 30 ++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100755 tools/imx8m_image.sh
Makefile +3 -0
@@ -1169,6 +1169,9 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE SPL: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE + $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ + u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
arch/arm/mach-imx/Makefile +31 -0
@@ -90,6 +90,10 @@ ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) +else ifeq ($(CONFIG_ARCH_IMX8M), y) +IMAGE_TYPE := imx8mimage +IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh +DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi) else IMAGE_TYPE := imximage DEPFILE_EXISTS := 0
@@ -113,6 +117,32 @@ ifeq ($(DEPFILE_EXISTS),0) endif endif +ifdef CONFIG_ARM64 +ifeq ($(CONFIG_ARCH_IMX8M), y) +SPL: + +MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \ + -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) +flash.bin: MKIMAGEOUTPUT = flash.log + +spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE +ifeq ($(DEPFILE_EXISTS),0) + @objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $(srctree)/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin + @objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $(srctree)/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin + @objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $(srctree)/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin + @cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin + @cat lpddr4_pmu_train_2d_imem_pad.bin lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin + @cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin + @rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin +endif + +flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE +ifeq ($(DEPFILE_EXISTS),0) + $(call if_changed,mkimage) +endif +endif + +else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) SPL: MKIMAGEOUTPUT = SPL.log
@@ -144,6 +174,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \ spl/u-boot-nand-spl.imx: SPL FORCE $(call if_changed,u-boot-nand-spl_imx) +endif targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
tools/imx8m_image.sh new file +30 -0
@@ -0,0 +1,30 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to check whether the file exists in imximage.cfg for i.MX8 +# +# usage: $0 <imximage.cfg> + +file=$1 + +blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2} /^SECOND_LOADER/ {print $2} /^DDR_FW/ {print $2}' $file` +for f in $blobs; do + tmp=$srctree/$f + + if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then + continue + fi + + if [ -f $f ]; then + continue + fi + + if [ ! -f $tmp ]; then + echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2 + exit 1 + fi + + sed -in "s;$f;$tmp;" $file +done + +exit 0
Signature · 1 line
2.14.1
PATCH 12/15 imx: imx8m: not build bootaux when building SPL
In reply to Peng FanNo need to build bootaux in SPL stage
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/mach-imx/Makefile | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/mach-imx/Makefile +2 -0
@@ -10,7 +10,9 @@ obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),imx8m)) +ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
Signature · 1 line
2.14.1
PATCH 13/15 imx: imx8m: add lpddr4 header file
In reply to Peng FanIntroduce lpddr4 header file
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/include/asm/arch-imx8m/lpddr4_define.h | 100 ++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8m/lpddr4_define.h
arch/arm/include/asm/arch-imx8m/lpddr4_define.h new file +100 -0
@@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Copyright 2018 NXP +*/ + +#ifndef __LPDDR4_DEFINE_H_ +#define __LPDDR4_DEFINE_H_ + +#define LPDDR4_DVFS_DBI +#define DDR_ONE_RANK +/* #define LPDDR4_DBI_ON */ +#define DFI_BUG_WR +#define M845S_4GBx2 +#define PRETRAIN + +/* DRAM MR setting */ +#ifdef LPDDR4_DBI_ON +#define LPDDR4_MR3 0xf1 +#define LPDDR4_PHY_DMIPinPresent 0x1 +#else +#define LPDDR4_MR3 0x31 +#define LPDDR4_PHY_DMIPinPresent 0x0 +#endif + +#ifdef DDR_ONE_RANK +#define LPDDR4_CS 0x1 +#else +#define LPDDR4_CS 0x3 +#endif + +/* PHY training feature */ +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +/* 400/100 training seq */ +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) +#define LPDDR4_MR22_RANK0 ((0 << 5) | (0 << 4) | (0 << 3) | \ + (LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5) | (0 << 4) | (1 << 3) | \ + (LPDDR4_RTT40)) + +#define LPDDR4_MR3_PU_CAL 1 + +#endif /* __LPDDR4_DEFINE_H__ */
Signature · 1 line
2.14.1
PATCH 14/15 drivers: ddr: introduce DDR driver for i.MX8M
In reply to Peng FanIntroduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller.
Signed-off-by Peng Fan <[email protected]>
--- arch/arm/include/asm/arch-imx8m/ddr.h | 575 ++++++++++++++++++++++++++++++++++ drivers/Makefile | 1 + drivers/ddr/Kconfig | 1 + drivers/ddr/imx/Kconfig | 1 + drivers/ddr/imx/imx8m/Kconfig | 22 ++ drivers/ddr/imx/imx8m/Makefile | 11 + drivers/ddr/imx/imx8m/ddr4_init.c | 113 +++++++ drivers/ddr/imx/imx8m/ddrphy_train.c | 87 +++++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 186 +++++++++++ drivers/ddr/imx/imx8m/helper.c | 171 ++++++++++ drivers/ddr/imx/imx8m/lpddr4_init.c | 188 +++++++++++ 11 files changed, 1356 insertions(+) create mode 100644 drivers/ddr/imx/Kconfig create mode 100644 drivers/ddr/imx/imx8m/Kconfig create mode 100644 drivers/ddr/imx/imx8m/Makefile create mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_train.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_utils.c create mode 100644 drivers/ddr/imx/imx8m/helper.c create mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.c
arch/arm/include/asm/arch-imx8m/ddr.h +575 -0
@@ -6,6 +6,10 @@#ifndef __ASM_ARCH_IMX8M_DDR_H#define __ASM_ARCH_IMX8M_DDR_H +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/ddr.h> +#define DDRC_DDR_SS_GPR0 0x3d000000#define DDRC_IPS_BASE_ADDR_0 0x3f400000#define IP2APB_DDRPHY_IPS_BASE_ADDR (X ) (0x3c000000 + (X * 0x2000000))
@@ -352,4 +356,575 @@ enum msg_response { TRAIN_FAIL = 0xff, }; +#define DDRC_MSTR_0 0x3d400000 +#define DDRC_STAT_0 0x3d400004 +#define DDRC_MSTR1_0 0x3d400008 +#define DDRC_MRCTRL0_0 0x3d400010 +#define DDRC_MRCTRL1_0 0x3d400014 +#define DDRC_MRSTAT_0 0x3d400018 +#define DDRC_MRCTRL2_0 0x3d40001c +#define DDRC_DERATEEN_0 0x3d400020 +#define DDRC_DERATEINT_0 0x3d400024 +#define DDRC_MSTR2_0 0x3d400028 +#define DDRC_PWRCTL_0 0x3d400030 +#define DDRC_PWRTMG_0 0x3d400034 +#define DDRC_HWLPCTL_0 0x3d400038 +#define DDRC_HWFFCCTL_0 0x3d40003c +#define DDRC_HWFFCSTAT_0 0x3d400040 +#define DDRC_RFSHCTL0_0 0x3d400050 +#define DDRC_RFSHCTL1_0 0x3d400054 +#define DDRC_RFSHCTL2_0 0x3d400058 +#define DDRC_RFSHCTL3_0 0x3d400060 +#define DDRC_RFSHTMG_0 0x3d400064 +#define DDRC_ECCCFG0_0 0x3d400070 +#define DDRC_ECCCFG1_0 0x3d400074 +#define DDRC_ECCSTAT_0 0x3d400078 +#define DDRC_ECCCLR_0 0x3d40007c +#define DDRC_ECCERRCNT_0 0x3d400080 +#define DDRC_ECCCADDR0_0 0x3d400084 +#define DDRC_ECCCADDR1_0 0x3d400088 +#define DDRC_ECCCSYN0_0 0x3d40008c +#define DDRC_ECCCSYN1_0 0x3d400090 +#define DDRC_ECCCSYN2_0 0x3d400094 +#define DDRC_ECCBITMASK0_0 0x3d400098 +#define DDRC_ECCBITMASK1_0 0x3d40009c +#define DDRC_ECCBITMASK2_0 0x3d4000a0 +#define DDRC_ECCUADDR0_0 0x3d4000a4 +#define DDRC_ECCUADDR1_0 0x3d4000a8 +#define DDRC_ECCUSYN0_0 0x3d4000ac +#define DDRC_ECCUSYN1_0 0x3d4000b0 +#define DDRC_ECCUSYN2_0 0x3d4000b4 +#define DDRC_ECCPOISONADDR0_0 0x3d4000b8 +#define DDRC_ECCPOISONADDR1_0 0x3d4000bc +#define DDRC_CRCPARCTL0_0 0x3d4000c0 +#define DDRC_CRCPARCTL1_0 0x3d4000c4 +#define DDRC_CRCPARCTL2_0 0x3d4000c8 +#define DDRC_CRCPARSTAT_0 0x3d4000cc +#define DDRC_INIT0_0 0x3d4000d0 +#define DDRC_INIT1_0 0x3d4000d4 +#define DDRC_INIT2_0 0x3d4000d8 +#define DDRC_INIT3_0 0x3d4000dc +#define DDRC_INIT4_0 0x3d4000e0 +#define DDRC_INIT5_0 0x3d4000e4 +#define DDRC_INIT6_0 0x3d4000e8 +#define DDRC_INIT7_0 0x3d4000ec +#define DDRC_DIMMCTL_0 0x3d4000f0 +#define DDRC_RANKCTL_0 0x3d4000f4 +#define DDRC_DRAMTMG0_0 0x3d400100 +#define DDRC_DRAMTMG1_0 0x3d400104 +#define DDRC_DRAMTMG2_0 0x3d400108 +#define DDRC_DRAMTMG3_0 0x3d40010c +#define DDRC_DRAMTMG4_0 0x3d400110 +#define DDRC_DRAMTMG5_0 0x3d400114 +#define DDRC_DRAMTMG6_0 0x3d400118 +#define DDRC_DRAMTMG7_0 0x3d40011c +#define DDRC_DRAMTMG8_0 0x3d400120 +#define DDRC_DRAMTMG9_0 0x3d400124 +#define DDRC_DRAMTMG10_0 0x3d400128 +#define DDRC_DRAMTMG11_0 0x3d40012c +#define DDRC_DRAMTMG12_0 0x3d400130 +#define DDRC_DRAMTMG13_0 0x3d400134 +#define DDRC_DRAMTMG14_0 0x3d400138 +#define DDRC_DRAMTMG15_0 0x3d40013C +#define DDRC_DRAMTMG16_0 0x3d400140 +#define DDRC_DRAMTMG17_0 0x3d400144 + +#define DDRC_ZQCTL0_0 0x3d400180 +#define DDRC_ZQCTL1_0 0x3d400184 +#define DDRC_ZQCTL2_0 0x3d400188 +#define DDRC_ZQSTAT_0 0x3d40018c +#define DDRC_DFITMG0_0 0x3d400190 +#define DDRC_DFITMG1_0 0x3d400194 +#define DDRC_DFILPCFG0_0 0x3d400198 +#define DDRC_DFILPCFG1_0 0x3d40019c +#define DDRC_DFIUPD0_0 0x3d4001a0 +#define DDRC_DFIUPD1_0 0x3d4001a4 +#define DDRC_DFIUPD2_0 0x3d4001a8 + +#define DDRC_DFIMISC_0 0x3d4001b0 +#define DDRC_DFITMG2_0 0x3d4001b4 +#define DDRC_DFITMG3_0 0x3d4001b8 +#define DDRC_DFISTAT_0 0x3d4001bc + +#define DDRC_DBICTL_0 0x3d4001c0 +#define DDRC_DFIPHYMSTR_0 0x3d4001c4 +#define DDRC_TRAINCTL0_0 0x3d4001d0 +#define DDRC_TRAINCTL1_0 0x3d4001d4 +#define DDRC_TRAINCTL2_0 0x3d4001d8 +#define DDRC_TRAINSTAT_0 0x3d4001dc +#define DDRC_ADDRMAP0_0 0x3d400200 +#define DDRC_ADDRMAP1_0 0x3d400204 +#define DDRC_ADDRMAP2_0 0x3d400208 +#define DDRC_ADDRMAP3_0 0x3d40020c +#define DDRC_ADDRMAP4_0 0x3d400210 +#define DDRC_ADDRMAP5_0 0x3d400214 +#define DDRC_ADDRMAP6_0 0x3d400218 +#define DDRC_ADDRMAP7_0 0x3d40021c +#define DDRC_ADDRMAP8_0 0x3d400220 +#define DDRC_ADDRMAP9_0 0x3d400224 +#define DDRC_ADDRMAP10_0 0x3d400228 +#define DDRC_ADDRMAP11_0 0x3d40022c + +#define DDRC_ODTCFG_0 0x3d400240 +#define DDRC_ODTMAP_0 0x3d400244 +#define DDRC_SCHED_0 0x3d400250 +#define DDRC_SCHED1_0 0x3d400254 +#define DDRC_PERFHPR1_0 0x3d40025c +#define DDRC_PERFLPR1_0 0x3d400264 +#define DDRC_PERFWR1_0 0x3d40026c +#define DDRC_PERFVPR1_0 0x3d400274 + +#define DDRC_PERFVPW1_0 0x3d400278 + +#define DDRC_DQMAP0_0 0x3d400280 +#define DDRC_DQMAP1_0 0x3d400284 +#define DDRC_DQMAP2_0 0x3d400288 +#define DDRC_DQMAP3_0 0x3d40028c +#define DDRC_DQMAP4_0 0x3d400290 +#define DDRC_DQMAP5_0 0x3d400294 +#define DDRC_DBG0_0 0x3d400300 +#define DDRC_DBG1_0 0x3d400304 +#define DDRC_DBGCAM_0 0x3d400308 +#define DDRC_DBGCMD_0 0x3d40030c +#define DDRC_DBGSTAT_0 0x3d400310 + +#define DDRC_SWCTL_0 0x3d400320 +#define DDRC_SWSTAT_0 0x3d400324 +#define DDRC_OCPARCFG0_0 0x3d400330 +#define DDRC_OCPARCFG1_0 0x3d400334 +#define DDRC_OCPARCFG2_0 0x3d400338 +#define DDRC_OCPARCFG3_0 0x3d40033c +#define DDRC_OCPARSTAT0_0 0x3d400340 +#define DDRC_OCPARSTAT1_0 0x3d400344 +#define DDRC_OCPARWLOG0_0 0x3d400348 +#define DDRC_OCPARWLOG1_0 0x3d40034c +#define DDRC_OCPARWLOG2_0 0x3d400350 +#define DDRC_OCPARAWLOG0_0 0x3d400354 +#define DDRC_OCPARAWLOG1_0 0x3d400358 +#define DDRC_OCPARRLOG0_0 0x3d40035c +#define DDRC_OCPARRLOG1_0 0x3d400360 +#define DDRC_OCPARARLOG0_0 0x3d400364 +#define DDRC_OCPARARLOG1_0 0x3d400368 +#define DDRC_POISONCFG_0 0x3d40036C +#define DDRC_POISONSTAT_0 0x3d400370 +#define DDRC_ADVECCINDEX_0 0x3d400003 +#define DDRC_ADVECCSTAT_0 0x3d400003 +#define DDRC_ECCPOISONPAT0_0 0x3d400003 +#define DDRC_ECCPOISONPAT1_0 0x3d400003 +#define DDRC_ECCPOISONPAT2_0 0x3d400003 +#define DDRC_HIFCTL_0 0x3d400003 + +#define DDRC_PSTAT_0 0x3d4003fc +#define DDRC_PCCFG_0 0x3d400400 +#define DDRC_PCFGR_0_0 0x3d400404 +#define DDRC_PCFGR_1_0 0x3d4004b4 +#define DDRC_PCFGR_2_0 0x3d400564 +#define DDRC_PCFGR_3_0 0x3d400614 +#define DDRC_PCFGW_0_0 0x3d400408 +#define DDRC_PCFGW_1_0 0x3d400408 +#define DDRC_PCFGW_2_0 0x3d400568 +#define DDRC_PCFGW_3_0 0x3d400618 +#define DDRC_PCFGC_0_0 0x3d40040c +#define DDRC_PCFGIDMASKCH_0 0x3d400410 +#define DDRC_PCFGIDVALUECH_0 0x3d400414 +#define DDRC_PCTRL_0_0 0x3d400490 +#define DDRC_PCTRL_1_0 0x3d400540 +#define DDRC_PCTRL_2_0 0x3d4005f0 +#define DDRC_PCTRL_3_0 0x3d4006a0 +#define DDRC_PCFGQOS0_0_0 0x3d400494 +#define DDRC_PCFGQOS1_0_0 0x3d400498 +#define DDRC_PCFGWQOS0_0_0 0x3d40049c +#define DDRC_PCFGWQOS1_0_0 0x3d4004a0 +#define DDRC_SARBASE0_0 0x3d400f04 +#define DDRC_SARSIZE0_0 0x3d400f08 +#define DDRC_SBRCTL_0 0x3d400f24 +#define DDRC_SBRSTAT_0 0x3d400f28 +#define DDRC_SBRWDATA0_0 0x3d400f2c +#define DDRC_SBRWDATA1_0 0x3d400f30 +#define DDRC_PDCH_0 0x3d400f34 + +/**********************/ +#define DDRC_MSTR (X ) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN (X ) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR (X ) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x144) +#define DDRC_ZQCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) +#define DDRC_DBICTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x22c) +#define DDRC_ODTCFG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP (X ) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED (X ) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x274) +#define DDRC_PERFVPW1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x278) +#define DDRC_DQMAP0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM (X ) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD (X ) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x310) +#define DDRC_SWCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x370) +#define DDRC_ADVECCINDEX (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ADVECCSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_HIFCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) + +#define DDRC_PSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1 (X ) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2 (X ) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3 (X ) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1 (X ) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2 (X ) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3 (X ) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH (X ) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH (X ) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH (X ) (DDRC_IPS_BASE_ADDR(X) + 0xf34) + +#define DDRC_FREQ1_DERATEEN (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG (X ) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW (X ) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW (X ) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW (X ) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRPHY_CalBusy (X ) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097) + +#define DRC_PERF_MON_BASE_ADDR (X ) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_MRR0_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +/* user data type */ +enum fw_type { +FW_1D_IMAGE , +FW_2D_IMAGE , +}; + +struct dram_cfg_param { +unsigned int reg; +unsigned int val; +}; + +struct dram_fsp_msg { +unsigned int drate; +enum fw_type fw_type; +struct dram_cfg_param *fsp_cfg; +unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { +/* umctl2 config */ +struct dram_cfg_param *ddrc_cfg; +unsigned int ddrc_cfg_num; +/* ddrphy config */ +struct dram_cfg_param *ddrphy_cfg; +unsigned int ddrphy_cfg_num; +/* ddr fsp train info */ +struct dram_fsp_msg *fsp_msg; +unsigned int fsp_msg_num; +/* ddr phy trained CSR */ +struct dram_cfg_param *ddrphy_trained_csr; +unsigned int ddrphy_trained_csr_num; +/* ddr phy PIE */ +struct dram_cfg_param *ddrphy_pie; +unsigned int ddrphy_pie_num; +/* initialized drate table */ +unsigned int fsp_table[4 ]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware (enum fw_type type); +void ddr_init (struct dram_timing_info *timing_info); +void ddr_cfg_phy (struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie (void ); +void ddrphy_trained_csr_save (struct dram_cfg_param *param,unsigned int num); +void dram_config_save (struct dram_timing_info *info,unsigned long base); + +/* utils function for ddr phy training */ +void wait_ddrphy_training_complete (void ); +void ddrphy_init_set_dfi_clk (unsigned int drate); +void ddrphy_init_read_msg_block (enum fw_type type); + +static inline void reg32_write (unsigned long addr,u32 val) +{ +writel (val, addr); +} + +static inline u32 reg32_read (unsigned long addr) +{ +return readl (addr); +} + +static inline void reg32setbit (unsigned long addr,u32 bit) +{ +setbits_le32 (addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr (addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd (addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))#endif
drivers/Makefile +1 -0
@@ -28,6 +28,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
drivers/ddr/Kconfig +1 -0
@@ -1 +1,2 @@ source "drivers/ddr/altera/Kconfig" +source "drivers/ddr/imx/Kconfig"
drivers/ddr/imx/Kconfig new file +1 -0
@@ -0,0 +1 @@ +source "drivers/ddr/imx/imx8m/Kconfig"
drivers/ddr/imx/imx8m/Kconfig new file +22 -0
@@ -0,0 +1,22 @@ +config IMX8M_DRAM + bool "imx8m dram" + +config IMX8M_LPDDR4 + bool "imx8m lpddr4" + select IMX8M_DRAM + help + Select the i.MX8M LPDDR4 driver support on i.MX8M SOC. + +config IMX8M_DDR4 + bool "imx8m ddr4" + select IMX8M_DRAM + help + Select the i.MX8M DDR4 driver support on i.MX8M SOC. + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. OCRAM_S is used for this + purpose on i.MX8MM. + default 0x180000
drivers/ddr/imx/imx8m/Makefile new file +11 -0
@@ -0,0 +1,11 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o +endif
drivers/ddr/imx/imx8m/ddr4_init.c new file +113 -0
113 lines not on this page · raw message
drivers/ddr/imx/imx8m/ddrphy_train.c new file +87 -0
87 lines not on this page · raw message
drivers/ddr/imx/imx8m/ddrphy_utils.c new file +186 -0
186 lines not on this page · raw message
drivers/ddr/imx/imx8m/helper.c new file +171 -0
171 lines not on this page · raw message
drivers/ddr/imx/imx8m/lpddr4_init.c new file +188 -0
188 lines not on this page · raw message
Signature · 1 line
2.14.1
PATCH 14/15 drivers: ddr: introduce DDR driver for i.MX8M
Quoted 42 lines · Peng Fan
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller.
Signed-off-by Peng Fan <[email protected]>--- arch/arm/include/asm/arch-imx8m/ddr.h | 575 ++++++++++++++++++++++++++++++++++ drivers/Makefile | 1 + drivers/ddr/Kconfig | 1 + drivers/ddr/imx/Kconfig | 1 + drivers/ddr/imx/imx8m/Kconfig | 22 ++ drivers/ddr/imx/imx8m/Makefile | 11 + drivers/ddr/imx/imx8m/ddr4_init.c | 113 +++++++ drivers/ddr/imx/imx8m/ddrphy_train.c | 87 +++++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 186 +++++++++++ drivers/ddr/imx/imx8m/helper.c | 171 ++++++++++ drivers/ddr/imx/imx8m/lpddr4_init.c | 188 +++++++++++ 11 files changed, 1356 insertions(+) create mode 100644 drivers/ddr/imx/Kconfig create mode 100644 drivers/ddr/imx/imx8m/Kconfig create mode 100644 drivers/ddr/imx/imx8m/Makefile create mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_train.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_utils.c create mode 100644 drivers/ddr/imx/imx8m/helper.c create mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.carch/arm/include/asm/arch-imx8m/ddr.h +4
-0@@ -6,6 +6,10 @@#ifndef __ASM_ARCH_IMX8M_DDR_H#define __ASM_ARCH_IMX8M_DDR_H +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/ddr.h> +#define DDRC_DDR_SS_GPR0 0x3d000000#define DDRC_IPS_BASE_ADDR_0 0x3f400000#define IP2APB_DDRPHY_IPS_BASE_ADDR (X ) (0x3c000000 + (X * 0x2000000))
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 361
Quoted 6 lines
arch/arm/include/asm/arch-imx8m/ddr.h +3
-0@@ -352,4 +356,575 @@ enum msg_response { TRAIN_FAIL = 0xff, }; +#define DDRC_MSTR_0 0x3d400000 +#define DDRC_STAT_0 0x3d400004 +#define DDRC_MSTR1_0 0x3d400008
Looks like this should be a structure
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 549
Quoted 4 lines
arch/arm/include/asm/arch-imx8m/ddr.h +4
-0+/**********************/ +#define DDRC_MSTR (X ) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x08)
Same structure
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 696
Quoted 6 lines
arch/arm/include/asm/arch-imx8m/ddr.h +6
-0+#define DDRC_ADVECCINDEX (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ADVECCSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_HIFCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3)
Are they really the same address ???
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 837
Quoted 5 lines
arch/arm/include/asm/arch-imx8m/ddr.h +5
-0+#define DRC_PERF_MON_BASE_ADDR (X ) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL (X ) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
Structure
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 383
Quoted 7 lines
arch/arm/include/asm/arch-imx8m/ddr.h +7
-0+void ddrphy_init_set_dfi_clk (unsigned int drate) +{ +switch (drate) { +case 3200 : +dram_pll_init (DRAM_PLL_OUT_800M ); +dram_disable_bypass (); +break ;
Maybe drate can be changed to a Hz freq instead of MHZ
if (drate > 400M) {
dram_pll_init(drate/4);
dram_disable_bypass();
} else {
dram_enable_bypass(drate);
}PATCH 14/15 drivers: ddr: introduce DDR driver for i.MX8M
Quoted 61 lines
-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: 2018年11月10日 2:53
To: Peng Fan <[email protected]>; sbabic at denx.de; Fabio Estevam <[email protected]>
Cc: u-boot at lists.denx.de; dl-linux-imx <[email protected]>
Subject: Re: [U-Boot] [PATCH 14/15] drivers: ddr: introduce DDR driver for i.MX8MQuoted 6 lines · Peng Fan
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller.
Signed-off-by Peng Fan <[email protected]>--- arch/arm/include/asm/arch-imx8m/ddr.h | 575++++++++++++++++++++++++++++++++++
Quoted 12 lines
drivers/Makefile | 1 + drivers/ddr/Kconfig | 1 + drivers/ddr/imx/Kconfig | 1 + drivers/ddr/imx/imx8m/Kconfig | 22 ++ drivers/ddr/imx/imx8m/Makefile | 11 + drivers/ddr/imx/imx8m/ddr4_init.c | 113 +++++++ drivers/ddr/imx/imx8m/ddrphy_train.c | 87 +++++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 186 +++++++++++ drivers/ddr/imx/imx8m/helper.c | 171 ++++++++++ drivers/ddr/imx/imx8m/lpddr4_init.c | 188 +++++++++++ 11 files changed, 1356 insertions(+) create mode 100644 drivers/ddr/imx/Kconfig create mode 100644Quoted 6 lines
drivers/ddr/imx/imx8m/Kconfigcreate mode 100644drivers/ddr/imx/imx8m/Makefilecreate mode 100644drivers/ddr/imx/imx8m/ddr4_init.ccreate mode 100644drivers/ddr/imx/imx8m/ddrphy_train.ccreate mode 100644 drivers/ddr/imx/imx8m/ddrphy_utils.c create mode 100644 drivers/ddr/imx/imx8m/helper.c create mode100644
Quoted 8 lines
drivers/ddr/imx/imx8m/lpddr4_init.carch/arm/include/asm/arch-imx8m/ddr.h +0
-0arch/arm/include/asm/arch-imx8m/ddr.h line 15
Quoted 10 lines
arch/arm/include/asm/arch-imx8m/ddr.h +4
-0@@ -6,6 +6,10 @@#ifndef __ASM_ARCH_IMX8M_DDR_H#define __ASM_ARCH_IMX8M_DDR_H +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/ddr.h> +#define DDRC_DDR_SS_GPR0 0x3d000000#define DDRC_IPS_BASE_ADDR_0 0x3f400000#define IP2APB_DDRPHY_IPS_BASE_ADDR (X ) (0x3c000000 + (X *
0x2000000))Quoted 4 lines
arch/arm/include/asm/arch-imx8m/ddr.h +0
-0@@ -352,4 +356,575 @@ enum msg_response { TRAIN_FAIL = 0xff, };
Quoted 5 lines
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 361
Quoted 3 lines
arch/arm/include/asm/arch-imx8m/ddr.h +3
-0+#define DDRC_MSTR_0 0x3d400000 +#define DDRC_STAT_0 0x3d400004 +#define DDRC_MSTR1_0 0x3d400008Looks like this should be a structure
I tried structure before, see https://patchwork.ozlabs.org/patch/857974/
But that still not good. There are too many registers, I would like
to keep current code. The ddr code are used in NXP vendor tree and are used in GA release, and the ddr tool will auto generated code, manually converting the current code to structure will be also easy to introduce errors.
Stefano, Fabio, what do you think?
Quoted 8 lines
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 549
Quoted 5 lines
arch/arm/include/asm/arch-imx8m/ddr.h +4
-0+/**********************/ +#define DDRC_MSTR (X ) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x08)Same structure
Quoted 8 lines
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 696
Quoted 6 lines
arch/arm/include/asm/arch-imx8m/ddr.h +6
-0+#define DDRC_ADVECCINDEX (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ADVECCSTAT (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT0 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT1 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT2 (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_HIFCTL (X ) (DDRC_IPS_BASE_ADDR(X) + 0x3)Are they really the same address ???
This could be dropped.
Thanks,
Peng.
Quoted 29 lines
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 372
Quoted 2 lines
arch/arm/include/asm/arch-imx8m/ddr.h +1
-0+#define DRC_PERF_MON_BASE_ADDR (X ) (0x3d800000 + ((X) *
0x2000000))arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 373
Quoted 1 line
arch/arm/include/asm/arch-imx8m/ddr.h +1
-0+#define DRC_PERF_MON_CNT0_CTL (X )(
DRC_PERF_MON_BASE_ADDR(X)+0x0)arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 374
Quoted 1 line
arch/arm/include/asm/arch-imx8m/ddr.h +1
-0+#define DRC_PERF_MON_CNT1_CTL (X )(
DRC_PERF_MON_BASE_ADDR(X)+0x4)arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 375
Quoted 1 line
arch/arm/include/asm/arch-imx8m/ddr.h +1
-0+#define DRC_PERF_MON_CNT2_CTL (X )(
DRC_PERF_MON_BASE_ADDR(X)+0x8)arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 376
Quoted 1 line
arch/arm/include/asm/arch-imx8m/ddr.h +1
-0+#define DRC_PERF_MON_CNT3_CTL (X )(
DRC_PERF_MON_BASE_ADDR(X)+0xC)Structure
arch/arm/include/asm/arch-imx8m/ddr.h enum msg_response { · line 382
Quoted 6 lines
arch/arm/include/asm/arch-imx8m/ddr.h +6
-0+void ddrphy_init_set_dfi_clk (unsigned int drate) { +switch (drate) { +case 3200 : +dram_pll_init (DRAM_PLL_OUT_800M ); +dram_disable_bypass (); +break ;Maybe drate can be changed to a Hz freq instead of MHZ
if (drate > 400M) { dram_pll_init(drate/4); dram_disable_bypass(); } else { dram_enable_bypass(drate); }
Fabio Estevam
reviewerPATCH 14/15 drivers: ddr: introduce DDR driver for i.MX8M
Hi Peng,
Quoted 7 lines · Peng Fan
I tried structure before, see https://patchwork.ozlabs.org/patch/857974/
But that still not good. There are too many registers, I would like
to keep current code. The ddr code are used in NXP vendor tree and are used in GA release, and the ddr tool will auto generated code, manually converting the current code to structure will be also easy to introduce errors.Stefano, Fabio, what do you think?
I am fine with the current approach from this patch.
PATCH 15/15 imx: add i.MX8MQ EVK support
In reply to Peng FanAdd i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM.
The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-rc3-00029-gc824c60f06 (Nov 09 2018 - 17:16:05 +0800)
PMIC: PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
U-Boot 2018.11-rc3-00029-gc824c60f06 (Nov 09 2018 - 17:16:05 +0800)
CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial
Net:
Warning: ethernet at 30be0000 using MAC address from ROM
eth0: ethernet at 30be0000
Hit any key to stop autoboot: 0
u-boot=>
"
Signed-off-by Peng Fan <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8mq-evk.dts | 414 +++++ arch/arm/mach-imx/imx8m/Kconfig | 13 + board/freescale/imx8mq_evk/Kconfig | 12 + board/freescale/imx8mq_evk/MAINTAINERS | 6 + board/freescale/imx8mq_evk/Makefile | 12 + board/freescale/imx8mq_evk/README | 36 + board/freescale/imx8mq_evk/imx8mq_evk.c | 130 ++ board/freescale/imx8mq_evk/lpddr4_timing.c | 2104 +++++++++++++++++++++++++ board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1972 +++++++++++++++++++++++ board/freescale/imx8mq_evk/spl.c | 246 +++ configs/imx8mq_evk_defconfig | 37 + include/configs/imx8mq_evk.h | 252 +++ 13 files changed, 5236 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts create mode 100644 board/freescale/imx8mq_evk/Kconfig create mode 100644 board/freescale/imx8mq_evk/MAINTAINERS create mode 100644 board/freescale/imx8mq_evk/Makefile create mode 100644 board/freescale/imx8mq_evk/README create mode 100644 board/freescale/imx8mq_evk/imx8mq_evk.c create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing_b0.c create mode 100644 board/freescale/imx8mq_evk/spl.c create mode 100644 configs/imx8mq_evk_defconfig create mode 100644 include/configs/imx8mq_evk.h
arch/arm/dts/Makefile +2 -0
@@ -456,6 +456,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb-u-boot.dtb \ r8a7795-salvator-x-u-boot.dtb \
arch/arm/dts/fsl-imx8mq-evk.dts new file +414 -0
414 lines not on this page · raw message
arch/arm/mach-imx/imx8m/Kconfig +13 -0
@@ -7,4 +7,17 @@ config IMX8M config SYS_SOC default "imx8m" +choice + prompt "NXP i.MX8M board select" + optional + +config TARGET_IMX8MQ_EVK + bool "imx8mq_evk" + select IMX8M + select IMX8M_LPDDR4 + +endchoice + +source "board/freescale/imx8mq_evk/Kconfig" + endif
board/freescale/imx8mq_evk/Kconfig new file +12 -0
@@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_EVK + +config SYS_BOARD + default "imx8mq_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_evk" + +endif
board/freescale/imx8mq_evk/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +i.MX8MQ EVK BOARD +M: Peng Fan <[email protected]> +S: Maintained +F: board/freescale/imx8mq_evk/ +F: include/configs/imx8mq_evk.h +F: configs/imx8mq_evk_defconfig
board/freescale/imx8mq_evk/Makefile new file +12 -0
@@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif
board/freescale/imx8mq_evk/README new file +36 -0
@@ -0,0 +1,36 @@ +U-Boot for the NXP i.MX8MQ EVK board + +Quick Start +==================== +- Build the ARM Trusted firmware binary +- Get ddr and hdmi fimware +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +==================== +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +branch: imx_4.14.62_1.0.0_beta +$ make PLAT=imx8mq bl31 + +Get the ddr and hdmi firmware +==================== +Note: srctree is U-Boot source directory +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin +$ chmod +x firmware-imx-7.9.bin +$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree) +$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee) + +Build U-Boot +==================== +$ export ARCH=arm64 +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make imx8mq_evk_defconfig +$ make flash.bin + +Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==================== +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
board/freescale/imx8mq_evk/imx8mq_evk.c new file +130 -0
130 lines not on this page · raw message
board/freescale/imx8mq_evk/lpddr4_timing.c new file +2104 -0
2,104 lines not on this page · raw message
board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file +1972 -0
261 lines not on this page · raw message
board/freescale/imx8mq_evk/spl.c new file +246 -0
246 lines not on this page · raw message
include/configs/imx8mq_evk.h new file +252 -0
252 lines not on this page · raw message
The rest of this diff is not shown. View the raw message.
Signature · 1 line
2.14.1
Part of the diff is not shown here. View the raw message.
PATCH 15/15 imx: add i.MX8MQ EVK support
board/freescale/imx8mq_evk/lpddr4_timing_b0.c line 72
Quoted 10 lines · Peng Fan
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM....
board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file +5
-0+ +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { +/* Start to config, default 3200mbps */ +/* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + {DDRC_DBG1 (0 ),0x00000001 },
Just a little elaboration on how a structure might work here
#define DDRC_ADDR(reg, x) &((struct ddrc *)(DDRC_IPS_BASE_ADDR(x))->reg)
{ DDRC_ADDR(dbg1, 0), 0x00000001 },Thanks for working on this Peng!
BR
Troy
PATCH 15/15 imx: add i.MX8MQ EVK support
Quoted 22 lines · Troy Kisky
board/freescale/imx8mq_evk/lpddr4_timing_b0.c line 72
Quoted 10 lines · Peng Fan
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM....
board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file +5
-0+ +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { +/* Start to config, default 3200mbps */ +/* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + {DDRC_DBG1 (0 ),0x00000001 },Just a little elaboration on how a structure might work here
#define
DDRC_ADDR(reg, x)&((struct ddrc *)(DDRC_IPS_BASE_ADDR(x))->reg){ DDRC_ADDR(dbg1, 0), 0x00000001 },
Quoted 5 lines
Thanks for working on this Peng!
BR
Troy
Yes thanks for working on this Peng. Just to clarify one thing. Do you have a script that is generating the structures from output of the mx8m_ddr_tool, or is the mx8m_ddr_tool being changed to output the structures?
-Jon
PATCH 15/15 imx: add i.MX8MQ EVK support
Quoted 39 lines
-----Original Message-----
From: Jon Nettleton [mailto:jon at solid-run.com]
Sent: 2018年11月13日 15:53
To: Troy Kisky <[email protected]>
Cc: Peng Fan <[email protected]>; sbabic at denx.de; Fabio Estevam <[email protected]>; U-Boot Mailing List <[email protected]>; dl-linux-imx <[email protected]>
Subject: Re: [U-Boot] [PATCH 15/15] imx: add i.MX8MQ EVK supportQuoted 26 lines · Troy Kisky
board/freescale/imx8mq_evk/lpddr4_timing_b0.c line 72
Quoted 10 lines · Peng Fan
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM....
board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file +5
-0+ +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { +/* Start to config, default 3200mbps */ +/* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + {DDRC_DBG1 (0 ),0x00000001 },Just a little elaboration on how a structure might work here
#define
DDRC_ADDR(reg, x)&((struct ddrc
*)(DDRC_IPS_BASE_ADDR(x))->reg){ DDRC_ADDR(dbg1, 0), 0x00000001 },Thanks for working on this Peng!
Quoted 6 lines
Quoted 2 lines
BR
TroyYes thanks for working on this Peng. Just to clarify one thing. Do you have a script that is generating the structures from output of the
mx8m_ddr_tool, or is themx8m_ddr_toolbeing changed to output the structures?
Currently the i.MX8MQ ddr is still original format, not the format used in this patch. When NXP GA software release, I think the ddr tool will support this new format.
Regards,
Peng.
Quoted 2 lines
-Jon
PATCH 15/15 imx: add i.MX8MQ EVK support
In reply to Peng Fan*snip*
Quoted 29 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +26
-0@@ -0,0 +1,2104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> + +#define LPDDR4_HDT_CTL_2D 0xC8/* stage completion */ +#define LPDDR4_HDT_CTL_3200_1D 0xC8/* stage completion */ +#define LPDDR4_HDT_CTL_400_1D 0xC8/* stage completion */ +#define LPDDR4_HDT_CTL_100_1D 0xC8/* stage completion */ + +// 400/100 training seq +#define LPDDR4_TRAIN_SEQ_100 0x121f +#define LPDDR4_TRAIN_SEQ_400 0x121f + +//2D share & weight +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 +
board/freescale/imx8mq_evk/lpddr4_timing.c line 36
Quoted 10 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +10
-0+#define WR_POST_EXT_3200 /* recommened to define */ + +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0
Are these board specific? They seem like they should be defined in ddr.h
board/freescale/imx8mq_evk/lpddr4_timing.c line 43
Quoted 7 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +7
-0+ +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3
ditto.
Quoted 9 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +9
-0+ +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40/* MR3[5:3] */
board/freescale/imx8mq_evk/lpddr4_timing.c line 62
Quoted 10 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +10
-0+#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40/* MR11[2:0] */ +#define LPDDR4_RTT_CA LPDDR4_RTT40/* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40/* MR11[6:4] */ +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40/* LPDDR4_RTT_DIS */
do these values ever differ? seems like it would be better to use LPDDR_RTT and then have the board file #define LPDRR4_RTT to LPDDR4_RTT40
board/freescale/imx8mq_evk/lpddr4_timing.c line 71
Quoted 9 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +9
-0+#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd))/* MR12 */ +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd))/* MR14 */ +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd))/* MR14 */ +#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \ + (LPDDR4_RTT40))/* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR22_RANK1 ((0 << 5) | (1 << 4) | (0 << 3) | \ + (LPDDR4_RTT40))/* MR22: OP[5:3]ODTD-CA,CS,CK */ +#define LPDDR4_MR3_PU_CAL 1/* MR3[0] */ +
*snip*
Quoted 6 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +5
-0+ +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + {0x213149 ,0xfbe }, +
board/freescale/imx8mq_evk/lpddr4_timing.c line 323
Quoted 10 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +10
-0+ { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
Are there any benefits to not just using the register writes here?
board/freescale/imx8mq_evk/lpddr4_timing.c
Quoted 2 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +2
-0+ + { 0x20018, 0x3 },
*snip*
Quoted 713 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +713
-0+ +/* ddr phy trained csr */ +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + {0x200b2 ,0x0 }, + {0x1200b2 ,0x0 }, + {0x2200b2 ,0x0 }, + {0x200cb ,0x0 }, + {0x10043 ,0x0 }, + {0x110043 ,0x0 }, + {0x210043 ,0x0 }, + {0x10143 ,0x0 }, + {0x110143 ,0x0 }, + {0x210143 ,0x0 }, + {0x11043 ,0x0 }, + {0x111043 ,0x0 }, + {0x211043 ,0x0 }, + {0x11143 ,0x0 }, + {0x111143 ,0x0 }, + {0x211143 ,0x0 }, + {0x12043 ,0x0 }, + {0x112043 ,0x0 }, + {0x212043 ,0x0 }, + {0x12143 ,0x0 }, + {0x112143 ,0x0 }, + {0x212143 ,0x0 }, + {0x13043 ,0x0 }, + {0x113043 ,0x0 }, + {0x213043 ,0x0 }, + {0x13143 ,0x0 }, + {0x113143 ,0x0 }, + {0x213143 ,0x0 }, + {0x80 ,0x0 }, + {0x100080 ,0x0 }, + {0x200080 ,0x0 }, + {0x1080 ,0x0 }, + {0x101080 ,0x0 }, + {0x201080 ,0x0 }, + {0x2080 ,0x0 }, + {0x102080 ,0x0 }, + {0x202080 ,0x0 }, + {0x3080 ,0x0 }, + {0x103080 ,0x0 }, + {0x203080 ,0x0 }, + {0x4080 ,0x0 }, + {0x104080 ,0x0 }, + {0x204080 ,0x0 }, + {0x5080 ,0x0 }, + {0x105080 ,0x0 }, + {0x205080 ,0x0 }, + {0x6080 ,0x0 }, + {0x106080 ,0x0 }, + {0x206080 ,0x0 }, + {0x7080 ,0x0 }, + {0x107080 ,0x0 }, + {0x207080 ,0x0 }, + {0x8080 ,0x0 }, + {0x108080 ,0x0 }, + {0x208080 ,0x0 }, + {0x9080 ,0x0 }, + {0x109080 ,0x0 }, + {0x209080 ,0x0 }, + {0x10080 ,0x0 }, + {0x110080 ,0x0 }, + {0x210080 ,0x0 }, + {0x10180 ,0x0 }, + {0x110180 ,0x0 }, + {0x210180 ,0x0 }, + {0x11080 ,0x0 }, + {0x111080 ,0x0 }, + {0x211080 ,0x0 }, + {0x11180 ,0x0 }, + {0x111180 ,0x0 }, + {0x211180 ,0x0 }, + {0x12080 ,0x0 }, + {0x112080 ,0x0 }, + {0x212080 ,0x0 }, + {0x12180 ,0x0 }, + {0x112180 ,0x0 }, + {0x212180 ,0x0 }, + {0x13080 ,0x0 }, + {0x113080 ,0x0 }, + {0x213080 ,0x0 }, + {0x13180 ,0x0 }, + {0x113180 ,0x0 }, + {0x213180 ,0x0 }, + {0x10081 ,0x0 }, + {0x110081 ,0x0 }, + {0x210081 ,0x0 }, + {0x10181 ,0x0 }, + {0x110181 ,0x0 }, + {0x210181 ,0x0 }, + {0x11081 ,0x0 }, + {0x111081 ,0x0 }, + {0x211081 ,0x0 }, + {0x11181 ,0x0 }, + {0x111181 ,0x0 }, + {0x211181 ,0x0 }, + {0x12081 ,0x0 }, + {0x112081 ,0x0 }, + {0x212081 ,0x0 }, + {0x12181 ,0x0 }, + {0x112181 ,0x0 }, + {0x212181 ,0x0 }, + {0x13081 ,0x0 }, + {0x113081 ,0x0 }, + {0x213081 ,0x0 }, + {0x13181 ,0x0 }, + {0x113181 ,0x0 }, + {0x213181 ,0x0 }, + {0x100d0 ,0x0 }, + {0x1100d0 ,0x0 }, + {0x2100d0 ,0x0 }, + {0x101d0 ,0x0 }, + {0x1101d0 ,0x0 }, + {0x2101d0 ,0x0 }, + {0x110d0 ,0x0 }, + {0x1110d0 ,0x0 }, + {0x2110d0 ,0x0 }, + {0x111d0 ,0x0 }, + {0x1111d0 ,0x0 }, + {0x2111d0 ,0x0 }, + {0x120d0 ,0x0 }, + {0x1120d0 ,0x0 }, + {0x2120d0 ,0x0 }, + {0x121d0 ,0x0 }, + {0x1121d0 ,0x0 }, + {0x2121d0 ,0x0 }, + {0x130d0 ,0x0 }, + {0x1130d0 ,0x0 }, + {0x2130d0 ,0x0 }, + {0x131d0 ,0x0 }, + {0x1131d0 ,0x0 }, + {0x2131d0 ,0x0 }, + {0x100d1 ,0x0 }, + {0x1100d1 ,0x0 }, + {0x2100d1 ,0x0 }, + {0x101d1 ,0x0 }, + {0x1101d1 ,0x0 }, + {0x2101d1 ,0x0 }, + {0x110d1 ,0x0 }, + {0x1110d1 ,0x0 }, + {0x2110d1 ,0x0 }, + {0x111d1 ,0x0 }, + {0x1111d1 ,0x0 }, + {0x2111d1 ,0x0 }, + {0x120d1 ,0x0 }, + {0x1120d1 ,0x0 }, + {0x2120d1 ,0x0 }, + {0x121d1 ,0x0 }, + {0x1121d1 ,0x0 }, + {0x2121d1 ,0x0 }, + {0x130d1 ,0x0 }, + {0x1130d1 ,0x0 }, + {0x2130d1 ,0x0 }, + {0x131d1 ,0x0 }, + {0x1131d1 ,0x0 }, + {0x2131d1 ,0x0 }, + {0x10068 ,0x0 }, + {0x10168 ,0x0 }, + {0x10268 ,0x0 }, + {0x10368 ,0x0 }, + {0x10468 ,0x0 }, + {0x10568 ,0x0 }, + {0x10668 ,0x0 }, + {0x10768 ,0x0 }, + {0x10868 ,0x0 }, + {0x11068 ,0x0 }, + {0x11168 ,0x0 }, + {0x11268 ,0x0 }, + {0x11368 ,0x0 }, + {0x11468 ,0x0 }, + {0x11568 ,0x0 }, + {0x11668 ,0x0 }, + {0x11768 ,0x0 }, + {0x11868 ,0x0 }, + {0x12068 ,0x0 }, + {0x12168 ,0x0 }, + {0x12268 ,0x0 }, + {0x12368 ,0x0 }, + {0x12468 ,0x0 }, + {0x12568 ,0x0 }, + {0x12668 ,0x0 }, + {0x12768 ,0x0 }, + {0x12868 ,0x0 }, + {0x13068 ,0x0 }, + {0x13168 ,0x0 }, + {0x13268 ,0x0 }, + {0x13368 ,0x0 }, + {0x13468 ,0x0 }, + {0x13568 ,0x0 }, + {0x13668 ,0x0 }, + {0x13768 ,0x0 }, + {0x13868 ,0x0 }, + {0x10069 ,0x0 }, + {0x10169 ,0x0 }, + {0x10269 ,0x0 }, + {0x10369 ,0x0 }, + {0x10469 ,0x0 }, + {0x10569 ,0x0 }, + {0x10669 ,0x0 }, + {0x10769 ,0x0 }, + {0x10869 ,0x0 }, + {0x11069 ,0x0 }, + {0x11169 ,0x0 }, + {0x11269 ,0x0 }, + {0x11369 ,0x0 }, + {0x11469 ,0x0 }, + {0x11569 ,0x0 }, + {0x11669 ,0x0 }, + {0x11769 ,0x0 }, + {0x11869 ,0x0 }, + {0x12069 ,0x0 }, + {0x12169 ,0x0 }, + {0x12269 ,0x0 }, + {0x12369 ,0x0 }, + {0x12469 ,0x0 }, + {0x12569 ,0x0 }, + {0x12669 ,0x0 }, + {0x12769 ,0x0 }, + {0x12869 ,0x0 }, + {0x13069 ,0x0 }, + {0x13169 ,0x0 }, + {0x13269 ,0x0 }, + {0x13369 ,0x0 }, + {0x13469 ,0x0 }, + {0x13569 ,0x0 }, + {0x13669 ,0x0 }, + {0x13769 ,0x0 }, + {0x13869 ,0x0 }, + {0x1008c ,0x0 }, + {0x11008c ,0x0 }, + {0x21008c ,0x0 }, + {0x1018c ,0x0 }, + {0x11018c ,0x0 }, + {0x21018c ,0x0 }, + {0x1108c ,0x0 }, + {0x11108c ,0x0 }, + {0x21108c ,0x0 }, + {0x1118c ,0x0 }, + {0x11118c ,0x0 }, + {0x21118c ,0x0 }, + {0x1208c ,0x0 }, + {0x11208c ,0x0 }, + {0x21208c ,0x0 }, + {0x1218c ,0x0 }, + {0x11218c ,0x0 }, + {0x21218c ,0x0 }, + {0x1308c ,0x0 }, + {0x11308c ,0x0 }, + {0x21308c ,0x0 }, + {0x1318c ,0x0 }, + {0x11318c ,0x0 }, + {0x21318c ,0x0 }, + {0x1008d ,0x0 }, + {0x11008d ,0x0 }, + {0x21008d ,0x0 }, + {0x1018d ,0x0 }, + {0x11018d ,0x0 }, + {0x21018d ,0x0 }, + {0x1108d ,0x0 }, + {0x11108d ,0x0 }, + {0x21108d ,0x0 }, + {0x1118d ,0x0 }, + {0x11118d ,0x0 }, + {0x21118d ,0x0 }, + {0x1208d ,0x0 }, + {0x11208d ,0x0 }, + {0x21208d ,0x0 }, + {0x1218d ,0x0 }, + {0x11218d ,0x0 }, + {0x21218d ,0x0 }, + {0x1308d ,0x0 }, + {0x11308d ,0x0 }, + {0x21308d ,0x0 }, + {0x1318d ,0x0 }, + {0x11318d ,0x0 }, + {0x21318d ,0x0 }, + {0x100c0 ,0x0 }, + {0x1100c0 ,0x0 }, + {0x2100c0 ,0x0 }, + {0x101c0 ,0x0 }, + {0x1101c0 ,0x0 }, + {0x2101c0 ,0x0 }, + {0x102c0 ,0x0 }, + {0x1102c0 ,0x0 }, + {0x2102c0 ,0x0 }, + {0x103c0 ,0x0 }, + {0x1103c0 ,0x0 }, + {0x2103c0 ,0x0 }, + {0x104c0 ,0x0 }, + {0x1104c0 ,0x0 }, + {0x2104c0 ,0x0 }, + {0x105c0 ,0x0 }, + {0x1105c0 ,0x0 }, + {0x2105c0 ,0x0 }, + {0x106c0 ,0x0 }, + {0x1106c0 ,0x0 }, + {0x2106c0 ,0x0 }, + {0x107c0 ,0x0 }, + {0x1107c0 ,0x0 }, + {0x2107c0 ,0x0 }, + {0x108c0 ,0x0 }, + {0x1108c0 ,0x0 }, + {0x2108c0 ,0x0 }, + {0x110c0 ,0x0 }, + {0x1110c0 ,0x0 }, + {0x2110c0 ,0x0 }, + {0x111c0 ,0x0 }, + {0x1111c0 ,0x0 }, + {0x2111c0 ,0x0 }, + {0x112c0 ,0x0 }, + {0x1112c0 ,0x0 }, + {0x2112c0 ,0x0 }, + {0x113c0 ,0x0 }, + {0x1113c0 ,0x0 }, + {0x2113c0 ,0x0 }, + {0x114c0 ,0x0 }, + {0x1114c0 ,0x0 }, + {0x2114c0 ,0x0 }, + {0x115c0 ,0x0 }, + {0x1115c0 ,0x0 }, + {0x2115c0 ,0x0 }, + {0x116c0 ,0x0 }, + {0x1116c0 ,0x0 }, + {0x2116c0 ,0x0 }, + {0x117c0 ,0x0 }, + {0x1117c0 ,0x0 }, + {0x2117c0 ,0x0 }, + {0x118c0 ,0x0 }, + {0x1118c0 ,0x0 }, + {0x2118c0 ,0x0 }, + {0x120c0 ,0x0 }, + {0x1120c0 ,0x0 }, + {0x2120c0 ,0x0 }, + {0x121c0 ,0x0 }, + {0x1121c0 ,0x0 }, + {0x2121c0 ,0x0 }, + {0x122c0 ,0x0 }, + {0x1122c0 ,0x0 }, + {0x2122c0 ,0x0 }, + {0x123c0 ,0x0 }, + {0x1123c0 ,0x0 }, + {0x2123c0 ,0x0 }, + {0x124c0 ,0x0 }, + {0x1124c0 ,0x0 }, + {0x2124c0 ,0x0 }, + {0x125c0 ,0x0 }, + {0x1125c0 ,0x0 }, + {0x2125c0 ,0x0 }, + {0x126c0 ,0x0 }, + {0x1126c0 ,0x0 }, + {0x2126c0 ,0x0 }, + {0x127c0 ,0x0 }, + {0x1127c0 ,0x0 }, + {0x2127c0 ,0x0 }, + {0x128c0 ,0x0 }, + {0x1128c0 ,0x0 }, + {0x2128c0 ,0x0 }, + {0x130c0 ,0x0 }, + {0x1130c0 ,0x0 }, + {0x2130c0 ,0x0 }, + {0x131c0 ,0x0 }, + {0x1131c0 ,0x0 }, + {0x2131c0 ,0x0 }, + {0x132c0 ,0x0 }, + {0x1132c0 ,0x0 }, + {0x2132c0 ,0x0 }, + {0x133c0 ,0x0 }, + {0x1133c0 ,0x0 }, + {0x2133c0 ,0x0 }, + {0x134c0 ,0x0 }, + {0x1134c0 ,0x0 }, + {0x2134c0 ,0x0 }, + {0x135c0 ,0x0 }, + {0x1135c0 ,0x0 }, + {0x2135c0 ,0x0 }, + {0x136c0 ,0x0 }, + {0x1136c0 ,0x0 }, + {0x2136c0 ,0x0 }, + {0x137c0 ,0x0 }, + {0x1137c0 ,0x0 }, + {0x2137c0 ,0x0 }, + {0x138c0 ,0x0 }, + {0x1138c0 ,0x0 }, + {0x2138c0 ,0x0 }, + {0x100c1 ,0x0 }, + {0x1100c1 ,0x0 }, + {0x2100c1 ,0x0 }, + {0x101c1 ,0x0 }, + {0x1101c1 ,0x0 }, + {0x2101c1 ,0x0 }, + {0x102c1 ,0x0 }, + {0x1102c1 ,0x0 }, + {0x2102c1 ,0x0 }, + {0x103c1 ,0x0 }, + {0x1103c1 ,0x0 }, + {0x2103c1 ,0x0 }, + {0x104c1 ,0x0 }, + {0x1104c1 ,0x0 }, + {0x2104c1 ,0x0 }, + {0x105c1 ,0x0 }, + {0x1105c1 ,0x0 }, + {0x2105c1 ,0x0 }, + {0x106c1 ,0x0 }, + {0x1106c1 ,0x0 }, + {0x2106c1 ,0x0 }, + {0x107c1 ,0x0 }, + {0x1107c1 ,0x0 }, + {0x2107c1 ,0x0 }, + {0x108c1 ,0x0 }, + {0x1108c1 ,0x0 }, + {0x2108c1 ,0x0 }, + {0x110c1 ,0x0 }, + {0x1110c1 ,0x0 }, + {0x2110c1 ,0x0 }, + {0x111c1 ,0x0 }, + {0x1111c1 ,0x0 }, + {0x2111c1 ,0x0 }, + {0x112c1 ,0x0 }, + {0x1112c1 ,0x0 }, + {0x2112c1 ,0x0 }, + {0x113c1 ,0x0 }, + {0x1113c1 ,0x0 }, + {0x2113c1 ,0x0 }, + {0x114c1 ,0x0 }, + {0x1114c1 ,0x0 }, + {0x2114c1 ,0x0 }, + {0x115c1 ,0x0 }, + {0x1115c1 ,0x0 }, + {0x2115c1 ,0x0 }, + {0x116c1 ,0x0 }, + {0x1116c1 ,0x0 }, + {0x2116c1 ,0x0 }, + {0x117c1 ,0x0 }, + {0x1117c1 ,0x0 }, + {0x2117c1 ,0x0 }, + {0x118c1 ,0x0 }, + {0x1118c1 ,0x0 }, + {0x2118c1 ,0x0 }, + {0x120c1 ,0x0 }, + {0x1120c1 ,0x0 }, + {0x2120c1 ,0x0 }, + {0x121c1 ,0x0 }, + {0x1121c1 ,0x0 }, + {0x2121c1 ,0x0 }, + {0x122c1 ,0x0 }, + {0x1122c1 ,0x0 }, + {0x2122c1 ,0x0 }, + {0x123c1 ,0x0 }, + {0x1123c1 ,0x0 }, + {0x2123c1 ,0x0 }, + {0x124c1 ,0x0 }, + {0x1124c1 ,0x0 }, + {0x2124c1 ,0x0 }, + {0x125c1 ,0x0 }, + {0x1125c1 ,0x0 }, + {0x2125c1 ,0x0 }, + {0x126c1 ,0x0 }, + {0x1126c1 ,0x0 }, + {0x2126c1 ,0x0 }, + {0x127c1 ,0x0 }, + {0x1127c1 ,0x0 }, + {0x2127c1 ,0x0 }, + {0x128c1 ,0x0 }, + {0x1128c1 ,0x0 }, + {0x2128c1 ,0x0 }, + {0x130c1 ,0x0 }, + {0x1130c1 ,0x0 }, + {0x2130c1 ,0x0 }, + {0x131c1 ,0x0 }, + {0x1131c1 ,0x0 }, + {0x2131c1 ,0x0 }, + {0x132c1 ,0x0 }, + {0x1132c1 ,0x0 }, + {0x2132c1 ,0x0 }, + {0x133c1 ,0x0 }, + {0x1133c1 ,0x0 }, + {0x2133c1 ,0x0 }, + {0x134c1 ,0x0 }, + {0x1134c1 ,0x0 }, + {0x2134c1 ,0x0 }, + {0x135c1 ,0x0 }, + {0x1135c1 ,0x0 }, + {0x2135c1 ,0x0 }, + {0x136c1 ,0x0 }, + {0x1136c1 ,0x0 }, + {0x2136c1 ,0x0 }, + {0x137c1 ,0x0 }, + {0x1137c1 ,0x0 }, + {0x2137c1 ,0x0 }, + {0x138c1 ,0x0 }, + {0x1138c1 ,0x0 }, + {0x2138c1 ,0x0 }, + {0x10020 ,0x0 }, + {0x110020 ,0x0 }, + {0x210020 ,0x0 }, + {0x11020 ,0x0 }, + {0x111020 ,0x0 }, + {0x211020 ,0x0 }, + {0x12020 ,0x0 }, + {0x112020 ,0x0 }, + {0x212020 ,0x0 }, + {0x13020 ,0x0 }, + {0x113020 ,0x0 }, + {0x213020 ,0x0 }, + {0x20072 ,0x0 }, + {0x20073 ,0x0 }, + {0x20074 ,0x0 }, + {0x100aa ,0x0 }, + {0x110aa ,0x0 }, + {0x120aa ,0x0 }, + {0x130aa ,0x0 }, + {0x20010 ,0x0 }, + {0x120010 ,0x0 }, + {0x220010 ,0x0 }, + {0x20011 ,0x0 }, + {0x120011 ,0x0 }, + {0x220011 ,0x0 }, + {0x100ae ,0x0 }, + {0x1100ae ,0x0 }, + {0x2100ae ,0x0 }, + {0x100af ,0x0 }, + {0x1100af ,0x0 }, + {0x2100af ,0x0 }, + {0x110ae ,0x0 }, + {0x1110ae ,0x0 }, + {0x2110ae ,0x0 }, + {0x110af ,0x0 }, + {0x1110af ,0x0 }, + {0x2110af ,0x0 }, + {0x120ae ,0x0 }, + {0x1120ae ,0x0 }, + {0x2120ae ,0x0 }, + {0x120af ,0x0 }, + {0x1120af ,0x0 }, + {0x2120af ,0x0 }, + {0x130ae ,0x0 }, + {0x1130ae ,0x0 }, + {0x2130ae ,0x0 }, + {0x130af ,0x0 }, + {0x1130af ,0x0 }, + {0x2130af ,0x0 }, + {0x20020 ,0x0 }, + {0x120020 ,0x0 }, + {0x220020 ,0x0 }, + {0x100a0 ,0x0 }, + {0x100a1 ,0x0 }, + {0x100a2 ,0x0 }, + {0x100a3 ,0x0 }, + {0x100a4 ,0x0 }, + {0x100a5 ,0x0 }, + {0x100a6 ,0x0 }, + {0x100a7 ,0x0 }, + {0x110a0 ,0x0 }, + {0x110a1 ,0x0 }, + {0x110a2 ,0x0 }, + {0x110a3 ,0x0 }, + {0x110a4 ,0x0 }, + {0x110a5 ,0x0 }, + {0x110a6 ,0x0 }, + {0x110a7 ,0x0 }, + {0x120a0 ,0x0 }, + {0x120a1 ,0x0 }, + {0x120a2 ,0x0 }, + {0x120a3 ,0x0 }, + {0x120a4 ,0x0 }, + {0x120a5 ,0x0 }, + {0x120a6 ,0x0 }, + {0x120a7 ,0x0 }, + {0x130a0 ,0x0 }, + {0x130a1 ,0x0 }, + {0x130a2 ,0x0 }, + {0x130a3 ,0x0 }, + {0x130a4 ,0x0 }, + {0x130a5 ,0x0 }, + {0x130a6 ,0x0 }, + {0x130a7 ,0x0 }, + {0x2007c ,0x0 }, + {0x12007c ,0x0 }, + {0x22007c ,0x0 }, + {0x2007d ,0x0 }, + {0x12007d ,0x0 }, + {0x22007d ,0x0 }, + {0x400fd ,0x0 }, + {0x400c0 ,0x0 }, + {0x90201 ,0x0 }, + {0x190201 ,0x0 }, + {0x290201 ,0x0 }, + {0x90202 ,0x0 }, + {0x190202 ,0x0 }, + {0x290202 ,0x0 }, + {0x90203 ,0x0 }, + {0x190203 ,0x0 }, + {0x290203 ,0x0 }, + {0x90204 ,0x0 }, + {0x190204 ,0x0 }, + {0x290204 ,0x0 }, + {0x90205 ,0x0 }, + {0x190205 ,0x0 }, + {0x290205 ,0x0 }, + {0x90206 ,0x0 }, + {0x190206 ,0x0 }, + {0x290206 ,0x0 }, + {0x90207 ,0x0 }, + {0x190207 ,0x0 }, + {0x290207 ,0x0 }, + {0x90208 ,0x0 }, + {0x190208 ,0x0 }, + {0x290208 ,0x0 }, + {0x10062 ,0x0 }, + {0x10162 ,0x0 }, + {0x10262 ,0x0 }, + {0x10362 ,0x0 }, + {0x10462 ,0x0 }, + {0x10562 ,0x0 }, + {0x10662 ,0x0 }, + {0x10762 ,0x0 }, + {0x10862 ,0x0 }, + {0x11062 ,0x0 }, + {0x11162 ,0x0 }, + {0x11262 ,0x0 }, + {0x11362 ,0x0 }, + {0x11462 ,0x0 }, + {0x11562 ,0x0 }, + {0x11662 ,0x0 }, + {0x11762 ,0x0 }, + {0x11862 ,0x0 }, + {0x12062 ,0x0 }, + {0x12162 ,0x0 }, + {0x12262 ,0x0 }, + {0x12362 ,0x0 }, + {0x12462 ,0x0 }, + {0x12562 ,0x0 }, + {0x12662 ,0x0 }, + {0x12762 ,0x0 }, + {0x12862 ,0x0 }, + {0x13062 ,0x0 }, + {0x13162 ,0x0 }, + {0x13262 ,0x0 }, + {0x13362 ,0x0 }, + {0x13462 ,0x0 }, + {0x13562 ,0x0 }, + {0x13662 ,0x0 }, + {0x13762 ,0x0 }, + {0x13862 ,0x0 }, + {0x20077 ,0x0 }, + {0x10001 ,0x0 }, + {0x11001 ,0x0 }, + {0x12001 ,0x0 }, + {0x13001 ,0x0 }, + {0x10040 ,0x0 }, + {0x10140 ,0x0 }, + {0x10240 ,0x0 }, + {0x10340 ,0x0 }, + {0x10440 ,0x0 }, + {0x10540 ,0x0 }, + {0x10640 ,0x0 }, + {0x10740 ,0x0 }, + {0x10840 ,0x0 }, + {0x10030 ,0x0 }, + {0x10130 ,0x0 }, + {0x10230 ,0x0 }, + {0x10330 ,0x0 }, + {0x10430 ,0x0 }, + {0x10530 ,0x0 }, + {0x10630 ,0x0 }, + {0x10730 ,0x0 }, + {0x10830 ,0x0 }, + {0x11040 ,0x0 }, + {0x11140 ,0x0 }, + {0x11240 ,0x0 }, + {0x11340 ,0x0 }, + {0x11440 ,0x0 }, + {0x11540 ,0x0 }, + {0x11640 ,0x0 }, + {0x11740 ,0x0 }, + {0x11840 ,0x0 }, + {0x11030 ,0x0 }, + {0x11130 ,0x0 }, + {0x11230 ,0x0 }, + {0x11330 ,0x0 }, + {0x11430 ,0x0 }, + {0x11530 ,0x0 }, + {0x11630 ,0x0 }, + {0x11730 ,0x0 }, + {0x11830 ,0x0 }, + {0x12040 ,0x0 }, + {0x12140 ,0x0 }, + {0x12240 ,0x0 }, + {0x12340 ,0x0 }, + {0x12440 ,0x0 }, + {0x12540 ,0x0 }, + {0x12640 ,0x0 }, + {0x12740 ,0x0 }, + {0x12840 ,0x0 }, + {0x12030 ,0x0 }, + {0x12130 ,0x0 }, + {0x12230 ,0x0 }, + {0x12330 ,0x0 }, + {0x12430 ,0x0 }, + {0x12530 ,0x0 }, + {0x12630 ,0x0 }, + {0x12730 ,0x0 }, + {0x12830 ,0x0 }, + {0x13040 ,0x0 }, + {0x13140 ,0x0 }, + {0x13240 ,0x0 }, + {0x13340 ,0x0 }, + {0x13440 ,0x0 }, + {0x13540 ,0x0 }, + {0x13640 ,0x0 }, + {0x13740 ,0x0 }, + {0x13840 ,0x0 },
board/freescale/imx8mq_evk/lpddr4_timing.c line 1107
Quoted 10 lines
board/freescale/imx8mq_evk/lpddr4_timing.c new file +10
-0+ { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +};
This is just a generic structure to store values. This should live in the mx8m lpddr code not in the board file.
I have put together a rough perl script that can generate this format
form the existing code generated by the mx8m ddr tool. If other mx8m
devs want to test it let me know. This is still some copy paste but it parses the values properly and populates the structures.
-Jon
PATCH 1/15 Introduce CONFIG_FIT_EXTERNAL_OFFSET
In reply to Peng FanQuoted 14 lines · Peng Fan
Introduce
CONFIG_FIT_EXTERNAL_OFFSETto give user a choice to choose where to put the external data.Signed-off-by Peng Fan <[email protected]>--- Kconfig | 6 ++++++ Makefile | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-)Kconfig +0
-0
Kconfig config FIT · line 255
Quoted 8 lines
Kconfig +5
-0@@ -248,6 +248,12 @@ config FIT if FIT +config FIT_EXTERNAL_OFFSET + hex "Text Base" + default 0x0 + help + This specifics a data offset in fit image.
"specifies". And another sentence about why or when this is useful would be good. Thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181109/ab0bcc70/attachment.sig>