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parisc: Replace sync instruction by nop on UP kernel

PATCH In review Helge Deller 2 participants 3 messages Nov 9, 2018 – Nov 11, 2018 PA-RISC architecture

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Helge Deller

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#0 lore raw

PATCH 1/1 parisc: Replace sync instruction by nop on UP kernel

Signed-off-by Helge Deller <[email protected]>
arch/parisc/include/asm/barrier.h +2 -1
index dbaaca84f27f..43bcdccc56b8 100644
@@ -6,7 +6,8 @@
 
 /* The synchronize caches instruction executes as a nop on systems in
    which all memory references are performed in order. */
-#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory")
+#define synchronize_caches() asm volatile \
+	("sync" ALTERNATIVE(ALT_COND_NO_SMP, INSN_NOP) : : : "memory")
 
 #if defined(CONFIG_SMP)
 #define mb()		do { synchronize_caches(); } while (0)
#1 lore raw
Quoted 7 lines · Helge Deller
Signed-off-by Helge Deller <[email protected]>
arch/parisc/include/asm/barrier.h +0 -0
index dbaaca84f27f..43bcdccc56b8 100644

arch/parisc/include/asm/barrier.h line 13

Quoted 9 lines
arch/parisc/include/asm/barrier.h +2 -1
@@ -6,7 +6,8 @@
 
  /* The synchronize caches instruction executes as a nop on systems in
     which all memory references are performed in order. */
-#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory")
+#define synchronize_caches() asm volatile \
+	("sync" ALTERNATIVE(ALT_COND_NO_SMP, INSN_NOP) : : : "memory")
 
  #if defined(CONFIG_SMP)
  #define mb()		do { synchronize_caches(); } while (0)

Although this change is consistent with mb() on UP kernels, I'm thinking that it is wrong.  That is the PA 2.0 out-of-order execution of memory accesses is likely visible on a UP machine when an interruption occurs.  I think the UP and SMP defines for mb() need to be the same.

Dave

Signature · 1 line
John David Anglin  [email protected]
author maintainer
#2 lore raw
Quoted 18 lines · John David Anglin
Quoted 12 lines · Helge Deller
Signed-off-by Helge Deller <[email protected]>
arch/parisc/include/asm/barrier.h +0 -0
index dbaaca84f27f..43bcdccc56b8 100644
@@ -6,7 +6,8 @@
     /* The synchronize caches instruction executes as a nop on systems in

     which all memory references are performed in order. */

arch/parisc/include/asm/barrier.h +2 -1
-#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory")
+#define synchronize_caches() asm volatile \
+    ("sync" ALTERNATIVE(ALT_COND_NO_SMP, INSN_NOP) : : : "memory")
Quoted 2 lines

    #if defined(CONFIG_SMP)
  #define mb()        do { synchronize_caches(); } while (0)

Although this change is consistent with mb() on UP kernels, I'm thinking that it is wrong.  That is the PA 2.0 out-of-order execution of memory accesses is likely visible on a UP machine when an interruption occurs.  I think the UP and SMP defines for mb() need to be the same.

I think you are right with the fact that the sync-removals in this patch and the other one was wrong. I'll resend the patch without touching sync in a few moments.
I'll keep the remaining patches in my for-next-next git branch.

Helge