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cpu: Fix typos

PATCH In review Junchang Wang 3 participants 6 messages Nov 10, 2018 – Nov 13, 2018

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Junchang Wang

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#0 lore raw

PATCH 1/1 cpu: Fix typos

Signed-off-by Junchang Wang <[email protected]>

---
Hi Paul,

This is the only patch for Chapter CPU. Please take a look.

Thanks,
--Junchang

--

 cpu/overheads.tex | 4 ++--
 cpu/overview.tex  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
cpu/overheads.tex +2 -2
index 2474cfe..17b120b 100644
@@ -155,7 +155,7 @@ displayed in
 Table~\ref{tab:cpu:Performance of Synchronization Mechanisms on 4-CPU 1.8GHz AMD Opteron 844 System}.
 This system's clock period rounds to 0.6\,ns.
 Although it is not unusual for modern microprocessors to be able to
-retire multiple instructions per clock period, the operations's costs are
+retire multiple instructions per clock period, the operations' costs are
 nevertheless normalized to a clock period in the third column, labeled
 ``Ratio''.
 The first thing to note about this table is the large values of many of

@@ -360,7 +360,7 @@ It is clear that the combination of speculative execution and cloud
 computing needs more than a bit of rework!
 
 A fifth hardware optimization is large caches, allowing individual
-CPUs to operate on larger datasets without incuring expensive cache
+CPUs to operate on larger datasets without incurring expensive cache
 misses.
 Although large caches can degrade energy efficiency and cache-miss
 latency, the ever-growing cache sizes on production microprocessors
cpu/overview.tex +1 -1
index 071cf7c..9e91a7b 100644
@@ -15,7 +15,7 @@ where the race always goes to the swiftest.
 \ContributedBy{Figure}{fig:cpu:CPU Performance at its Best}{Melissa Broussard}
 \end{figure}
 
-Although there are a few CPU-bound benchmarks that approach the ideal
+Although there are a few CPU-bound benchmarks that approach the ideal case
 shown in Figure~\ref{fig:cpu:CPU Performance at its Best},
 the typical program more closely resembles an obstacle course than
 a race track.
Signature · 1 line
2.7.4
#1 lore raw
Quoted 29 lines · Junchang Wang
Signed-off-by Junchang Wang <[email protected]>

---
Hi Paul,

This is the only patch for Chapter CPU. Please take a look.

Thanks,
--Junchang

--

 cpu/overheads.tex | 4 ++--
 cpu/overview.tex  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
cpu/overheads.tex +1 -1
index 2474cfe..17b120b 100644
@@ -155,7 +155,7 @@ displayed in
 Table~\ref{tab:cpu:Performance of Synchronization Mechanisms on 4-CPU 1.8GHz AMD Opteron 844 System}.
 This system's clock period rounds to 0.6\,ns.
 Although it is not unusual for modern microprocessors to be able to
-retire multiple instructions per clock period, the operations's costs are
+retire multiple instructions per clock period, the operations' costs are
 nevertheless normalized to a clock period in the third column, labeled
 ``Ratio''.
 The first thing to note about this table is the large values of many of

cpu/overheads.tex It is clear that the combination of speculative execution and cloud · line 364

Quoted 6 lines
cpu/overheads.tex +1 -1
@@ -360,7 +360,7 @@ It is clear that the combination of speculative execution and cloud
 computing needs more than a bit of rework!
 
 A fifth hardware optimization is large caches, allowing individual
-CPUs to operate on larger datasets without incuring expensive cache
+CPUs to operate on larger datasets without incurring expensive cache
 misses.

Nice catches!

cpu/overview.tex where the race always goes to the swiftest. · line 19

Quoted 13 lines
cpu/overheads.tex +0 -0
 Although large caches can degrade energy efficiency and cache-miss
 latency, the ever-growing cache sizes on production microprocessors
cpu/overview.tex +1 -1
index 071cf7c..9e91a7b 100644
@@ -15,7 +15,7 @@ where the race always goes to the swiftest.
 \ContributedBy{Figure}{fig:cpu:CPU Performance at its Best}{Melissa Broussard}
 \end{figure}
 
-Although there are a few CPU-bound benchmarks that approach the ideal
+Although there are a few CPU-bound benchmarks that approach the ideal case
 shown in Figure~\ref{fig:cpu:CPU Performance at its Best},

"ideal" can be used as a noun. I don't think this hunk is necessary.

Thanks, Akira

Quoted 3 lines
cpu/overview.tex +0 -0
 the typical program more closely resembles an obstacle course than
 a race track.
#2 lore raw
Quoted 32 lines · Akira Yokosawa
Quoted 31 lines · Junchang Wang
Signed-off-by Junchang Wang <[email protected]>

---
Hi Paul,

This is the only patch for Chapter CPU. Please take a look.

Thanks,
--Junchang

--

 cpu/overheads.tex | 4 ++--
 cpu/overview.tex  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
cpu/overheads.tex +1 -1
index 2474cfe..17b120b 100644
@@ -155,7 +155,7 @@ displayed in
 Table~\ref{tab:cpu:Performance of Synchronization Mechanisms on 4-CPU 1.8GHz AMD Opteron 844 System}.
 This system's clock period rounds to 0.6\,ns.
 Although it is not unusual for modern microprocessors to be able to
-retire multiple instructions per clock period, the operations's costs are
+retire multiple instructions per clock period, the operations' costs are
 nevertheless normalized to a clock period in the third column, labeled
 ``Ratio''.
 The first thing to note about this table is the large values of many of

@@ -360,7 +360,7 @@ It is clear that the combination of speculative execution and cloud
 computing needs more than a bit of rework!
Quoted 6 lines

cpu/overheads.tex It is clear that the combination of speculative execution and cloud · line 364

Quoted 4 lines
cpu/overheads.tex +1 -1
 A fifth hardware optimization is large caches, allowing individual
-CPUs to operate on larger datasets without incuring expensive cache
+CPUs to operate on larger datasets without incurring expensive cache
 misses.

Nice catches!

Indeed!!! ;-)

Quoted 10 lines
Quoted 10 lines
cpu/overheads.tex +0 -0
 Although large caches can degrade energy efficiency and cache-miss
 latency, the ever-growing cache sizes on production microprocessors
cpu/overview.tex +0 -0
index 071cf7c..9e91a7b 100644
@@ -15,7 +15,7 @@ where the race always goes to the swiftest.
 \ContributedBy{Figure}{fig:cpu:CPU Performance at its Best}{Melissa Broussard}
 \end{figure}
Quoted 5 lines

cpu/overview.tex where the race always goes to the swiftest. · line 19

Quoted 3 lines
cpu/overview.tex +1 -1
-Although there are a few CPU-bound benchmarks that approach the ideal
+Although there are a few CPU-bound benchmarks that approach the ideal case
 shown in Figure~\ref{fig:cpu:CPU Performance at its Best},

"ideal" can be used as a noun. I don't think this hunk is necessary.

This is quite true, but making it a bit less confusing to non-native English speakers is worth something. Not that I am volunteering to confine myself to the 850-word vocabulary of Basic English, mind you! ;-)

So Akira has a good point, but I will take Junchang's patch.

Thanx, Paul

Quoted 6 lines

Thanks, Akira

Quoted 3 lines
cpu/overview.tex +0 -0
 the typical program more closely resembles an obstacle course than
 a race track.
author
#3 lore raw
Quoted 34 lines · Paul E. McKenney
Quoted 32 lines · Akira Yokosawa
Quoted 31 lines · Junchang Wang
Signed-off-by Junchang Wang <[email protected]>

---
Hi Paul,

This is the only patch for Chapter CPU. Please take a look.

Thanks,
--Junchang

--

 cpu/overheads.tex | 4 ++--
 cpu/overview.tex  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
cpu/overheads.tex +1 -1
index 2474cfe..17b120b 100644
@@ -155,7 +155,7 @@ displayed in
 Table~\ref{tab:cpu:Performance of Synchronization Mechanisms on 4-CPU 1.8GHz AMD Opteron 844 System}.
 This system's clock period rounds to 0.6\,ns.
 Although it is not unusual for modern microprocessors to be able to
-retire multiple instructions per clock period, the operations's costs are
+retire multiple instructions per clock period, the operations' costs are
 nevertheless normalized to a clock period in the third column, labeled
 ``Ratio''.
 The first thing to note about this table is the large values of many of

@@ -360,7 +360,7 @@ It is clear that the combination of speculative execution and cloud
 computing needs more than a bit of rework!
Quoted 25 lines
Quoted 6 lines

cpu/overheads.tex It is clear that the combination of speculative execution and cloud · line 364

Quoted 4 lines
cpu/overheads.tex +1 -1
 A fifth hardware optimization is large caches, allowing individual
-CPUs to operate on larger datasets without incuring expensive cache
+CPUs to operate on larger datasets without incurring expensive cache
 misses.

Nice catches!

Indeed!!! ;-)

Quoted 15 lines

cpu/overview.tex where the race always goes to the swiftest. · line 19

Quoted 13 lines
cpu/overheads.tex +0 -0
 Although large caches can degrade energy efficiency and cache-miss
 latency, the ever-growing cache sizes on production microprocessors
cpu/overview.tex +1 -1
index 071cf7c..9e91a7b 100644
@@ -15,7 +15,7 @@ where the race always goes to the swiftest.
 \ContributedBy{Figure}{fig:cpu:CPU Performance at its Best}{Melissa Broussard}
 \end{figure}
 
-Although there are a few CPU-bound benchmarks that approach the ideal
+Although there are a few CPU-bound benchmarks that approach the ideal case
 shown in Figure~\ref{fig:cpu:CPU Performance at its Best},

"ideal" can be used as a noun. I don't think this hunk is necessary.

Hi Akira,

You are right. I never realized this until you helped point this out. I checked my dictionary which says that ideal can be used as a noun and means 'a perfect example of what something should be like'; in this respect, word 'case' is unnecessary. Thank you so much. Happy learning :-)

Quoted 5 lines

This is quite true, but making it a bit less confusing to non-native English speakers is worth something. Not that I am volunteering to confine myself to the 850-word vocabulary of Basic English, mind you! ;-)

So Akira has a good point, but I will take Junchang's patch.

Hi Paul,

Thanks. Then I will explicitly mark this type of patches as suggestions if there are any in the future. It is a great pleasure to help improve the book.

Best Regards,
--Junchang

Quoted 10 lines

Thanx, Paul

Quoted 6 lines

Thanks, Akira

Quoted 3 lines
cpu/overview.tex +0 -0
 the typical program more closely resembles an obstacle course than
 a race track.
#4 lore raw
Quoted 73 lines · Junchang Wang
Quoted 34 lines · Paul E. McKenney
Quoted 32 lines · Akira Yokosawa
Quoted 31 lines · Junchang Wang
Signed-off-by Junchang Wang <[email protected]>

---
Hi Paul,

This is the only patch for Chapter CPU. Please take a look.

Thanks,
--Junchang

--

 cpu/overheads.tex | 4 ++--
 cpu/overview.tex  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
cpu/overheads.tex +1 -1
index 2474cfe..17b120b 100644
@@ -155,7 +155,7 @@ displayed in
 Table~\ref{tab:cpu:Performance of Synchronization Mechanisms on 4-CPU 1.8GHz AMD Opteron 844 System}.
 This system's clock period rounds to 0.6\,ns.
 Although it is not unusual for modern microprocessors to be able to
-retire multiple instructions per clock period, the operations's costs are
+retire multiple instructions per clock period, the operations' costs are
 nevertheless normalized to a clock period in the third column, labeled
 ``Ratio''.
 The first thing to note about this table is the large values of many of

@@ -360,7 +360,7 @@ It is clear that the combination of speculative execution and cloud
 computing needs more than a bit of rework!
Quoted 25 lines
Quoted 6 lines

cpu/overheads.tex It is clear that the combination of speculative execution and cloud · line 364

Quoted 4 lines
cpu/overheads.tex +1 -1
 A fifth hardware optimization is large caches, allowing individual
-CPUs to operate on larger datasets without incuring expensive cache
+CPUs to operate on larger datasets without incurring expensive cache
 misses.

Nice catches!

Indeed!!! ;-)

Quoted 15 lines

cpu/overview.tex where the race always goes to the swiftest. · line 19

Quoted 13 lines
cpu/overheads.tex +0 -0
 Although large caches can degrade energy efficiency and cache-miss
 latency, the ever-growing cache sizes on production microprocessors
cpu/overview.tex +1 -1
index 071cf7c..9e91a7b 100644
@@ -15,7 +15,7 @@ where the race always goes to the swiftest.
 \ContributedBy{Figure}{fig:cpu:CPU Performance at its Best}{Melissa Broussard}
 \end{figure}
 
-Although there are a few CPU-bound benchmarks that approach the ideal
+Although there are a few CPU-bound benchmarks that approach the ideal case
 shown in Figure~\ref{fig:cpu:CPU Performance at its Best},

"ideal" can be used as a noun. I don't think this hunk is necessary.

Hi Akira,

You are right. I never realized this until you helped point this out. I checked my dictionary which says that ideal can be used as a noun and means 'a perfect example of what something should be like'; in this respect, word 'case' is unnecessary. Thank you so much. Happy learning :-)

Quoted 4 lines

This is quite true, but making it a bit less confusing to non-native English speakers is worth something. Not that I am volunteering to confine myself to the 850-word vocabulary of Basic English, mind you! ;-)

Quoted 7 lines
Quoted 1 line

So Akira has a good point, but I will take Junchang's patch.

Hi Paul,

Thanks. Then I will explicitly mark this type of patches as suggestions if there are any in the future. It is a great pleasure to help improve the book.

For my part, I am looking forward to more feedback and patches!

Thanx, Paul

Quoted 15 lines

Best Regards,
--Junchang

Quoted 10 lines

Thanx, Paul

Quoted 6 lines

Thanks, Akira

Quoted 3 lines
cpu/overview.tex +0 -0
 the typical program more closely resembles an obstacle course than
 a race track.
#5 lore raw
In reply to Junchang Wang
Quoted 2 lines · Junchang Wang
Signed-off-by Junchang Wang <[email protected]>

Applied and soon to be pushed, thank you!

Thanx, Paul

Quoted 52 lines

---
Hi Paul,

This is the only patch for Chapter CPU. Please take a look.

Thanks,
--Junchang

--

 cpu/overheads.tex | 4 ++--
 cpu/overview.tex  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
cpu/overheads.tex +2 -2
index 2474cfe..17b120b 100644
@@ -155,7 +155,7 @@ displayed in
 Table~\ref{tab:cpu:Performance of Synchronization Mechanisms on 4-CPU 1.8GHz AMD Opteron 844 System}.
 This system's clock period rounds to 0.6\,ns.
 Although it is not unusual for modern microprocessors to be able to
-retire multiple instructions per clock period, the operations's costs are
+retire multiple instructions per clock period, the operations' costs are
 nevertheless normalized to a clock period in the third column, labeled
 ``Ratio''.
 The first thing to note about this table is the large values of many of

@@ -360,7 +360,7 @@ It is clear that the combination of speculative execution and cloud
 computing needs more than a bit of rework!
 
 A fifth hardware optimization is large caches, allowing individual
-CPUs to operate on larger datasets without incuring expensive cache
+CPUs to operate on larger datasets without incurring expensive cache
 misses.
 Although large caches can degrade energy efficiency and cache-miss
 latency, the ever-growing cache sizes on production microprocessors
cpu/overview.tex +1 -1
index 071cf7c..9e91a7b 100644
@@ -15,7 +15,7 @@ where the race always goes to the swiftest.
 \ContributedBy{Figure}{fig:cpu:CPU Performance at its Best}{Melissa Broussard}
 \end{figure}
 
-Although there are a few CPU-bound benchmarks that approach the ideal
+Although there are a few CPU-bound benchmarks that approach the ideal case
 shown in Figure~\ref{fig:cpu:CPU Performance at its Best},
 the typical program more closely resembles an obstacle course than
 a race track.
Signature · 1 line
2.7.4