openrisc: make function cache_loop() inline
PATCH 1/1 openrisc: make function cache_loop() inline
The third operand of mtspr instruction must be a constraint. To guarantee this condition, function cache_loop() which uses macro mtspr() must be inlined. So let's force it as 'inline'. This is to fix compiling error with new option CONFIG_NO_AUTO_INLINE.
In file included from arch/openrisc/mm/cache.c:17:0:arch/openrisc/mm/cache.c: In function 'cache_loop':arch/openrisc/include/asm/spr.h:20:27: warning: asm operand 0 probably doesn't match constraints
^
arch/openrisc/mm/cache.c:29:3: note: in expansion of macro 'mtspr'
mtspr(reg, line);
^~~~~arch/openrisc/include/asm/spr.h:20:27: error: impossible constraint in 'asm'
--- arch/openrisc/mm/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/openrisc/mm/cache.c +1 -1
@@ -20,7 +20,7 @@#include <asm/cacheflush.h> #include <asm/tlbflush.h> -static void cache_loop (struct page *page,const unsigned int reg) +static inline void cache_loop (struct page *page,const unsigned int reg) {unsigned long paddr =page_to_pfn (page) <<PAGE_SHIFT ;unsigned long line = paddr & ~(L1_CACHE_BYTES -1 );
Signature · 1 line
2.17.1
Quoted 4 lines · Changbin Du
The third operand of mtspr instruction must be a constraint. To guarantee this condition, function
cache_loop()which uses macromtspr()must be inlined. So let's force it as 'inline'. This is to fix compiling error with new optionCONFIG_NO_AUTO_INLINE.
Thanks for looking at this.
Do you mean, must be a 'constant'?
I think this fix is fine for now. Can you add it to your 'kernel hacking: GCC optimization for better debug experience' series?
Quoted 7 lines
In file included from
arch/openrisc/mm/cache.c:17:0:arch/openrisc/mm/cache.c: In function 'cache_loop':arch/openrisc/include/asm/spr.h:20:27: warning: asm operand 0 probably doesn't match constraints^ arch/openrisc/mm/cache.c:29:3: note: in expansion of macro 'mtspr' mtspr(reg, line); ^~~~~
Quoted 6 lines
arch/openrisc/include/asm/spr.h:20:27: error: impossible constraint in 'asm'Signed-off-by Changbin Du <[email protected]>Reported-by kbuild test robot <[email protected]>Cc Stafford Horne <[email protected]>Cc Masahiro Yamada <[email protected]>
Quoted 20 lines
--- arch/openrisc/mm/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/openrisc/mm/cache.c +1
-1@@ -20,7 +20,7 @@#include <asm/cacheflush.h> #include <asm/tlbflush.h> -static void cache_loop (struct page *page,const unsigned int reg) +static inline void cache_loop (struct page *page,const unsigned int reg) {unsigned long paddr =page_to_pfn (page) <<PAGE_SHIFT ;unsigned long line = paddr & ~(L1_CACHE_BYTES -1 );Signature · 1 line
2.17.1
Quoted 10 lines · Stafford Horne
Quoted 4 lines · Changbin Du
The third operand of mtspr instruction must be a constraint. To guarantee this condition, function
cache_loop()which uses macromtspr()must be inlined. So let's force it as 'inline'. This is to fix compiling error with new optionCONFIG_NO_AUTO_INLINE.Thanks for looking at this.
Do you mean, must be a 'constant'?
yes, it is 'constant'. sorry for the misstake.
Quoted 3 lines
I think this fix is fine for now. Can you add it to your 'kernel hacking: GCC optimization for better debug experience' series?
hi Yamada, could you add this patch to your kbuild tree? thanks!
Quoted 36 lines
Quoted 7 lines
In file included from
arch/openrisc/mm/cache.c:17:0:arch/openrisc/mm/cache.c: In function 'cache_loop':arch/openrisc/include/asm/spr.h:20:27: warning: asm operand 0 probably doesn't match constraints^ arch/openrisc/mm/cache.c:29:3: note: in expansion of macro 'mtspr' mtspr(reg, line); ^~~~~Quoted 6 lines
arch/openrisc/include/asm/spr.h:20:27: error: impossible constraint in 'asm'Signed-off-by Changbin Du <[email protected]>Reported-by kbuild test robot <[email protected]>Cc Stafford Horne <[email protected]>Cc Masahiro Yamada <[email protected]>Acked-by Stafford Horne <[email protected]>Quoted 20 lines
--- arch/openrisc/mm/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/openrisc/mm/cache.c +1
-1@@ -20,7 +20,7 @@#include <asm/cacheflush.h> #include <asm/tlbflush.h> -static void cache_loop (struct page *page,const unsigned int reg) +static inline void cache_loop (struct page *page,const unsigned int reg) {unsigned long paddr =page_to_pfn (page) <<PAGE_SHIFT ;unsigned long line = paddr & ~(L1_CACHE_BYTES -1 );Signature · 1 line
2.17.1
Signature · 2 lines
Thanks, Changbin Du