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spi: npcm: add NPCM Peripheral SPI driver

PATCH In review Tomer Maimon 2 participants 4 messages Nov 12, 2018 – Nov 13, 2018

Subsystems (3)
Device tree bindings SPI Arm/nuvoton npcm architecture
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Tomer Maimon

author maintainer
#0 lore raw

cover spi: npcm: add NPCM Peripheral SPI driver

This patch set adds Peripheral SPI (PSPI) support for the Nuvoton NPCM Baseboard Management Controller (BMC).

The NPCM PSPI operates in master mode.

The NPCM750/730/715/710 supports up to two PSPI devices.

The NPCM PSPI driver tested on NPCM750 evaluation board.

Tomer Maimon (2):
dt-binding: spi: add NPCM PSPI controller documentation
spi: npcm: add NPCM PSPI controller driver

 .../devicetree/bindings/spi/nuvoton,npcm-pspi.txt  |  35 ++
 drivers/spi/Kconfig                                |   7 +
 drivers/spi/Makefile                               |   1 +
 drivers/spi/spi-npcm-pspi.c                        | 480 +++++++++++++++++++++
 4 files changed, 523 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
 create mode 100644 drivers/spi/spi-npcm-pspi.c
Signature · 1 line
2.14.1
author maintainer
#1 lore raw

PATCH 1/2 dt-binding: spi: add NPCM PSPI controller documentation

Added device tree binding documentation for Nuvoton BMC NPCM Peripheral SPI controller.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../devicetree/bindings/spi/nuvoton,npcm-pspi.txt  | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt new file +35 -0
new file mode 100644
index 000000000000..99606b22e5c2
@@ -0,0 +1,35 @@
+Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
+
+Nuvoton NPCM7xx SOC support two PSPI channels.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
+ - #address-cells : should be 1. see spi-bus.txt
+ - #size-cells : should be 0. see spi-bus.txt
+ - specifies physical base address and size of the register.
+ - interrupts : contain PSPI interrupt.
+ - clocks : phandle of PSPI reference clock.
+ - clock-names: Should be "clk_apb5".
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+ - cs-gpios: Specifies the gpio pins to be used for chipselects.
+            See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- clock-frequency : Input clock frequency to the PSPI block in Hz.
+		    Default is 25000000 Hz.
+
+Example:
+
+spi0: spi@f0200000 {
+	compatible = "nuvoton,npcm750-pspi";
+	reg = <0xf0200000 0x1000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pspi1_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clk NPCM7XX_CLK_APB5>;
+	clock-names = "clk_apb5";
+	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+};
Signature · 1 line
2.14.1
maintainer
#2 lore raw

Applied "dt-binding: spi: add NPCM PSPI controller documentation" to the spi tree

The patch

dt-binding: spi: add NPCM PSPI controller documentation

has been applied to the spi tree at

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From 4ad26864df53b265976c4a3ae61b1e6cad92fe40 Mon Sep 17 00:00:00 2001

From: Tomer Maimon <[email protected]>
Date: Mon, 12 Nov 2018 18:42:31 +0200
Subject: [PATCH] dt-binding: spi: add NPCM PSPI controller documentation

Added device tree binding documentation for Nuvoton BMC NPCM Peripheral SPI controller.

Signed-off-by Tomer Maimon <[email protected]>
Signed-off-by Mark Brown <[email protected]>
---
 .../bindings/spi/nuvoton,npcm-pspi.txt        | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt new file +35 -0
new file mode 100644
index 000000000000..99606b22e5c2
@@ -0,0 +1,35 @@
+Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
+
+Nuvoton NPCM7xx SOC support two PSPI channels.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
+ - #address-cells : should be 1. see spi-bus.txt
+ - #size-cells : should be 0. see spi-bus.txt
+ - specifies physical base address and size of the register.
+ - interrupts : contain PSPI interrupt.
+ - clocks : phandle of PSPI reference clock.
+ - clock-names: Should be "clk_apb5".
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+ - cs-gpios: Specifies the gpio pins to be used for chipselects.
+            See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- clock-frequency : Input clock frequency to the PSPI block in Hz.
+		    Default is 25000000 Hz.
+
+Example:
+
+spi0: spi@f0200000 {
+	compatible = "nuvoton,npcm750-pspi";
+	reg = <0xf0200000 0x1000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pspi1_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clk NPCM7XX_CLK_APB5>;
+	clock-names = "clk_apb5";
+	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+};
Signature · 1 line
2.19.1
author maintainer
#3 lore raw

PATCH 2/2 spi: npcm: add NPCM PSPI controller driver

In reply to Tomer Maimon

Add Nuvoton NPCM BMC Peripheral SPI controller driver.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/spi/Kconfig         |   7 +
 drivers/spi/Makefile        |   1 +
 drivers/spi/spi-npcm-pspi.c | 480 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 488 insertions(+)
 create mode 100644 drivers/spi/spi-npcm-pspi.c
drivers/spi/Kconfig +7 -0
index 7d3a5c94727e..21eb08405127 100644
@@ -397,6 +397,13 @@ config SPI_MT65XX
 	  say Y or M here.If you are not sure, say N.
 	  SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
 
+config SPI_NPCM_PSPI
+	tristate "Nuvoton NPCM PSPI Controller"
+	depends on ARCH_NPCM || COMPILE_TEST
+	help
+	  This driver provides support for Nuvoton NPCM BMC
+	  Peripheral SPI controller in master mode.
+
 config SPI_NUC900
 	tristate "Nuvoton NUC900 series SPI"
 	depends on ARCH_W90X900
drivers/spi/Makefile +1 -0
index 3575205c5c27..d40a3611809c 100644
@@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC)		+= spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52xx.o
 obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
+obj-$(CONFIG_SPI_NPCM_PSPI)		+= spi-npcm-pspi.o
 obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
 spi-octeon-objs				:= spi-cavium.o spi-cavium-octeon.o
drivers/spi/spi-npcm-pspi.c new file +480 -0

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Signature · 1 line
2.14.1