mkwrite_device_info removal

From: Tvrtko Ursulin <[email protected]>

It is only initialized to zero once so does not need an explicit initializer.

Signed-off-by Tvrtko Ursulin <[email protected]>

Cc Chris Wilson <[email protected]>

Cc Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

drivers/gpu/drm/i915/i915_pci.c +0 -0

index 4ccab8372dd4..e6e7fcdf0ab7 100644

From: Tvrtko Ursulin <[email protected]>

Idea of runtime device info is to contain all fields from the existing device info which are modified at runtime.

Initially we move there fields which are never set from the static tables ie.: num_rings, num_sprites, num_scalers,

cs_timestamp_frequency_khz, sseu and has_pooled_eu.

Signed-off-by Tvrtko Ursulin <[email protected]>

Cc Chris Wilson <[email protected]>

Cc Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_debugfs.c           | 27 +++---
 drivers/gpu/drm/i915/i915_drv.c               | 17 ++--
 drivers/gpu/drm/i915/i915_drv.h               |  3 +-
 drivers/gpu/drm/i915/i915_gpu_error.c         | 19 +++--
 drivers/gpu/drm/i915/i915_gpu_error.h         |  1 +
 drivers/gpu/drm/i915/i915_perf.c              |  5 +-
 drivers/gpu/drm/i915/i915_query.c             |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c      | 82 +++++++++++--------
 drivers/gpu/drm/i915/intel_device_info.h      | 42 ++++++----
 drivers/gpu/drm/i915/intel_display.c          |  2 +-
 drivers/gpu/drm/i915/intel_display.h          |  6 +-
 drivers/gpu/drm/i915/intel_engine_cs.c        |  4 +-
 drivers/gpu/drm/i915/intel_lrc.c              | 14 ++--
 drivers/gpu/drm/i915/intel_pm.c               |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c       |  4 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h       |  4 +-
 drivers/gpu/drm/i915/intel_workarounds.c      |  6 +-
 .../gpu/drm/i915/selftests/i915_gem_context.c |  6 +-
 drivers/gpu/drm/i915/selftests/intel_lrc.c    |  4 +-
 19 files changed, 144 insertions(+), 106 deletions(-)

drivers/gpu/drm/i915/i915_debugfs.c +13 -14

index 670db5073d70..1b8a3f203b92 100644
@@ -48,7 +48,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
 	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
 
 	intel_device_info_dump_flags(info, &p);
-	intel_device_info_dump_runtime(info, &p);
+	intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
 	intel_driver_caps_print(&dev_priv->caps, &p);
 
 	kernel_param_lock(THIS_MODULE);

@@ -3289,7 +3289,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
 	seq_printf(m, "Global active requests: %d\n",
 		   dev_priv->gt.active_requests);
 	seq_printf(m, "CS timestamp frequency: %u kHz\n",
-		   dev_priv->info.cs_timestamp_frequency_khz);
+		   dev_priv->runtime_info.cs_timestamp_frequency_khz);
 
 	p = drm_seq_file_printer(m);
 	for_each_engine(engine, dev_priv, id)

@@ -3305,7 +3305,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct drm_printer p = drm_seq_file_printer(m);
 
-	intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
+	intel_device_info_dump_topology(&dev_priv->runtime_info.sseu, &p);
 
 	return 0;
 }

@@ -4341,7 +4341,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 				     struct sseu_dev_info *sseu)
 {
 #define SS_MAX 6
-	const struct intel_device_info *info = INTEL_INFO(dev_priv);
+	const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
 	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
 	int s, ss;
 

@@ -4397,7 +4397,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 				    struct sseu_dev_info *sseu)
 {
 #define SS_MAX 3
-	const struct intel_device_info *info = INTEL_INFO(dev_priv);
+	const struct intel_runtime_device_info *info = &dev_priv->runtime_info;
 	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
 	int s, ss;
 

@@ -4424,8 +4424,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 		sseu->slice_mask |= BIT(s);
 
 		if (IS_GEN9_BC(dev_priv))
-			sseu->subslice_mask[s] =
-				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+			sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;

@@ -4459,10 +4458,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
 
 	if (sseu->slice_mask) {
 		sseu->eu_per_subslice =
-				INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+			dev_priv->runtime_info.sseu.eu_per_subslice;
 		for (s = 0; s < fls(sseu->slice_mask); s++) {
 			sseu->subslice_mask[s] =
-				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+				dev_priv->runtime_info.sseu.subslice_mask[s];
 		}
 		sseu->eu_total = sseu->eu_per_subslice *
 				 sseu_subslice_total(sseu);

@@ -4470,7 +4469,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
 		/* subtract fused off EU(s) from enabled slice(s) */
 		for (s = 0; s < fls(sseu->slice_mask); s++) {
 			u8 subslice_7eu =
-				INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
+				dev_priv->runtime_info.sseu.subslice_7eu[s];
 
 			sseu->eu_total -= hweight8(subslice_7eu);
 		}

@@ -4523,14 +4522,14 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 		return -ENODEV;
 
 	seq_puts(m, "SSEU Device Info\n");
-	i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
+	i915_print_sseu_info(m, true, &dev_priv->runtime_info.sseu);
 
 	seq_puts(m, "SSEU Device Status\n");
 	memset(&sseu, 0, sizeof(sseu));
-	sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices;
-	sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices;
+	sseu.max_slices = dev_priv->runtime_info.sseu.max_slices;
+	sseu.max_subslices = dev_priv->runtime_info.sseu.max_subslices;
 	sseu.max_eus_per_subslice =
-		INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
+		dev_priv->runtime_info.sseu.max_eus_per_subslice;
 
 	intel_runtime_pm_get(dev_priv);
 

drivers/gpu/drm/i915/i915_drv.c +9 -8

index b1d23c73c147..9cfd5b145248 100644
@@ -357,12 +357,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = i915_cmd_parser_get_version(dev_priv);
 		break;
 	case I915_PARAM_SUBSLICE_TOTAL:
-		value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
+		value = sseu_subslice_total(&dev_priv->runtime_info.sseu);
 		if (!value)
 			return -ENODEV;
 		break;
 	case I915_PARAM_EU_TOTAL:
-		value = INTEL_INFO(dev_priv)->sseu.eu_total;
+		value = dev_priv->runtime_info.sseu.eu_total;
 		if (!value)
 			return -ENODEV;
 		break;

@@ -379,7 +379,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_POOLED_EU(dev_priv);
 		break;
 	case I915_PARAM_MIN_EU_IN_POOL:
-		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
+		value = dev_priv->runtime_info.sseu.min_eu_in_pool;
 		break;
 	case I915_PARAM_HUC_STATUS:
 		value = intel_huc_check_status(&dev_priv->huc);

@@ -429,17 +429,18 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = intel_engines_has_context_isolation(dev_priv);
 		break;
 	case I915_PARAM_SLICE_MASK:
-		value = INTEL_INFO(dev_priv)->sseu.slice_mask;
+		value = dev_priv->runtime_info.sseu.slice_mask;
 		if (!value)
 			return -ENODEV;
 		break;
 	case I915_PARAM_SUBSLICE_MASK:
-		value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
+		value = dev_priv->runtime_info.sseu.subslice_mask[0];
 		if (!value)
 			return -ENODEV;
 		break;
 	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
-		value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
+		value = 1000 *
+			dev_priv->runtime_info.cs_timestamp_frequency_khz;
 		break;
 	case I915_PARAM_MMAP_GTT_COHERENT:
 		value = INTEL_INFO(dev_priv)->has_coherent_ggtt;

@@ -1372,7 +1373,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	if (i915_inject_load_failure())
 		return -ENODEV;
 
-	intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
+	intel_device_info_runtime_init(dev_priv);
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&

@@ -1620,7 +1621,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 		struct drm_printer p = drm_debug_printer("i915 device info:");
 
 		intel_device_info_dump(&dev_priv->info, &p);
-		intel_device_info_dump_runtime(&dev_priv->info, &p);
+		intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
 	}
 
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))

drivers/gpu/drm/i915/i915_drv.h +2 -1

index 08d25aa480f7..f677a9936d33 100644
@@ -1589,6 +1589,7 @@ struct drm_i915_private {
 	struct kmem_cache *priorities;
 
 	const struct intel_device_info info;
+	struct intel_runtime_device_info runtime_info;
 	struct intel_driver_caps caps;
 
 	/**

@@ -2663,7 +2664,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission()
 #define USES_HUC(dev_priv)		intel_uc_is_using_huc()
 
-#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv)	((dev_priv)->runtime_info.has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff80
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00

drivers/gpu/drm/i915/i915_gpu_error.c +14 -5

index c8d8f79688a8..3e872bb1f00a 100644
@@ -589,15 +589,18 @@ static void print_error_obj(struct drm_i915_error_state_buf *m,
 	err_puts(m, "\n");
 }
 
-static void err_print_capabilities(struct drm_i915_error_state_buf *m,
-				   const struct intel_device_info *info,
-				   const struct intel_driver_caps *caps)
+static void
+err_print_capabilities(struct drm_i915_error_state_buf *m,
+		       const struct intel_device_info *info,
+		       const struct intel_runtime_device_info *runtime_info,
+		       const struct intel_driver_caps *caps)
 {
 	struct drm_printer p = i915_error_printer(m);
 
 	intel_device_info_dump_flags(info, &p);
+	intel_device_info_dump_runtime(runtime_info, &p);
 	intel_driver_caps_print(caps, &p);
-	intel_device_info_dump_topology(&info->sseu, &p);
+	intel_device_info_dump_topology(&runtime_info->sseu, &p);
 }
 
 static void err_print_params(struct drm_i915_error_state_buf *m,

@@ -829,7 +832,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	if (error->display)
 		intel_display_print_error_state(m, error->display);
 
-	err_print_capabilities(m, &error->device_info, &error->driver_caps);
+	err_print_capabilities(m,
+			       &error->device_info,
+			       &error->runtime_device_info,
+			       &error->driver_caps);
 	err_print_params(m, &error->params);
 	err_print_uc(m, &error->uc);
 

@@ -1751,6 +1757,9 @@ static void capture_gen_state(struct i915_gpu_state *error)
 	memcpy(&error->device_info,
 	       INTEL_INFO(i915),
 	       sizeof(error->device_info));
+	memcpy(&error->runtime_device_info,
+	       &i915->runtime_info,
+	       sizeof(error->runtime_device_info));
 	error->driver_caps = i915->caps;
 }
 

drivers/gpu/drm/i915/i915_gpu_error.h +1 -0

index 8710fb18ed74..ede9aa5ae1a2 100644
@@ -45,6 +45,7 @@ struct i915_gpu_state {
 	u32 reset_count;
 	u32 suspend_count;
 	struct intel_device_info device_info;
+	struct intel_runtime_device_info runtime_device_info;
 	struct intel_driver_caps driver_caps;
 	struct i915_params params;
 

drivers/gpu/drm/i915/i915_perf.c +3 -2

index 2c2b63be7a6c..9054237251c3 100644
@@ -2646,7 +2646,8 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
 static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
 {
 	return div64_u64(1000000000ULL * (2ULL << exponent),
-			 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
+			 1000ULL *
+			 dev_priv->runtime_info.cs_timestamp_frequency_khz);
 }
 
 static int

@@ -3505,7 +3506,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
 		spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
 
 		oa_sample_rate_hard_limit = 1000 *
-			(INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
+			(dev_priv->runtime_info.cs_timestamp_frequency_khz / 2);
 		dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
 
 		mutex_init(&dev_priv->perf.metrics_lock);

drivers/gpu/drm/i915/i915_query.c +1 -1

index 6fc4b8eeab42..6b2c6e6873d3 100644
@@ -13,7 +13,7 @@
 static int query_topology_info(struct drm_i915_private *dev_priv,
 			       struct drm_i915_query_item *query_item)
 {
-	const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+	const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
 

drivers/gpu/drm/i915/intel_device_info.c +49 -33

index 89ed3a84a4fa..8385767aaf08 100644
@@ -79,6 +79,15 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
 #undef PRINT_FLAG
 }
 
+void
+intel_runtime_device_info_dump_flags(const struct intel_runtime_device_info *info,
+				     struct drm_printer *p)
+{
+#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
+	DEV_RUNTIME_INFO_FOR_EACH_FLAG(PRINT_FLAG);
+#undef PRINT_FLAG
+}
+
 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 {
 	int s;

@@ -100,13 +109,16 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 	drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
 }
 
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
-				    struct drm_printer *p)
+void
+intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
+			       struct drm_printer *p)
 {
 	sseu_dump(&info->sseu, p);
 
 	drm_printf(p, "CS timestamp frequency: %u kHz\n",
 		   info->cs_timestamp_frequency_khz);
+
+	intel_runtime_device_info_dump_flags(info, p);
 }
 
 void intel_device_info_dump(const struct intel_device_info *info,

@@ -160,7 +172,7 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 
 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
 {
-	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	u8 s_en;
 	u32 ss_en, ss_en_mask;
 	u8 eu_en;

@@ -199,7 +211,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
 
 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 {
-	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	const u32 fuse2 = I915_READ(GEN8_FUSE2);
 	int s, ss;
 	const int eu_mask = 0xff;

@@ -276,7 +288,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
-	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	u32 fuse;
 
 	fuse = I915_READ(CHV_FUSE_GT);

@@ -329,7 +341,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 
 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 {
-	struct intel_device_info *info = mkwrite_device_info(dev_priv);
+	struct intel_runtime_device_info *info = &dev_priv->runtime_info;
 	struct sseu_dev_info *sseu = &info->sseu;
 	int s, ss;
 	u32 fuse2, eu_disable, subslice_mask;

@@ -433,7 +445,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 
 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 {
-	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	int s, ss;
 	u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
 

@@ -515,8 +527,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 
 static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
 {
-	struct intel_device_info *info = mkwrite_device_info(dev_priv);
-	struct sseu_dev_info *sseu = &info->sseu;
+	struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	u32 fuse1;
 	int s, ss;
 

@@ -524,9 +535,9 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
 	 * There isn't a register to tell us how many slices/subslices. We
 	 * work off the PCI-ids here.
 	 */
-	switch (info->gt) {
+	switch (INTEL_INFO(dev_priv)->gt) {
 	default:
-		MISSING_CASE(info->gt);
+		MISSING_CASE(INTEL_INFO(dev_priv)->gt);
 		/* fall through */
 	case 1:
 		sseu->slice_mask = BIT(0);

@@ -735,29 +746,30 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
  *   - after the PCH has been detected,
  *   - before the first usage of the fields it can tweak.
  */
-void intel_device_info_runtime_init(struct intel_device_info *info)
+void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv =
-		container_of(info, struct drm_i915_private, info);
+	struct intel_device_info *info = mkwrite_device_info(dev_priv);
+	struct intel_runtime_device_info *runtime_info =
+		&dev_priv->runtime_info;
 	enum pipe pipe;
 
 	if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
-			info->num_scalers[pipe] = 2;
+			runtime_info->num_scalers[pipe] = 2;
 	} else if (IS_GEN9(dev_priv)) {
-		info->num_scalers[PIPE_A] = 2;
-		info->num_scalers[PIPE_B] = 2;
-		info->num_scalers[PIPE_C] = 1;
+		runtime_info->num_scalers[PIPE_A] = 2;
+		runtime_info->num_scalers[PIPE_B] = 2;
+		runtime_info->num_scalers[PIPE_C] = 1;
 	}
 
 	BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
 
 	if (IS_GEN11(dev_priv))
 		for_each_pipe(dev_priv, pipe)
-			info->num_sprites[pipe] = 6;
+			runtime_info->num_sprites[pipe] = 6;
 	else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
 		for_each_pipe(dev_priv, pipe)
-			info->num_sprites[pipe] = 3;
+			runtime_info->num_sprites[pipe] = 3;
 	else if (IS_BROXTON(dev_priv)) {
 		/*
 		 * Skylake and Broxton currently don't expose the topmost plane as its

@@ -768,15 +780,15 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		 * down the line.
 		 */
 
-		info->num_sprites[PIPE_A] = 2;
-		info->num_sprites[PIPE_B] = 2;
-		info->num_sprites[PIPE_C] = 1;
+		runtime_info->num_sprites[PIPE_A] = 2;
+		runtime_info->num_sprites[PIPE_B] = 2;
+		runtime_info->num_sprites[PIPE_C] = 1;
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
-			info->num_sprites[pipe] = 2;
+			runtime_info->num_sprites[pipe] = 2;
 	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
-			info->num_sprites[pipe] = 1;
+			runtime_info->num_sprites[pipe] = 1;
 	}
 
 	if (i915_modparams.disable_display) {

@@ -860,7 +872,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	}
 
 	/* Initialize command stream timestamp frequency */
-	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
+	runtime_info->cs_timestamp_frequency_khz =
+		read_timestamp_frequency(dev_priv);
 }
 
 void intel_driver_caps_print(const struct intel_driver_caps *caps,

@@ -880,6 +893,8 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
 {
 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
+	struct intel_runtime_device_info *runtime_info =
+		&dev_priv->runtime_info;
 	u32 media_fuse;
 	unsigned int i;
 

@@ -888,27 +903,28 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
 
 	media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
 
-	info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
-	info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
-			     GEN11_GT_VEBOX_DISABLE_SHIFT;
+	runtime_info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+	runtime_info->vebox_enable =
+		(media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+		GEN11_GT_VEBOX_DISABLE_SHIFT;
 
-	DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable);
+	DRM_DEBUG_DRIVER("vdbox enable: %04x\n", runtime_info->vdbox_enable);
 	for (i = 0; i < I915_MAX_VCS; i++) {
 		if (!HAS_ENGINE(dev_priv, _VCS(i)))
 			continue;
 
-		if (!(BIT(i) & info->vdbox_enable)) {
+		if (!(BIT(i) & runtime_info->vdbox_enable)) {
 			info->ring_mask &= ~ENGINE_MASK(_VCS(i));
 			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
 		}
 	}
 
-	DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
+	DRM_DEBUG_DRIVER("vebox enable: %04x\n", runtime_info->vebox_enable);
 	for (i = 0; i < I915_MAX_VECS; i++) {
 		if (!HAS_ENGINE(dev_priv, _VECS(i)))
 			continue;
 
-		if (!(BIT(i) & info->vebox_enable)) {
+		if (!(BIT(i) & runtime_info->vebox_enable)) {
 			info->ring_mask &= ~ENGINE_MASK(_VECS(i));
 			DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
 		}

drivers/gpu/drm/i915/intel_device_info.h +26 -16

index 88f97210dc49..83e19ac8e401 100644
@@ -105,7 +105,6 @@ enum intel_ppgtt {
 	func(has_logical_ring_elsq); \
 	func(has_logical_ring_preemption); \
 	func(has_overlay); \
-	func(has_pooled_eu); \
 	func(has_psr); \
 	func(has_rc6); \
 	func(has_rc6p); \

@@ -154,8 +153,8 @@ struct intel_device_info {
 
 	u8 gen;
 	u8 gt; /* GT number, 0 if undefined */
-	u8 num_rings;
 	intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+	u8 num_pipes;
 
 	enum intel_platform platform;
 	u32 platform_mask;

@@ -165,10 +164,6 @@ struct intel_device_info {
 
 	u32 display_mmio_offset;
 
-	u8 num_pipes;
-	u8 num_sprites[I915_MAX_PIPES];
-	u8 num_scalers[I915_MAX_PIPES];
-
 #define DEFINE_FLAG(name) u8 name:1
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG

@@ -179,19 +174,33 @@ struct intel_device_info {
 	int trans_offsets[I915_MAX_TRANSCODERS];
 	int cursor_offsets[I915_MAX_PIPES];
 
-	/* Slice/subslice/EU info */
-	struct sseu_dev_info sseu;
+	struct color_luts {
+		u16 degamma_lut_size;
+		u16 gamma_lut_size;
+	} color;
+};
 
-	u32 cs_timestamp_frequency_khz;
+#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
+	func(has_pooled_eu); \
+
+struct intel_runtime_device_info {
+	unsigned int num_rings;
+
+	u8 num_sprites[I915_MAX_PIPES];
+	u8 num_scalers[I915_MAX_PIPES];
 
 	/* Enabled (not fused off) media engine bitmasks. */
 	u8 vdbox_enable;
 	u8 vebox_enable;
 
-	struct color_luts {
-		u16 degamma_lut_size;
-		u16 gamma_lut_size;
-	} color;
+	u32 cs_timestamp_frequency_khz;
+
+	/* Slice/subslice/EU info */
+	struct sseu_dev_info sseu;
+
+#define DEFINE_FLAG(name) u8 name:1
+	DEV_RUNTIME_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
 };
 
 struct intel_driver_caps {

@@ -248,13 +257,14 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
 
 const char *intel_platform_name(enum intel_platform platform);
 
-void intel_device_info_runtime_init(struct intel_device_info *info);
+void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 void intel_device_info_dump(const struct intel_device_info *info,
 			    struct drm_printer *p);
 void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);
-void intel_device_info_dump_runtime(const struct intel_device_info *info,
-				    struct drm_printer *p);
+void
+intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
+			       struct drm_printer *p);
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
 				     struct drm_printer *p);
 

drivers/gpu/drm/i915/intel_display.c +1 -1

index a7fa032310ae..cc30bf1172ad 100644
@@ -13892,7 +13892,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i;
 
-	crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
+	crtc->num_scalers = dev_priv->runtime_info.num_scalers[crtc->pipe];
 	if (!crtc->num_scalers)
 		return;
 

drivers/gpu/drm/i915/intel_display.h +3 -3

index 5d50decbcbb5..607ddc4a0b11 100644
@@ -105,7 +105,7 @@ enum i9xx_plane_id {
 };
 
 #define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * dev_priv->runtime_info.num_sprites[(p)] + (s) + 'A')
 
 /*
  * Per-pipe plane identifier.

@@ -294,12 +294,12 @@ struct intel_link_m_n {
 
 #define for_each_universal_plane(__dev_priv, __pipe, __p)		\
 	for ((__p) = 0;							\
-	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
+	     (__p) < (__dev_priv)->runtime_info.num_sprites[(__pipe)] + 1;\
 	     (__p)++)
 
 #define for_each_sprite(__dev_priv, __p, __s)				\
 	for ((__s) = 0;							\
-	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
+	     (__s) < (__dev_priv)->runtime_info.num_sprites[(__p)];	\
 	     (__s)++)
 
 #define for_each_port_masked(__port, __ports_mask) \

drivers/gpu/drm/i915/intel_engine_cs.c +2 -2

index bc147d9e6c92..b464ee0afb85 100644
@@ -365,7 +365,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
 		goto cleanup;
 	}
 
-	device_info->num_rings = hweight32(mask);
+	dev_priv->runtime_info.num_rings = hweight32(mask);
 
 	i915_check_and_clear_faults(dev_priv);
 

@@ -807,7 +807,7 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 
 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
 {
-	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+	const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	u32 mcr_s_ss_select;
 	u32 slice = fls(sseu->slice_mask);
 	u32 subslice = fls(sseu->subslice_mask[slice]);

drivers/gpu/drm/i915/intel_lrc.c +7 -7

index 08fd9b12e4d7..cc897f429635 100644
@@ -2343,9 +2343,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
 static u32
 make_rpcs(struct drm_i915_private *dev_priv)
 {
-	bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
-	u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
-	u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
+	bool subslice_pg = dev_priv->runtime_info.sseu.has_subslice_pg;
+	u8 slices = hweight8(dev_priv->runtime_info.sseu.slice_mask);
+	u8 subslices = hweight8(dev_priv->runtime_info.sseu.subslice_mask[0]);
 	u32 rpcs = 0;
 
 	/*

@@ -2393,7 +2393,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
 	 * must make an explicit request through RPCS for full
 	 * enablement.
 	*/
-	if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+	if (dev_priv->runtime_info.sseu.has_slice_pg) {
 		u32 mask, val = slices;
 
 		if (INTEL_GEN(dev_priv) >= 11) {

@@ -2421,17 +2421,17 @@ make_rpcs(struct drm_i915_private *dev_priv)
 		rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
 	}
 
-	if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
+	if (dev_priv->runtime_info.sseu.has_eu_pg) {
 		u32 val;
 
-		val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
+		val = dev_priv->runtime_info.sseu.eu_per_subslice <<
 		      GEN8_RPCS_EU_MIN_SHIFT;
 		GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
 		val &= GEN8_RPCS_EU_MIN_MASK;
 
 		rpcs |= val;
 
-		val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
+		val = dev_priv->runtime_info.sseu.eu_per_subslice <<
 		      GEN8_RPCS_EU_MAX_SHIFT;
 		GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
 		val &= GEN8_RPCS_EU_MAX_MASK;

drivers/gpu/drm/i915/intel_pm.c +1 -1

index 5df7f6e1ab5e..17270d8f1880 100644
@@ -7341,7 +7341,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
 
 	val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
 
-	switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
+	switch (dev_priv->runtime_info.sseu.eu_total) {
 	case 8:
 		/* (2 * 4) config */
 		rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);

drivers/gpu/drm/i915/intel_ringbuffer.c +2 -2

index 87eebc13c0d8..fccebf773461 100644
@@ -1566,7 +1566,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 	const int num_rings =
 		/* Use an extended w/a on gen7 if signalling from other rings */
 		(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
-		INTEL_INFO(i915)->num_rings - 1 :
+		i915->runtime_info.num_rings - 1 :
 		0;
 	bool force_restore = false;
 	int len;

@@ -2231,7 +2231,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 
 		engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
 
-		num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
+		num_rings = dev_priv->runtime_info.num_rings - 1;
 		engine->emit_breadcrumb_sz += num_rings * 3;
 		if (num_rings & 1)
 			engine->emit_breadcrumb_sz++;

drivers/gpu/drm/i915/intel_ringbuffer.h +2 -2

index 8a2270b209b0..db2933d287b8 100644
@@ -94,11 +94,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
 
 #define instdone_slice_mask(dev_priv__) \
 	(IS_GEN7(dev_priv__) ? \
-	 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
+	 1 : (dev_priv__)->runtime_info.sseu.slice_mask)
 
 #define instdone_subslice_mask(dev_priv__) \
 	(IS_GEN7(dev_priv__) ? \
-	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
+	 1 : (dev_priv__)->runtime_info.sseu.subslice_mask[0])
 
 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
 	for ((slice__) = 0, (subslice__) = 0; \

drivers/gpu/drm/i915/intel_workarounds.c +3 -3

index d7176213e3ce..110556d0934f 100644
@@ -318,7 +318,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
 		 * Only consider slices where one, and only one, subslice has 7
 		 * EUs
 		 */
-		if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
+		if (!is_power_of_2(dev_priv->runtime_info.sseu.subslice_7eu[i]))
 			continue;
 
 		/*

@@ -327,7 +327,7 @@ static int skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
 		 *
 		 * ->    0 <= ss <= 3;
 		 */
-		ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
+		ss = ffs(dev_priv->runtime_info.sseu.subslice_7eu[i]) - 1;
 		vals[i] = 3 - ss;
 	}
 

@@ -732,7 +732,7 @@ static void cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
-	const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+	const struct sseu_dev_info *sseu = &dev_priv->runtime_info.sseu;
 	u32 mcr;
 	u32 mcr_slice_subslice_mask;
 

drivers/gpu/drm/i915/selftests/i915_gem_context.c +3 -3

index 7d82043aff10..4ee3fcff815a 100644
@@ -627,7 +627,7 @@ static int igt_ctx_exec(void *arg)
 		ncontexts++;
 	}
 	pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
-		ncontexts, INTEL_INFO(i915)->num_rings, ndwords);
+		ncontexts, i915->runtime_info.num_rings, ndwords);
 
 	dw = 0;
 	list_for_each_entry(obj, &objects, st_link) {

@@ -732,7 +732,7 @@ static int igt_ctx_readonly(void *arg)
 		}
 	}
 	pr_info("Submitted %lu dwords (across %u engines)\n",
-		ndwords, INTEL_INFO(i915)->num_rings);
+		ndwords, i915->runtime_info.num_rings);
 
 	dw = 0;
 	list_for_each_entry(obj, &objects, st_link) {

@@ -1064,7 +1064,7 @@ static int igt_vm_isolation(void *arg)
 		count += this;
 	}
 	pr_info("Checked %lu scratch offsets across %d engines\n",
-		count, INTEL_INFO(i915)->num_rings);
+		count, i915->runtime_info.num_rings);
 
 out_rpm:
 	intel_runtime_pm_put(i915);

drivers/gpu/drm/i915/selftests/intel_lrc.c +2 -2

index 94fc0e5c8766..7237a2474805 100644
@@ -719,7 +719,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
 
 	pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
 		count, flags,
-		INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
+		smoke->i915->runtime_info.num_rings, smoke->ncontext);
 	return 0;
 }
 

@@ -747,7 +747,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
 
 	pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
 		count, flags,
-		INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext);
+		smoke->i915->runtime_info.num_rings, smoke->ncontext);
 	return 0;
 }
 

Signature · 6 lines

2.19.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Quoted 5 lines · Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

Idea of runtime device info is to contain all fields from the existing device info which are modified at runtime.

Quoted 2 lines

Initially we move there fields which are never set from the static tables ie.: num_rings, num_sprites, num_scalers,

If we accept that num_sprites[fused_off_pipe] can be non-zero we could keep num_sprites and num_scalers in the static info. I don't *think* we have any code that would rely on those being zero.

struct intel_device_info {

drivers/gpu/drm/i915/intel_device_info.h +1 -3

-       u16 device_id;
        u16 gen_mask;
 
-       u8 gen;
+       u8 __gen;
        u8 gt; /* GT number, 0 if undefined */
-       intel_ring_mask_t ring_mask; /* Rings supported by the HW */

Quoting Tvrtko Ursulin (2018-11-12 17:12:38)

Quoted 12 lines

  struct intel_device_info {

drivers/gpu/drm/i915/intel_device_info.h +3 -4

-       u16 device_id;
         u16 gen_mask;
 
-       u8 gen;
+       u8 __gen;
         u8 gt; /* GT number, 0 if undefined */
-       intel_ring_mask_t ring_mask; /* Rings supported by the HW */
-       u8 num_pipes;
+       intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
+       u8 __num_pipes;

drivers/gpu/drm/i915/intel_device_info.h struct sseu_dev_info { · line 161

Quoted 6 lines

         enum intel_platform platform;
         u32 platform_mask;

drivers/gpu/drm/i915/intel_device_info.h +1 -2

-       enum intel_ppgtt ppgtt;
-       unsigned int page_sizes; /* page sizes supported by the HW */
+       enum intel_ppgtt __ppgtt;

ppgtt mode is static.

Quoted 13 lines

Quoting Tvrtko Ursulin (2018-11-12 17:12:38)

Quoted 12 lines

  struct intel_device_info {

drivers/gpu/drm/i915/intel_device_info.h +3 -4

-       u16 device_id;
         u16 gen_mask;
 
-       u8 gen;
+       u8 __gen;
         u8 gt; /* GT number, 0 if undefined */
-       intel_ring_mask_t ring_mask; /* Rings supported by the HW */
-       u8 num_pipes;
+       intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
+       u8 __num_pipes;

Quoted 8 lines

drivers/gpu/drm/i915/intel_device_info.h struct sseu_dev_info { · line 161

Quoted 6 lines

         enum intel_platform platform;
         u32 platform_mask;

drivers/gpu/drm/i915/intel_device_info.h +1 -2

-       enum intel_ppgtt ppgtt;
-       unsigned int page_sizes; /* page sizes supported by the HW */
+       enum intel_ppgtt __ppgtt;

ppgtt mode is static.

What about:

From: Tvrtko Ursulin <[email protected]>

After the previous change which cleared the static tables from effectively unused storage, we now replicate entries which have defaults set from there, but can be overriden at runtime.

For this class of variables all accessor macros and call sites are changed to use the runtime version. Therefore at driver load we need to copy over these variables from static to the runtime table.

We add double prefixes to the affected device info members to signify they are special and to catch all current and future users.

Signed-off-by Tvrtko Ursulin <[email protected]>

Cc Chris Wilson <[email protected]>

Cc Jani Nikula <[email protected]>

---

drivers/gpu/drm/i915/selftests/mock_gem_device.c +4 -5

-	mkwrite_device_info(i915)->page_sizes =
-		I915_GTT_PAGE_SIZE_4K |
-		I915_GTT_PAGE_SIZE_64K |
-		I915_GTT_PAGE_SIZE_2M;
+	i915->runtime_info.page_sizes = I915_GTT_PAGE_SIZE_4K |
+					I915_GTT_PAGE_SIZE_64K |
+					I915_GTT_PAGE_SIZE_2M;
 
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);

@@ -231,7 +230,7 @@ struct drm_i915_private *mock_gem_device(void)
 
 	mock_init_ggtt(i915);
 
-	mkwrite_device_info(i915)->ring_mask = BIT(0);
+	i915->runtime_info.ring_mask = BIT(0);
 	i915->kernel_context = mock_context(i915, NULL);
 	if (!i915->kernel_context)
 		goto err_unlock;

Signature · 6 lines

2.19.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Quoted 17 lines · Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

After the previous change which cleared the static tables from effectively unused storage, we now replicate entries which have defaults set from there, but can be overriden at runtime.

For this class of variables all accessor macros and call sites are changed to use the runtime version. Therefore at driver load we need to copy over these variables from static to the runtime table.

We add double prefixes to the affected device info members to signify they are special and to catch all current and future users.

Signed-off-by Tvrtko Ursulin <[email protected]>

Cc Chris Wilson <[email protected]>

Cc Jani Nikula <[email protected]>

---

[...]

Quoted 8 lines

drivers/gpu/drm/i915/selftests/mock_gem_device.c +0 -0

index 43ed8b28aeaa..b6849ca11e01 100644
@@ -174,12 +174,11 @@ struct drm_i915_private *mock_gem_device(void)
  	/* Using the global GTT may ask questions about KMS users, so prepare */
  	drm_mode_config_init(&i915->drm);
 

drivers/gpu/drm/i915/selftests/mock_gem_device.c struct drm_i915_private *mock_gem_device(void) · line 177

Quoted 2 lines

drivers/gpu/drm/i915/selftests/mock_gem_device.c +1 -1

-	mkwrite_device_info(i915)->gen = -1;
+	i915->runtime_info.gen = -1;

this seems the only place that is setting gen to something not statically defined. And it also misses that it'd need to set gen_mask, too.

Could we rather define a device_info for the mock device with the proper values rather than doing this?

From: Tvrtko Ursulin <[email protected]>

Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy.

Quoting Tvrtko Ursulin (2018-11-12 17:12:39)

Quoted 6 lines

From: Tvrtko Ursulin <[email protected]>

Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy.

The copy was deliberate to avoid the extra pointer. How does the change in code size now compare?

Quoted 10 lines · Chris Wilson

Quoting Tvrtko Ursulin (2018-11-12 17:12:39)

Quoted 6 lines

From: Tvrtko Ursulin <[email protected]>

Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy.

The copy was deliberate to avoid the extra pointer. How does the change in code size now compare?

AFAIR grows a bit, but overall series still ends up overall smaller. I need to re-run the numbers for more concrete info.

However, if we keep having a copy, ie. do not make device info properly read-only, are we still interested in splitting the two? Benefit would be diminished, but presumably people still think it would be worth it?

Quoted 12 lines · Chris Wilson

Quoted 10 lines

Quoting Tvrtko Ursulin (2018-11-12 17:12:39)

Quoted 6 lines

From: Tvrtko Ursulin <[email protected]>

Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy.

The copy was deliberate to avoid the extra pointer. How does the change in code size now compare?

Quoted 6 lines

AFAIR grows a bit, but overall series still ends up overall smaller. I need to re-run the numbers for more concrete info.

However, if we keep having a copy, ie. do not make device info properly read-only, are we still interested in splitting the two? Benefit would be diminished, but presumably people still think it would be worth it?

If we don't turn device info into a pointer to the static const structs, IMO there's simply no point in any of this. Then we might just as well drop the const and mkwrite_device_info, and use the mutable thing all over the place.

Modifying the device info copy was supposed to be an exception at the time of the copy, but with mkwrite_device_info it has proliferated. It's silly and ugly and wrong with no benefits. The const was put in place to hint that it's not supposed to be modified, but that didn't work out.

So which is it, runtime/static split with an extra pointer chase to the const data in rodata (I'm in favor), or just drop the const from the dev_priv copy and remove mkwrite_device_info?

The latter makes future attempts at utilizing DCE/LTO with a reduced number of device infos much harder I think.

From: Tvrtko Ursulin <[email protected]>

Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy.

Only unfortnate thing is that we need to convert all callsites which were referencing the device info directly to using the INTEL_INFO helper.

Signed-off-by Tvrtko Ursulin <[email protected]>

Cc Chris Wilson <[email protected]>

Cc Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_drv.c          |   9 +-
 drivers/gpu/drm/i915/i915_drv.h          | 107 ++++++-------
 drivers/gpu/drm/i915/i915_reg.h          | 190 +++++++++++------------
 drivers/gpu/drm/i915/intel_device_info.c |  11 +-
 drivers/gpu/drm/i915/intel_device_info.h |   2 +-
 drivers/gpu/drm/i915/intel_uncore.c      |   2 +-
 6 files changed, 151 insertions(+), 170 deletions(-)

drivers/gpu/drm/i915/i915_drv.c +3 -6

index bbdd36119eae..77dd7763b334 100644
@@ -1620,7 +1620,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 	if (drm_debug & DRM_UT_DRIVER) {
 		struct drm_printer p = drm_debug_printer("i915 device info:");
 
-		intel_device_info_dump(&dev_priv->info, &p);
+		intel_device_info_dump(dev_priv, &p);
 		intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
 	}
 

@@ -1638,7 +1638,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 	const struct intel_device_info *match_info =
 		(struct intel_device_info *)ent->driver_data;
 	struct intel_runtime_device_info *runtime_info;
-	struct intel_device_info *device_info;
+	const struct intel_device_info *device_info;
 	struct drm_i915_private *i915;
 	int err;
 

@@ -1654,12 +1654,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	i915->drm.pdev = pdev;
 	i915->drm.dev_private = i915;
+	i915->info = device_info = match_info;
 	pci_set_drvdata(pdev, &i915->drm);
 
-	/* Setup the write-once "constant" device info */
-	device_info = mkwrite_device_info(i915);
-	memcpy(device_info, match_info, sizeof(*device_info));
-
 	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 		     BITS_PER_TYPE(device_info->platform_mask));
 	BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));

drivers/gpu/drm/i915/i915_drv.h +47 -60

index 4fabbcd6cfb2..77ef41d53558 100644
@@ -1588,7 +1588,7 @@ struct drm_i915_private {
 	struct kmem_cache *dependencies;
 	struct kmem_cache *priorities;
 
-	const struct intel_device_info info;
+	const struct intel_device_info *info;
 	struct intel_runtime_device_info runtime_info;
 	struct intel_driver_caps caps;
 

@@ -2349,13 +2349,7 @@ static inline unsigned int i915_sg_segment_size(void)
 	return size;
 }
 
-static inline const struct intel_device_info *
-intel_info(const struct drm_i915_private *dev_priv)
-{
-	return &dev_priv->info;
-}
-
-#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
+#define INTEL_INFO(dev_priv)	((dev_priv)->info)
 #define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
 
 #define INTEL_GEN(dev_priv)	((dev_priv)->runtime_info.gen)

@@ -2371,7 +2365,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 /* Returns true if Gen is in inclusive range [Start, End] */
 #define IS_GEN(dev_priv, s, e) \
-	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
+	(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
 
 /*
  * Return true if revision is in range [since,until] inclusive.

@@ -2381,7 +2375,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_REVID(p, since, until) \
 	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
 
 #define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)

@@ -2403,7 +2397,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
-				 (dev_priv)->info.gt == 1)
+				 INTEL_INFO(dev_priv)->gt == 1)
 #define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)

@@ -2415,7 +2409,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
+#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \

@@ -2426,11 +2420,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
 				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
 				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
 				 INTEL_DEVID(dev_priv) == 0x0A1E)

@@ -2453,21 +2447,21 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
 				 INTEL_DEVID(dev_priv) == 0x87C0)
 #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
+				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 4)
+				 INTEL_INFO(dev_priv)->gt == 4)
 #define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
+				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
 				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
+				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
 					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
 

@@ -2530,16 +2524,16 @@ intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
+#define IS_GEN2(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
+#define IS_GEN6(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
+#define IS_GEN7(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
+#define IS_GEN8(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
+#define IS_GEN9(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
+#define IS_GEN11(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))

@@ -2566,20 +2560,20 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
 
-#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
-#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
+#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
+#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
 #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
 				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
 
-#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
+#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
-		((dev_priv)->info.has_logical_ring_contexts)
+		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
-		((dev_priv)->info.has_logical_ring_elsq)
+		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
-		((dev_priv)->info.has_logical_ring_preemption)
+		(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 

@@ -2596,9 +2590,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 	((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
 })
 
-#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
+#define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
-		((dev_priv)->info.overlay_needs_physical)
+		(INTEL_INFO(dev_priv)->overlay_needs_physical)
 
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))

@@ -2619,8 +2613,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
 					 !(IS_I915G(dev_priv) || \
 					 IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
+#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->has_hotplug)
 
 #define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
 #define HAS_FBC(dev_priv)	((dev_priv)->runtime_info.has_fbc)

@@ -2628,30 +2622,30 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
-#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
+#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->has_dp_mst)
 
-#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
-#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
+#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
+#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->has_psr)
 
 #define HAS_RC6(dev_priv)		 ((dev_priv)->runtime_info.has_rc6)
 #define HAS_RC6p(dev_priv)		 ((dev_priv)->runtime_info.has_rc6p)
 #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
 
-#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
+#define HAS_CSR(dev_priv)	(INTEL_INFO(dev_priv)->has_csr)
 
-#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
-#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
+#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
+#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
-#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)
+#define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->has_ipc)
 
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
-#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
+#define HAS_GUC(dev_priv)	(INTEL_INFO(dev_priv)->has_guc)
+#define HAS_GUC_CT(dev_priv)	(INTEL_INFO(dev_priv)->has_guc_ct)
 #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
 

@@ -2704,12 +2698,12 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->has_gmch_display)
 
 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
 
 /* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
+#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 				 2 : HAS_L3_DPF(dev_priv))
 

@@ -3465,13 +3459,6 @@ static inline void intel_register_dsm_handler(void) { return; }
 static inline void intel_unregister_dsm_handler(void) { return; }
 #endif /* CONFIG_ACPI */
 
-/* intel_device_info.c */
-static inline struct intel_device_info *
-mkwrite_device_info(struct drm_i915_private *dev_priv)
-{
-	return (struct intel_device_info *)&dev_priv->info;
-}
-
 /* modesetting */
 extern void intel_modeset_init_hw(struct drm_device *dev);
 extern int intel_modeset_init(struct drm_device *dev);

drivers/gpu/drm/i915/i915_reg.h +95 -95

index fe4b913e46ac..4c0e5b62e7fa 100644
@@ -179,15 +179,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
  * Device info offset array based helpers for groups of registers with unevenly
  * spaced base offsets.
  */
-#define _MMIO_PIPE2(pipe, reg)		_MMIO(dev_priv->info.pipe_offsets[pipe] - \
-					      dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
-					      dev_priv->info.display_mmio_offset)
-#define _MMIO_TRANS2(pipe, reg)		_MMIO(dev_priv->info.trans_offsets[(pipe)] - \
-					      dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
-					      dev_priv->info.display_mmio_offset)
-#define _CURSOR2(pipe, reg)		_MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
-					      dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
-					      dev_priv->info.display_mmio_offset)
+#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
+					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
+					      INTEL_INFO(dev_priv)->display_mmio_offset)
+#define _MMIO_TRANS2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
+					      INTEL_INFO(dev_priv)->display_mmio_offset)
+#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
+					      INTEL_INFO(dev_priv)->display_mmio_offset)
 
 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 #define _MASKED_FIELD(mask, value) ({					   \

@@ -3153,9 +3153,9 @@ enum i915_power_well_id {
 /*
  * Clock control & power management
  */
-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
-#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
+#define _DPLL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6014)
+#define _DPLL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6018)
+#define _CHV_DPLL_C (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6030)
 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
 
 #define VGA0	_MMIO(0x6000)

@@ -3252,9 +3252,9 @@ enum i915_power_well_id {
 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
 
-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
-#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
+#define _DPLL_A_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x601c)
+#define _DPLL_B_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6020)
+#define _CHV_DPLL_C_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x603c)
 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
 
 /*

@@ -3326,7 +3326,7 @@ enum i915_power_well_id {
 #define  DSTATE_PLL_D3_OFF			(1 << 3)
 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
-#define DSPCLK_GATE_D	_MMIO(dev_priv->info.display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6200)
 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */

@@ -3466,7 +3466,7 @@ enum i915_power_well_id {
 #define _PALETTE_A		0xa000
 #define _PALETTE_B		0xa800
 #define _CHV_PALETTE_C		0xc000
-#define PALETTE(pipe, i)	_MMIO(dev_priv->info.display_mmio_offset + \
+#define PALETTE(pipe, i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + \
 				      _PICK((pipe), _PALETTE_A,		\
 					    _PALETTE_B, _CHV_PALETTE_C) + \
 				      (i) * 4)

@@ -4295,7 +4295,7 @@ enum {
 
 
 /* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN		_MMIO(dev_priv->info.display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)

@@ -4325,7 +4325,7 @@ enum {
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
 
-#define PORT_HOTPLUG_STAT	_MMIO(dev_priv->info.display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61114)
 /*
  * HDMI/DP bits are g4x+
  *

@@ -4407,7 +4407,7 @@ enum {
 
 #define PORT_DFT_I9XX				_MMIO(0x61150)
 #define   DC_BALANCE_RESET			(1 << 25)
-#define PORT_DFT2_G4X		_MMIO(dev_priv->info.display_mmio_offset + 0x61154)
+#define PORT_DFT2_G4X		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
 #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */

@@ -4680,7 +4680,7 @@ enum {
 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
 
 /* Panel fitting */
-#define PFIT_CONTROL	_MMIO(dev_priv->info.display_mmio_offset + 0x61230)
+#define PFIT_CONTROL	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61230)
 #define   PFIT_ENABLE		(1 << 31)
 #define   PFIT_PIPE_MASK	(3 << 29)
 #define   PFIT_PIPE_SHIFT	29

@@ -4698,7 +4698,7 @@ enum {
 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
 #define   PFIT_SCALING_PILLAR	(2 << 26)
 #define   PFIT_SCALING_LETTER	(3 << 26)
-#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61234)
 /* Pre-965 */
 #define		PFIT_VERT_SCALE_SHIFT		20
 #define		PFIT_VERT_SCALE_MASK		0xfff00000

@@ -4710,25 +4710,25 @@ enum {
 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
 
-#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61238)
 
-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
+#define _VLV_BLC_PWM_CTL2_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61350)
 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
 					 _VLV_BLC_PWM_CTL2_B)
 
-#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
+#define _VLV_BLC_PWM_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61354)
 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
 					_VLV_BLC_PWM_CTL_B)
 
-#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
+#define _VLV_BLC_HIST_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61360)
 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
 					 _VLV_BLC_HIST_CTL_B)
 
 /* Backlight control */
-#define BLC_PWM_CTL2	_MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE		(1 << 31)
 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT		(1 << 29)

@@ -4751,7 +4751,7 @@ enum {
 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
-#define BLC_PWM_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.

@@ -4773,7 +4773,7 @@ enum {
 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
 
-#define BLC_HIST_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
 #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the

@@ -5397,47 +5397,47 @@ enum {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
-#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
-#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
-#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
-#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
-#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
-
-#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
-#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
-#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
-#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
-#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
-#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
-
-#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
-#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
-#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
-#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
-#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
-#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
-
-#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
-#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
-#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
-#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
-#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
-#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
-
-#define _DPE_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64410)
-#define _DPE_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64414)
-#define _DPE_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64418)
-#define _DPE_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6441c)
-#define _DPE_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64420)
-#define _DPE_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64424)
-
-#define _DPF_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64510)
-#define _DPF_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64514)
-#define _DPF_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64518)
-#define _DPF_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6451c)
-#define _DPF_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64520)
-#define _DPF_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64524)
+#define _DPA_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64324)
+
+#define _DPE_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64410)
+#define _DPE_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64414)
+#define _DPE_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64418)
+#define _DPE_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6441c)
+#define _DPE_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64420)
+#define _DPE_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64424)
+
+#define _DPF_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64524)
 
 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

@@ -5713,7 +5713,7 @@ enum {
 #define   DPINVGTT_STATUS_MASK			0xff
 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
-#define DSPARB			_MMIO(dev_priv->info.display_mmio_offset + 0x70030)
+#define DSPARB			_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)

@@ -5748,7 +5748,7 @@ enum {
 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
 
 /* pnv/gen4/g4x/vlv/chv */
-#define DSPFW1		_MMIO(dev_priv->info.display_mmio_offset + 0x70034)
+#define DSPFW1		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT		23
 #define   DSPFW_SR_MASK			(0x1ff << 23)
 #define   DSPFW_CURSORB_SHIFT		16

@@ -5759,7 +5759,7 @@ enum {
 #define   DSPFW_PLANEA_SHIFT		0
 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
-#define DSPFW2		_MMIO(dev_priv->info.display_mmio_offset + 0x70038)
+#define DSPFW2		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70038)
 #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
 #define   DSPFW_FBC_SR_SHIFT		28
 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */

@@ -5775,7 +5775,7 @@ enum {
 #define   DSPFW_SPRITEA_SHIFT		0
 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
-#define DSPFW3		_MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
+#define DSPFW3		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7003c)
 #define   DSPFW_HPLL_SR_EN		(1 << 31)
 #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
 #define   DSPFW_CURSOR_SR_SHIFT		24

@@ -6191,35 +6191,35 @@ enum {
  * [10:1f] all
  * [30:32] all
  */
-#define SWF0(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
-#define SWF1(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
-#define SWF3(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
+#define SWF0(i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
 /* Pipe B */
-#define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
-#define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
-#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
+#define _PIPEBDSL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71000)
+#define _PIPEBCONF		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71008)
+#define _PIPEBSTAT		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
-#define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_G4X	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_G4X	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71044)
 
 
 /* Display B control */
-#define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
+#define _DSPBCNTR		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71180)
 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
-#define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
-#define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
-#define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
-#define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
-#define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
-#define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
+#define _DSPBADDR		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71188)
+#define _DSPBPOS		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7118C)
+#define _DSPBSIZE		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71190)
+#define _DSPBSURF		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x711AC)
 
 /* ICL DSI 0 and 1 */
 #define _PIPEDSI0CONF		0x7b008

@@ -8773,7 +8773,7 @@ enum {
 #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1 << 2)
 
 /* Audio */
-#define G4X_AUD_VID_DID			_MMIO(dev_priv->info.display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID			_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x62020)
 #define   INTEL_AUDIO_DEVCL		0x808629FB
 #define   INTEL_AUDIO_DEVBLC		0x80862801
 #define   INTEL_AUDIO_DEVCTG		0x80862802

drivers/gpu/drm/i915/intel_device_info.c +4 -7

index aeb7b9225b18..00758d11047b 100644
@@ -121,19 +121,16 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
 	intel_runtime_device_info_dump_flags(info, p);
 }
 
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(struct drm_i915_private *dev_priv,
 			    struct drm_printer *p)
 {
-	struct drm_i915_private *dev_priv =
-		container_of(info, struct drm_i915_private, info);
-
 	drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
 		   INTEL_DEVID(dev_priv),
 		   INTEL_REVID(dev_priv),
-		   intel_platform_name(info->platform),
-		   info->__gen);
+		   intel_platform_name(INTEL_INFO(dev_priv)->platform),
+		   INTEL_INFO(dev_priv)->__gen);
 
-	intel_device_info_dump_flags(info, p);
+	intel_device_info_dump_flags(INTEL_INFO(dev_priv), p);
 }
 
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,

drivers/gpu/drm/i915/intel_device_info.h +1 -1

index 50c8fda20bdd..9bacd466f4a2 100644
@@ -270,7 +270,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
 const char *intel_platform_name(enum intel_platform platform);
 
 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(struct drm_i915_private *dev_priv,
 			    struct drm_printer *p);
 void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);

drivers/gpu/drm/i915/intel_uncore.c +1 -1

index 9289515108c3..def498402bbb 100644
@@ -2256,7 +2256,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
 
 bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
 {
-	return (dev_priv->info.has_reset_engine &&
+	return (INTEL_INFO(dev_priv)->has_reset_engine &&
 		i915_modparams.reset >= 2);
 }

Quoted 9 lines · Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy.

Only unfortnate thing is that we need to convert all callsites which were referencing the device info directly to using the INTEL_INFO helper.

I'm not sure if that's all that bad. When I was toying around with mkwrite_device_info removal, I actually started off with changing all device info references to INTEL_INFO. It's a big patch, but it nicely centralizes many of the other changes instead of splattering all over the place.

I'd actually like to see RUNTIME_INFO or similar macro as well, just to be able to change the way it's handled later on.

BR,
Jani.

Quoted 713 lines

Signed-off-by Tvrtko Ursulin <[email protected]>

Cc Chris Wilson <[email protected]>

Cc Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_drv.c          |   9 +-
 drivers/gpu/drm/i915/i915_drv.h          | 107 ++++++-------
 drivers/gpu/drm/i915/i915_reg.h          | 190 +++++++++++------------
 drivers/gpu/drm/i915/intel_device_info.c |  11 +-
 drivers/gpu/drm/i915/intel_device_info.h |   2 +-
 drivers/gpu/drm/i915/intel_uncore.c      |   2 +-
 6 files changed, 151 insertions(+), 170 deletions(-)

drivers/gpu/drm/i915/i915_drv.c +3 -6

index bbdd36119eae..77dd7763b334 100644
@@ -1620,7 +1620,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 	if (drm_debug & DRM_UT_DRIVER) {
 		struct drm_printer p = drm_debug_printer("i915 device info:");
 
-		intel_device_info_dump(&dev_priv->info, &p);
+		intel_device_info_dump(dev_priv, &p);
 		intel_device_info_dump_runtime(&dev_priv->runtime_info, &p);
 	}
 

@@ -1638,7 +1638,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 	const struct intel_device_info *match_info =
 		(struct intel_device_info *)ent->driver_data;
 	struct intel_runtime_device_info *runtime_info;
-	struct intel_device_info *device_info;
+	const struct intel_device_info *device_info;
 	struct drm_i915_private *i915;
 	int err;
 

@@ -1654,12 +1654,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	i915->drm.pdev = pdev;
 	i915->drm.dev_private = i915;
+	i915->info = device_info = match_info;
 	pci_set_drvdata(pdev, &i915->drm);
 
-	/* Setup the write-once "constant" device info */
-	device_info = mkwrite_device_info(i915);
-	memcpy(device_info, match_info, sizeof(*device_info));
-
 	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 		     BITS_PER_TYPE(device_info->platform_mask));
 	BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));

drivers/gpu/drm/i915/i915_drv.h +47 -60

index 4fabbcd6cfb2..77ef41d53558 100644
@@ -1588,7 +1588,7 @@ struct drm_i915_private {
 	struct kmem_cache *dependencies;
 	struct kmem_cache *priorities;
 
-	const struct intel_device_info info;
+	const struct intel_device_info *info;
 	struct intel_runtime_device_info runtime_info;
 	struct intel_driver_caps caps;
 

@@ -2349,13 +2349,7 @@ static inline unsigned int i915_sg_segment_size(void)
 	return size;
 }
 
-static inline const struct intel_device_info *
-intel_info(const struct drm_i915_private *dev_priv)
-{
-	return &dev_priv->info;
-}
-
-#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
+#define INTEL_INFO(dev_priv)	((dev_priv)->info)
 #define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
 
 #define INTEL_GEN(dev_priv)	((dev_priv)->runtime_info.gen)

@@ -2371,7 +2365,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 /* Returns true if Gen is in inclusive range [Start, End] */
 #define IS_GEN(dev_priv, s, e) \
-	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
+	(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
 
 /*
  * Return true if revision is in range [since,until] inclusive.

@@ -2381,7 +2375,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_REVID(p, since, until) \
 	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
 
 #define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)

@@ -2403,7 +2397,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
-				 (dev_priv)->info.gt == 1)
+				 INTEL_INFO(dev_priv)->gt == 1)
 #define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)

@@ -2415,7 +2409,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
+#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \

@@ -2426,11 +2420,11 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
 				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
 				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
 #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 /* ULX machines are also considered ULT. */
 #define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
 				 INTEL_DEVID(dev_priv) == 0x0A1E)

@@ -2453,21 +2447,21 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
 				 INTEL_DEVID(dev_priv) == 0x87C0)
 #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
+				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 4)
+				 INTEL_INFO(dev_priv)->gt == 4)
 #define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
+				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
 				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
 #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
+				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
+				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
 					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
 

@@ -2530,16 +2524,16 @@ intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
+#define IS_GEN2(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(4)))
+#define IS_GEN6(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(5)))
+#define IS_GEN7(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(6)))
+#define IS_GEN8(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(7)))
+#define IS_GEN9(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(9)))
+#define IS_GEN11(dev_priv)	(!!(INTEL_INFO(dev_priv)->gen_mask & BIT(10)))
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))

@@ -2566,20 +2560,20 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
 
-#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
-#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
+#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
+#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
 #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
 				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
 
-#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
+#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
-		((dev_priv)->info.has_logical_ring_contexts)
+		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
-		((dev_priv)->info.has_logical_ring_elsq)
+		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
-		((dev_priv)->info.has_logical_ring_preemption)
+		(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 

@@ -2596,9 +2590,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 	((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
 })
 
-#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
+#define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
-		((dev_priv)->info.overlay_needs_physical)
+		(INTEL_INFO(dev_priv)->overlay_needs_physical)
 
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))

@@ -2619,8 +2613,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
 					 !(IS_I915G(dev_priv) || \
 					 IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
+#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->supports_tv)
+#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->has_hotplug)
 
 #define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
 #define HAS_FBC(dev_priv)	((dev_priv)->runtime_info.has_fbc)

@@ -2628,30 +2622,30 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
-#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
+#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->has_dp_mst)
 
-#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
-#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
+#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
+#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->has_psr)
 
 #define HAS_RC6(dev_priv)		 ((dev_priv)->runtime_info.has_rc6)
 #define HAS_RC6p(dev_priv)		 ((dev_priv)->runtime_info.has_rc6p)
 #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
 
-#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
+#define HAS_CSR(dev_priv)	(INTEL_INFO(dev_priv)->has_csr)
 
-#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
-#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
+#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
+#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
-#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)
+#define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->has_ipc)
 
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
-#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
+#define HAS_GUC(dev_priv)	(INTEL_INFO(dev_priv)->has_guc)
+#define HAS_GUC_CT(dev_priv)	(INTEL_INFO(dev_priv)->has_guc_ct)
 #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
 

@@ -2704,12 +2698,12 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->has_gmch_display)
 
 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
 
 /* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
+#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 				 2 : HAS_L3_DPF(dev_priv))
 

@@ -3465,13 +3459,6 @@ static inline void intel_register_dsm_handler(void) { return; }
 static inline void intel_unregister_dsm_handler(void) { return; }
 #endif /* CONFIG_ACPI */
 
-/* intel_device_info.c */
-static inline struct intel_device_info *
-mkwrite_device_info(struct drm_i915_private *dev_priv)
-{
-	return (struct intel_device_info *)&dev_priv->info;
-}
-
 /* modesetting */
 extern void intel_modeset_init_hw(struct drm_device *dev);
 extern int intel_modeset_init(struct drm_device *dev);

drivers/gpu/drm/i915/i915_reg.h +95 -95

index fe4b913e46ac..4c0e5b62e7fa 100644
@@ -179,15 +179,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
  * Device info offset array based helpers for groups of registers with unevenly
  * spaced base offsets.
  */
-#define _MMIO_PIPE2(pipe, reg)		_MMIO(dev_priv->info.pipe_offsets[pipe] - \
-					      dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
-					      dev_priv->info.display_mmio_offset)
-#define _MMIO_TRANS2(pipe, reg)		_MMIO(dev_priv->info.trans_offsets[(pipe)] - \
-					      dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
-					      dev_priv->info.display_mmio_offset)
-#define _CURSOR2(pipe, reg)		_MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
-					      dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
-					      dev_priv->info.display_mmio_offset)
+#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
+					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
+					      INTEL_INFO(dev_priv)->display_mmio_offset)
+#define _MMIO_TRANS2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
+					      INTEL_INFO(dev_priv)->display_mmio_offset)
+#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
+					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
+					      INTEL_INFO(dev_priv)->display_mmio_offset)
 
 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 #define _MASKED_FIELD(mask, value) ({					   \

@@ -3153,9 +3153,9 @@ enum i915_power_well_id {
 /*
  * Clock control & power management
  */
-#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
-#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
+#define _DPLL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6014)
+#define _DPLL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6018)
+#define _CHV_DPLL_C (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6030)
 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
 
 #define VGA0	_MMIO(0x6000)

@@ -3252,9 +3252,9 @@ enum i915_power_well_id {
 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
 
-#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
-#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
-#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
+#define _DPLL_A_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x601c)
+#define _DPLL_B_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x6020)
+#define _CHV_DPLL_C_MD (INTEL_INFO(dev_priv)->display_mmio_offset + 0x603c)
 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
 
 /*

@@ -3326,7 +3326,7 @@ enum i915_power_well_id {
 #define  DSTATE_PLL_D3_OFF			(1 << 3)
 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
-#define DSPCLK_GATE_D	_MMIO(dev_priv->info.display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6200)
 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */

@@ -3466,7 +3466,7 @@ enum i915_power_well_id {
 #define _PALETTE_A		0xa000
 #define _PALETTE_B		0xa800
 #define _CHV_PALETTE_C		0xc000
-#define PALETTE(pipe, i)	_MMIO(dev_priv->info.display_mmio_offset + \
+#define PALETTE(pipe, i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + \
 				      _PICK((pipe), _PALETTE_A,		\
 					    _PALETTE_B, _CHV_PALETTE_C) + \
 				      (i) * 4)

@@ -4295,7 +4295,7 @@ enum {
 
 
 /* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN		_MMIO(dev_priv->info.display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)

@@ -4325,7 +4325,7 @@ enum {
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
 
-#define PORT_HOTPLUG_STAT	_MMIO(dev_priv->info.display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61114)
 /*
  * HDMI/DP bits are g4x+
  *

@@ -4407,7 +4407,7 @@ enum {
 
 #define PORT_DFT_I9XX				_MMIO(0x61150)
 #define   DC_BALANCE_RESET			(1 << 25)
-#define PORT_DFT2_G4X		_MMIO(dev_priv->info.display_mmio_offset + 0x61154)
+#define PORT_DFT2_G4X		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
 #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */

@@ -4680,7 +4680,7 @@ enum {
 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
 
 /* Panel fitting */
-#define PFIT_CONTROL	_MMIO(dev_priv->info.display_mmio_offset + 0x61230)
+#define PFIT_CONTROL	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61230)
 #define   PFIT_ENABLE		(1 << 31)
 #define   PFIT_PIPE_MASK	(3 << 29)
 #define   PFIT_PIPE_SHIFT	29

@@ -4698,7 +4698,7 @@ enum {
 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
 #define   PFIT_SCALING_PILLAR	(2 << 26)
 #define   PFIT_SCALING_LETTER	(3 << 26)
-#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61234)
 /* Pre-965 */
 #define		PFIT_VERT_SCALE_SHIFT		20
 #define		PFIT_VERT_SCALE_MASK		0xfff00000

@@ -4710,25 +4710,25 @@ enum {
 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
 
-#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS _MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61238)
 
-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
+#define _VLV_BLC_PWM_CTL2_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61350)
 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
 					 _VLV_BLC_PWM_CTL2_B)
 
-#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
+#define _VLV_BLC_PWM_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61354)
 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
 					_VLV_BLC_PWM_CTL_B)
 
-#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
+#define _VLV_BLC_HIST_CTL_A (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (INTEL_INFO(dev_priv)->display_mmio_offset + 0x61360)
 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
 					 _VLV_BLC_HIST_CTL_B)
 
 /* Backlight control */
-#define BLC_PWM_CTL2	_MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE		(1 << 31)
 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT		(1 << 29)

@@ -4751,7 +4751,7 @@ enum {
 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
-#define BLC_PWM_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61254)
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.

@@ -4773,7 +4773,7 @@ enum {
 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
 
-#define BLC_HIST_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x61260)
 #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the

@@ -5397,47 +5397,47 @@ enum {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
-#define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
-#define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
-#define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
-#define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
-#define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
-
-#define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
-#define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
-#define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
-#define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
-#define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
-#define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
-
-#define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
-#define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
-#define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
-#define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
-#define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
-#define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
-
-#define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
-#define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
-#define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
-#define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
-#define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
-#define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
-
-#define _DPE_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64410)
-#define _DPE_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64414)
-#define _DPE_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64418)
-#define _DPE_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6441c)
-#define _DPE_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64420)
-#define _DPE_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64424)
-
-#define _DPF_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64510)
-#define _DPF_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64514)
-#define _DPF_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64518)
-#define _DPF_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6451c)
-#define _DPF_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64520)
-#define _DPF_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64524)
+#define _DPA_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64010)
+#define _DPA_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64110)
+#define _DPB_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64210)
+#define _DPC_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64310)
+#define _DPD_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64314)
+#define _DPD_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64318)
+#define _DPD_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6431c)
+#define _DPD_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64320)
+#define _DPD_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64324)
+
+#define _DPE_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64410)
+#define _DPE_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64414)
+#define _DPE_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64418)
+#define _DPE_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6441c)
+#define _DPE_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64420)
+#define _DPE_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64424)
+
+#define _DPF_AUX_CH_CTL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64510)
+#define _DPF_AUX_CH_DATA1	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64514)
+#define _DPF_AUX_CH_DATA2	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64518)
+#define _DPF_AUX_CH_DATA3	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x6451c)
+#define _DPF_AUX_CH_DATA4	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64520)
+#define _DPF_AUX_CH_DATA5	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x64524)
 
 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */

@@ -5713,7 +5713,7 @@ enum {
 #define   DPINVGTT_STATUS_MASK			0xff
 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
 
-#define DSPARB			_MMIO(dev_priv->info.display_mmio_offset + 0x70030)
+#define DSPARB			_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)

@@ -5748,7 +5748,7 @@ enum {
 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
 
 /* pnv/gen4/g4x/vlv/chv */
-#define DSPFW1		_MMIO(dev_priv->info.display_mmio_offset + 0x70034)
+#define DSPFW1		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70034)
 #define   DSPFW_SR_SHIFT		23
 #define   DSPFW_SR_MASK			(0x1ff << 23)
 #define   DSPFW_CURSORB_SHIFT		16

@@ -5759,7 +5759,7 @@ enum {
 #define   DSPFW_PLANEA_SHIFT		0
 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
-#define DSPFW2		_MMIO(dev_priv->info.display_mmio_offset + 0x70038)
+#define DSPFW2		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70038)
 #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
 #define   DSPFW_FBC_SR_SHIFT		28
 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */

@@ -5775,7 +5775,7 @@ enum {
 #define   DSPFW_SPRITEA_SHIFT		0
 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
-#define DSPFW3		_MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
+#define DSPFW3		_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7003c)
 #define   DSPFW_HPLL_SR_EN		(1 << 31)
 #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
 #define   DSPFW_CURSOR_SR_SHIFT		24

@@ -6191,35 +6191,35 @@ enum {
  * [10:1f] all
  * [30:32] all
  */
-#define SWF0(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
-#define SWF1(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
-#define SWF3(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
+#define SWF0(i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i)	_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
 /* Pipe B */
-#define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
-#define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
-#define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
+#define _PIPEBDSL		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71000)
+#define _PIPEBCONF		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71008)
+#define _PIPEBSTAT		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
-#define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_G4X	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_G4X	(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71044)
 
 
 /* Display B control */
-#define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
+#define _DSPBCNTR		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71180)
 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
-#define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
-#define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
-#define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
-#define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
-#define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
-#define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
-#define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
+#define _DSPBADDR		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71188)
+#define _DSPBPOS		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7118C)
+#define _DSPBSIZE		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x71190)
+#define _DSPBSURF		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE		(INTEL_INFO(dev_priv)->display_mmio_offset + 0x711AC)
 
 /* ICL DSI 0 and 1 */
 #define _PIPEDSI0CONF		0x7b008

@@ -8773,7 +8773,7 @@ enum {
 #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1 << 2)
 
 /* Audio */
-#define G4X_AUD_VID_DID			_MMIO(dev_priv->info.display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID			_MMIO(INTEL_INFO(dev_priv)->display_mmio_offset + 0x62020)
 #define   INTEL_AUDIO_DEVCL		0x808629FB
 #define   INTEL_AUDIO_DEVBLC		0x80862801
 #define   INTEL_AUDIO_DEVCTG		0x80862802

drivers/gpu/drm/i915/intel_device_info.c +4 -7

index aeb7b9225b18..00758d11047b 100644
@@ -121,19 +121,16 @@ intel_device_info_dump_runtime(const struct intel_runtime_device_info *info,
 	intel_runtime_device_info_dump_flags(info, p);
 }
 
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(struct drm_i915_private *dev_priv,
 			    struct drm_printer *p)
 {
-	struct drm_i915_private *dev_priv =
-		container_of(info, struct drm_i915_private, info);
-
 	drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
 		   INTEL_DEVID(dev_priv),
 		   INTEL_REVID(dev_priv),
-		   intel_platform_name(info->platform),
-		   info->__gen);
+		   intel_platform_name(INTEL_INFO(dev_priv)->platform),
+		   INTEL_INFO(dev_priv)->__gen);
 
-	intel_device_info_dump_flags(info, p);
+	intel_device_info_dump_flags(INTEL_INFO(dev_priv), p);
 }
 
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,

drivers/gpu/drm/i915/intel_device_info.h +1 -1

index 50c8fda20bdd..9bacd466f4a2 100644
@@ -270,7 +270,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
 const char *intel_platform_name(enum intel_platform platform);
 
 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
-void intel_device_info_dump(const struct intel_device_info *info,
+void intel_device_info_dump(struct drm_i915_private *dev_priv,
 			    struct drm_printer *p);
 void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);

drivers/gpu/drm/i915/intel_uncore.c +1 -1

index 9289515108c3..def498402bbb 100644
@@ -2256,7 +2256,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
 
 bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
 {
-	return (dev_priv->info.has_reset_engine &&
+	return (INTEL_INFO(dev_priv)->has_reset_engine &&
 		i915_modparams.reset >= 2);
 }