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arm64: dts: actions: s700: Add I2C controller nodes

PATCH In review Parthiban Nallathambi 2 participants 3 messages Nov 13, 2018 – Nov 15, 2018

Subsystems (3)
Device tree bindings I2C subsystem host drivers Arm/actions semi architecture
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Parthiban Nallathambi

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#0 lore raw

PATCH 1/1 arm64: dts: actions: s700: Add I2C controller nodes

Add I2C controller nodes for Actions Semiconductor S700 SoC.

Signed-off-by Parthiban Nallathambi <[email protected]>
---
 arch/arm64/boot/dts/actions/s700.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
arch/arm64/boot/dts/actions/s700.dtsi +40 -0
index 192c7b39c8c1..573c844d7afe 100644
@@ -174,6 +174,46 @@
 			#clock-cells = <1>;
 		};
 
+		i2c0: i2c at e0170000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0170000 0 0x1000>;
+			clocks = <&cmu CLK_I2C0>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e0174000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0174000 0 0x1000>;
+			clocks = <&cmu CLK_I2C1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e0178000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0178000 0 0x1000>;
+			clocks = <&cmu CLK_I2C2>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e017c000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe017c000 0 0x1000>;
+			clocks = <&cmu CLK_I2C3>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		sps: power-controller at e01b0100 {
 			compatible = "actions,s700-sps";
 			reg = <0x0 0xe01b0100 0x0 0x100>;
Signature · 1 line
2.17.2
#1 lore raw

Hi Parthiban,

Quoted 12 lines · Parthiban Nallathambi

Add I2C controller nodes for Actions Semiconductor S700 SoC.

Signed-off-by Parthiban Nallathambi <[email protected]>
---
 arch/arm64/boot/dts/actions/s700.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
arch/arm64/boot/dts/actions/s700.dtsi +0 -0
index 192c7b39c8c1..573c844d7afe 100644

arch/arm64/boot/dts/actions/s700.dtsi line 178

Quoted 5 lines
arch/arm64/boot/dts/actions/s700.dtsi +2 -0
@@ -174,6 +174,46 @@
 			#clock-cells = <1>;
 		};
 
+		i2c0: i2c at e0170000 {
+			compatible = "actions,s900-i2c";

Why don't you add a compatible for S700? Also, please add the pinctrl nodes for these busses and enable the ones exposed on board. These could go in a separate patch.

Thanks,
Mani

Quoted 44 lines
arch/arm64/boot/dts/actions/s700.dtsi +38 -0
+			reg = <0 0xe0170000 0 0x1000>;
+			clocks = <&cmu CLK_I2C0>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e0174000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0174000 0 0x1000>;
+			clocks = <&cmu CLK_I2C1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e0178000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0178000 0 0x1000>;
+			clocks = <&cmu CLK_I2C2>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e017c000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe017c000 0 0x1000>;
+			clocks = <&cmu CLK_I2C3>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		sps: power-controller at e01b0100 {
 			compatible = "actions,s700-sps";
 			reg = <0x0 0xe01b0100 0x0 0x100>;
Signature · 1 line
2.17.2
author
#2 lore raw
Quoted 18 lines · Manivannan Sadhasivam

Hi Parthiban,

Quoted 15 lines · Parthiban Nallathambi

Add I2C controller nodes for Actions Semiconductor S700 SoC.

Signed-off-by Parthiban Nallathambi <[email protected]>
---
  arch/arm64/boot/dts/actions/s700.dtsi | 40 +++++++++++++++++++++++++++
  1 file changed, 40 insertions(+)
arch/arm64/boot/dts/actions/s700.dtsi +0 -0
index 192c7b39c8c1..573c844d7afe 100644
@@ -174,6 +174,46 @@
  			#clock-cells = <1>;
  		};
Quoted 6 lines

arch/arm64/boot/dts/actions/s700.dtsi line 178

Quoted 2 lines
arch/arm64/boot/dts/actions/s700.dtsi +2 -0
+		i2c0: i2c at e0170000 {
+			compatible = "actions,s900-i2c";

Why don't you add a compatible for S700? Also, please add the pinctrl nodes for these busses and enable the ones exposed on board. These could go in a separate patch.

Makes sense as pinctrl is already fine. Will do in v2 as series!

Thanks,
Parthi

Quoted 49 lines

Thanks,
Mani

Quoted 44 lines
arch/arm64/boot/dts/actions/s700.dtsi +38 -0
+			reg = <0 0xe0170000 0 0x1000>;
+			clocks = <&cmu CLK_I2C0>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e0174000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0174000 0 0x1000>;
+			clocks = <&cmu CLK_I2C1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e0178000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe0178000 0 0x1000>;
+			clocks = <&cmu CLK_I2C2>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e017c000 {
+			compatible = "actions,s900-i2c";
+			reg = <0 0xe017c000 0 0x1000>;
+			clocks = <&cmu CLK_I2C3>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
  		sps: power-controller at e01b0100 {
  			compatible = "actions,s700-sps";
  			reg = <0x0 0xe01b0100 0x0 0x100>;
Signature · 1 line
2.17.2
Signature · 6 lines
Thanks,
Parthiban N

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