kms_content_protection: Fix log bug on 32-bit platforms.

index 801eff66c272..ef90ed4c1792 100644
@@ -89,7 +89,8 @@ wait_for_prop_value(igt_output_t *output, uint64_t expected,
 			return true;
 		usleep(1000);
 	}
-	igt_info("prop_value mismatch %ld != %ld\n", val, expected);
+	igt_info("prop_value mismatch %" PRId64 " != %" PRId64 "\n",
+		 val, expected);
 
 	return false;
 }

new file mode 100644
index 000000000000..f446656d00b1
@@ -0,0 +1,204 @@
+/*
+ * Copyright © 2014-2018 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _V3D_DRM_H_
+#define _V3D_DRM_H_
+
+#include "drm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define DRM_V3D_SUBMIT_CL                         0x00
+#define DRM_V3D_WAIT_BO                           0x01
+#define DRM_V3D_CREATE_BO                         0x02
+#define DRM_V3D_MMAP_BO                           0x03
+#define DRM_V3D_GET_PARAM                         0x04
+#define DRM_V3D_GET_BO_OFFSET                     0x05
+
+#define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
+#define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
+#define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
+#define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
+#define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
+#define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
+
+/**
+ * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
+ * engine.
+ *
+ * This asks the kernel to have the GPU execute an optional binner
+ * command list, and a render command list.
+ */
+struct drm_v3d_submit_cl {
+	/* Pointer to the binner command list.
+	 *
+	 * This is the first set of commands executed, which runs the
+	 * coordinate shader to determine where primitives land on the screen,
+	 * then writes out the state updates and draw calls necessary per tile
+	 * to the tile allocation BO.
+	 *
+	 * This BCL will block on any previous BCL submitted on the
+	 * same FD, but not on any RCL or BCLs submitted by other
+	 * clients -- that is left up to the submitter to control
+	 * using in_sync_bcl if necessary.
+	 */
+	__u32 bcl_start;
+
+	 /** End address of the BCL (first byte after the BCL) */
+	__u32 bcl_end;
+
+	/* Offset of the render command list.
+	 *
+	 * This is the second set of commands executed, which will either
+	 * execute the tiles that have been set up by the BCL, or a fixed set
+	 * of tiles (in the case of RCL-only blits).
+	 *
+	 * This RCL will block on this submit's BCL, and any previous
+	 * RCL submitted on the same FD, but not on any RCL or BCLs
+	 * submitted by other clients -- that is left up to the
+	 * submitter to control using in_sync_rcl if necessary.
+	 */
+	__u32 rcl_start;
+
+	 /** End address of the RCL (first byte after the RCL) */
+	__u32 rcl_end;
+
+	/** An optional sync object to wait on before starting the BCL. */
+	__u32 in_sync_bcl;
+	/** An optional sync object to wait on before starting the RCL. */
+	__u32 in_sync_rcl;
+	/** An optional sync object to place the completion fence in. */
+	__u32 out_sync;
+
+	/* Offset of the tile alloc memory
+	 *
+	 * This is optional on V3D 3.3 (where the CL can set the value) but
+	 * required on V3D 4.1.
+	 */
+	__u32 qma;
+
+	/** Size of the tile alloc memory. */
+	__u32 qms;
+
+	/** Offset of the tile state data array. */
+	__u32 qts;
+
+	/* Pointer to a u32 array of the BOs that are referenced by the job.
+	 */
+	__u64 bo_handles;
+
+	/* Number of BO handles passed in (size is that times 4). */
+	__u32 bo_handle_count;
+
+	/* Pad, must be zero-filled. */
+	__u32 pad;
+};
+
+/**
+ * struct drm_v3d_wait_bo - ioctl argument for waiting for
+ * completion of the last DRM_V3D_SUBMIT_CL on a BO.
+ *
+ * This is useful for cases where multiple processes might be
+ * rendering to a BO and you want to wait for all rendering to be
+ * completed.
+ */
+struct drm_v3d_wait_bo {
+	__u32 handle;
+	__u32 pad;
+	__u64 timeout_ns;
+};
+
+/**
+ * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
+ *
+ * There are currently no values for the flags argument, but it may be
+ * used in a future extension.
+ */
+struct drm_v3d_create_bo {
+	__u32 size;
+	__u32 flags;
+	/** Returned GEM handle for the BO. */
+	__u32 handle;
+	/**
+	 * Returned offset for the BO in the V3D address space.  This offset
+	 * is private to the DRM fd and is valid for the lifetime of the GEM
+	 * handle.
+	 *
+	 * This offset value will always be nonzero, since various HW
+	 * units treat 0 specially.
+	 */
+	__u32 offset;
+};
+
+/**
+ * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
+ *
+ * This doesn't actually perform an mmap.  Instead, it returns the
+ * offset you need to use in an mmap on the DRM device node.  This
+ * means that tools like valgrind end up knowing about the mapped
+ * memory.
+ *
+ * There are currently no values for the flags argument, but it may be
+ * used in a future extension.
+ */
+struct drm_v3d_mmap_bo {
+	/** Handle for the object being mapped. */
+	__u32 handle;
+	__u32 flags;
+	/** offset into the drm node to use for subsequent mmap call. */
+	__u64 offset;
+};
+
+enum drm_v3d_param {
+	DRM_V3D_PARAM_V3D_UIFCFG,
+	DRM_V3D_PARAM_V3D_HUB_IDENT1,
+	DRM_V3D_PARAM_V3D_HUB_IDENT2,
+	DRM_V3D_PARAM_V3D_HUB_IDENT3,
+	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
+	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
+	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
+};
+
+struct drm_v3d_get_param {
+	__u32 param;
+	__u32 pad;
+	__u64 value;
+};
+
+/**
+ * Returns the offset for the BO in the V3D address space for this DRM fd.
+ * This is the same value returned by drm_v3d_create_bo, if that was called
+ * from this DRM fd.
+ */
+struct drm_v3d_get_bo_offset {
+	__u32 handle;
+	__u32 offset;
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _V3D_DRM_H_ */

index fee9d33ad2a5..d2aa1c19154f 100644
@@ -202,6 +202,7 @@ static const struct module {
 } modules[] = {
 	{ DRIVER_AMDGPU, "amdgpu" },
 	{ DRIVER_INTEL, "i915", modprobe_i915 },
+	{ DRIVER_V3D, "v3d" },
 	{ DRIVER_VC4, "vc4" },
 	{ DRIVER_VGEM, "vgem" },
 	{ DRIVER_VIRTIO, "virtio-gpu" },

@@ -340,6 +341,8 @@ static const char *chipset_to_str(int chipset)
 	switch (chipset) {
 	case DRIVER_INTEL:
 		return "intel";
+	case DRIVER_V3D:
+		return "v3d";
 	case DRIVER_VC4:
 		return "vc4";
 	case DRIVER_VGEM:

index 949865ee54dd..96ee517e2ec1 100644
@@ -43,6 +43,7 @@
 #define DRIVER_VGEM	(1 << 2)
 #define DRIVER_VIRTIO	(1 << 3)
 #define DRIVER_AMDGPU	(1 << 4)
+#define DRIVER_V3D	(1 << 5)
 /*
  * Exclude DRVER_VGEM from DRIVER_ANY since if you run on a system
  * with vgem as well as a supported driver, you can end up with a

130 lines not on this page · raw message

46 lines not on this page · raw message

index 1a5ede1bd5fc..619c072c0e47 100644
@@ -40,10 +40,6 @@
 #include "intel_chipset.h"
 #include "v3d_drm.h"
 
-#if NEW_CONTEXT_PARAM_NO_ERROR_CAPTURE_API
-#define LOCAL_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
-#endif
-
 /**
  * SECTION:igt_v3d
  * @short_description: V3D support library

78 lines not on this page · raw message

80 lines not on this page · raw message

55 lines not on this page · raw message

index 619c072c0e47..9a9f32e0ced4 100644
@@ -124,3 +124,129 @@ void igt_v3d_bo_mmap(int fd, struct v3d_bo *bo)
 				  PROT_READ | PROT_WRITE);
 	igt_assert(bo->map);
 }
+
+void *
+igt_v3d_wait_bo(int fd, uint32_t handle)
+{
+	struct drm_v3d_wait_bo wait_bo = {
+		.handle = handle,
+		.timeout_ns = ~0ull,
+	};
+
+	do_ioctl(fd, DRM_IOCTL_V3D_WAIT_BO, &wait_bo);
+
+	return 0;
+}
+
+void igt_v3d_bo_wait(int fd, struct v3d_bo *bo)
+{
+	igt_v3d_wait_bo(fd, bo->handle);
+}
+
+struct v3d_cl *
+igt_v3d_cl_create(int fd, size_t size)
+{
+	struct v3d_cl *cl = calloc(1, sizeof(*cl));
+
+	cl->fd = fd;
+	cl->bo = igt_v3d_create_bo(fd, size);
+	v3d_cl_reference_bo(cl, cl->bo);
+
+	igt_v3d_bo_mmap(fd, cl->bo);
+	cl->next = cl->bo->map;
+
+	return cl;
+}
+
+/** Creates a simple CL consisting of a single NOP instruction. */
+struct v3d_cl *
+igt_v3d_cl_create_nop(int fd)
+{
+	struct v3d_cl *cl = igt_v3d_cl_create(fd, 1);
+        uint8_t nop_opcode = 1;
+
+	memcpy(cl->next, &nop_opcode, 1);
+	cl->next++;
+
+	return cl;
+}
+
+/**
+ * Creates a simple CL consisting of an infinite loop branching to itself.
+ */
+struct v3d_cl *
+igt_v3d_cl_create_infinite_loop(int fd)
+{
+	struct v3d_cl *cl = igt_v3d_cl_create(fd, 5);
+        uint8_t branch_opcode = 16;
+
+	memcpy(cl->next, &branch_opcode, 1);
+	cl->next++;
+
+	memcpy(cl->next, &cl->bo->offset, 4);
+	cl->next += 4;
+
+	return cl;
+}
+
+void
+igt_v3d_cl_free(struct v3d_cl *cl)
+{
+	igt_v3d_free_bo(cl->fd, cl->bo);
+	free(cl);
+}
+
+void
+igt_v3d_submit_cl(int fd, struct drm_v3d_submit_cl *submit)
+{
+	do_ioctl(fd, DRM_IOCTL_V3D_SUBMIT_CL, submit);
+}
+
+void
+igt_v3d_submit_rcl(struct v3d_cl *rcl)
+{
+	struct drm_v3d_submit_cl submit = {
+		.rcl_start = rcl->bo->offset,
+		.rcl_end = rcl->bo->offset + cl_offset(rcl),
+		.bo_handles = (uintptr_t)rcl->handles,
+		.bo_handle_count = rcl->handle_count,
+	};
+	igt_v3d_submit_cl(rcl->fd, &submit);
+}
+
+static bool
+handle_in_list(uint32_t *handles, int handle_count, int handle)
+{
+	for (int i = 0; i < handle_count; i++) {
+		if (handles[i] == handle)
+			return true;
+	}
+	return false;
+}
+
+void
+igt_v3d_submit_bcl_and_rcl(struct v3d_cl *bcl, struct v3d_cl *rcl)
+{
+	uint32_t handles[32];
+	int handle_count = 0;
+
+	/* Merge the two incoming handle lists. */
+	igt_assert(rcl->handle_count + bcl->handle_count <= ARRAY_SIZE(handles));
+	for (int i = 0; i < rcl->handle_count; i++)
+		handles[handle_count++] = rcl->handles[i];
+
+	for (int i = 0; i < bcl->handle_count; i++) {
+		if (!handle_in_list(handles, handle_count, bcl->handles[i]))
+			handles[handle_count++] = bcl->handles[i];
+	}
+
+	struct drm_v3d_submit_cl submit = {
+		.rcl_start = rcl->bo->offset,
+		.rcl_end = rcl->bo->offset + cl_offset(rcl),
+		.bcl_start = bcl->bo->offset,
+		.bcl_end = bcl->bo->offset + cl_offset(bcl),
+		.bo_handles = (uintptr_t)handles,
+		.bo_handle_count = handle_count,
+	};
+	igt_v3d_submit_cl(rcl->fd, &submit);
+}

index 2042995103cc..7ddbee36a547 100644
@@ -33,6 +33,15 @@ struct v3d_bo {
 	void *map;
 };
 
+struct v3d_cl {
+	int fd;
+	struct v3d_bo *bo;
+	void *next;
+
+	uint32_t handles[32];
+	uint32_t handle_count;
+};
+
 struct v3d_bo *igt_v3d_create_bo(int fd, size_t size);
 void igt_v3d_free_bo(int fd, struct v3d_bo *bo);
 

@@ -40,7 +49,36 @@ void igt_v3d_free_bo(int fd, struct v3d_bo *bo);
 uint32_t igt_v3d_get_bo_offset(int fd, uint32_t handle);
 uint32_t igt_v3d_get_param(int fd, enum drm_v3d_param param);
 void *igt_v3d_mmap_bo(int fd, uint32_t handle, uint32_t size, unsigned prot);
+void *igt_v3d_wait_bo(int fd, uint32_t handle);
+void igt_v3d_submit_cl(int fd, struct drm_v3d_submit_cl *submit);
+void igt_v3d_submit_rcl(struct v3d_cl *rcl);
+void igt_v3d_submit_bcl_and_rcl(struct v3d_cl *bcl, struct v3d_cl *rcl);
 
 void igt_v3d_bo_mmap(int fd, struct v3d_bo *bo);
+void igt_v3d_bo_wait(int fd, struct v3d_bo *bo);
+
+static inline void v3d_cl_reference_bo(struct v3d_cl *cl,
+				       const struct v3d_bo *bo)
+{
+	if (!bo)
+		return;
+
+	for (int i = 0; i < cl->handle_count; i++) {
+		if (cl->handles[i] == bo->handle)
+			return;
+	}
+
+	cl->handles[cl->handle_count++] = bo->handle;
+}
+
+static inline uint32_t cl_offset(struct v3d_cl *cl)
+{
+	return (char *)cl->next - (char *)cl->bo->map;
+}
+
+struct v3d_cl *igt_v3d_cl_create(int fd, size_t size);
+struct v3d_cl *igt_v3d_cl_create_infinite_loop(int fd);
+struct v3d_cl *igt_v3d_cl_create_nop(int fd);
+void igt_v3d_cl_free(struct v3d_cl *cl);
 
 #endif /* IGT_V3D_H */

70 lines not on this page · raw message