ARM: vexpress-ca9x4_defconfig: Enable CMD_UBI support

PATCH New Otavio Salvador 5 participants 13 messages Oct 23, 2018 – Dec 2, 2018

Subsystems (6)

Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +2 more subsystems

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Otavio Salvador

author

2018-10-23 13:35 UTC #0 lore raw

PATCH v2 1/6 ARM: vexpress-ca9x4_defconfig: Enable CMD_UBI support

This allow for convenient use of QEMU machine to test loading of UBI filesystem.

Acked-by Linus Walleij <[email protected]>

Signed-off-by Otavio Salvador <[email protected]>

---

Changes in v2: None

 configs/vexpress_ca9x4_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/vexpress_ca9x4_defconfig +1 -0

index d3c23dee17..9ca542b0f2 100644
@@ -17,6 +17,7 @@ CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y

Signature · 1 line

2.19.1

Otavio Salvador

author

2018-10-23 13:35 UTC #1 lore raw

PATCH v2 2/6 ARM: rpi_*_defconfig: Add support to find UUID for filesystem

The most generic way of having a stable boot behavior is to rely on UUID instead of device names for root partition, so the order of probing does not cause issues with booting.

This enables the CMD_FS_UUID for following defconfig files:

- rpi_0_w_defconfig
- rpi_2_defconfig
- rpi_3_32b_defconfig
- rpi_3_defconfig
- rpi_defconfig

Signed-off-by Otavio Salvador <[email protected]>

Signed-off-by Fabio Berton <[email protected]>

---

Changes in v2:
- rework commit

 configs/rpi_0_w_defconfig   | 1 +
 configs/rpi_2_defconfig     | 1 +
 configs/rpi_3_32b_defconfig | 1 +
 configs/rpi_3_defconfig     | 1 +
 configs/rpi_defconfig       | 1 +
 5 files changed, 5 insertions(+)

configs/rpi_0_w_defconfig +1 -0

index d5bf01b76e..66b0de31b6 100644
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
 CONFIG_ENV_FAT_INTERFACE="mmc"

configs/rpi_2_defconfig +1 -0

index a50a815759..ba75e52dda 100644
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
 CONFIG_ENV_FAT_INTERFACE="mmc"

configs/rpi_3_32b_defconfig +1 -0

index d3d4596ba0..33c476bb4f 100644
@@ -14,6 +14,7 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
 CONFIG_ENV_FAT_INTERFACE="mmc"

configs/rpi_3_defconfig +1 -0

index ac99f2000a..54b6303c2d 100644
@@ -14,6 +14,7 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
 CONFIG_ENV_FAT_INTERFACE="mmc"

configs/rpi_defconfig +1 -0

index db42ffd135..e7820cb147 100644
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
 CONFIG_ENV_FAT_INTERFACE="mmc"

Signature · 1 line

2.19.1

Alexander Graf

Applied

2018-12-02 22:00 UTC #2 lore raw

PATCH v2 2/6 ARM: rpi_*_defconfig: Add support to find UUID for filesystem

Quoted 6 lines

The most generic way of having a stable boot behavior is to rely on UUID instead of device names for root partition, so the order of probing does not cause issues with booting.
This enables the CMD_FS_UUID for following defconfig files:

Quoted 8 lines

- rpi_0_w_defconfig
- rpi_2_defconfig
- rpi_3_32b_defconfig
- rpi_3_defconfig
- rpi_defconfig
Signed-off-by Otavio Salvador <[email protected]>
Signed-off-by Fabio Berton <[email protected]>

Thanks, applied to rpi-next

Alex

Otavio Salvador

2018-12-02 22:33 UTC #3 lore raw

PATCH v2 2/6 ARM: rpi_*_defconfig: Add support to find UUID for filesystem

Quoted 13 lines · Alexander Graf

Quoted 13 lines
The most generic way of having a stable boot behavior is to rely on UUID instead of device names for root partition, so the order of probing does not cause issues with booting.
This enables the CMD_FS_UUID for following defconfig files:
- rpi_0_w_defconfig
- rpi_2_defconfig
- rpi_3_32b_defconfig
- rpi_3_defconfig
- rpi_defconfig

Quoted 4 lines

Quoted 2 lines
Signed-off-by Otavio Salvador <[email protected]>
Signed-off-by Fabio Berton <[email protected]>
Thanks, applied to rpi-next

Couldn't this be applied for 2019.01 release?

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750

Alexander Graf

2018-12-02 22:36 UTC #4 lore raw

PATCH v2 2/6 ARM: rpi_*_defconfig: Add support to find UUID for filesystem

Quoted 14 lines · Otavio Salvador

Quoted 13 lines · Alexander Graf
Quoted 13 lines
The most generic way of having a stable boot behavior is to rely on UUID instead of device names for root partition, so the order of probing does not cause issues with booting.
This enables the CMD_FS_UUID for following defconfig files:
- rpi_0_w_defconfig
- rpi_2_defconfig
- rpi_3_32b_defconfig
- rpi_3_defconfig
- rpi_defconfig

Quoted 6 lines

Quoted 4 lines
Quoted 2 lines
Signed-off-by Otavio Salvador <[email protected]>
Signed-off-by Fabio Berton <[email protected]>
Thanks, applied to rpi-next
Couldn't this be applied for 2019.01 release?

That's what rpi-next is going to end up in, yes.

Alex

Otavio Salvador

author

2018-10-23 13:35 UTC #5 lore raw

PATCH v2 3/6 clk_rv1108: Sync with vendor tree

In reply to Otavio Salvador

Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version.

Signed-off-by Otavio Salvador <[email protected]>

---

Changes in v2: None

 .../include/asm/arch-rockchip/cru_rv1108.h    | 143 +++++-
 drivers/clk/rockchip/clk_rv1108.c             | 457 +++++++++++++++++-
 include/dt-bindings/clock/rv1108-cru.h        | 154 ++++--
 3 files changed, 706 insertions(+), 48 deletions(-)

arch/arm/include/asm/arch-rockchip/cru_rv1108.h +142 -1

index 3cc2ed0187..4ce8caa40f 100644
@@ -11,7 +11,11 @@
 #define OSC_HZ		(24 * 1000 * 1000)
 
 #define APLL_HZ		(600 * 1000000)
-#define GPLL_HZ		(594 * 1000000)
+#define GPLL_HZ		(1188 * 1000000)
+#define ACLK_PERI_HZ	(148500000)
+#define HCLK_PERI_HZ	(148500000)
+#define PCLK_PERI_HZ	(74250000)
+#define ACLK_BUS_HZ	(148500000)
 
 struct rv1108_clk_priv {
 	struct rv1108_cru *cru;

@@ -80,6 +84,11 @@ enum {
 	WORK_MODE_NORMAL	= 1,
 	DSMPD_SHIFT             = 3,
 	DSMPD_MASK		= 1 << DSMPD_SHIFT,
+	INTEGER_MODE			= 1,
+	GLOBAL_POWER_DOWN_SHIFT		= 0,
+	GLOBAL_POWER_DOWN_MASK		= 1 << GLOBAL_POWER_DOWN_SHIFT,
+	GLOBAL_POWER_DOWN		= 1,
+	GLOBAL_POWER_UP			= 0,
 
 	/* CLKSEL0_CON */
 	CORE_PLL_SEL_SHIFT	= 8,

@@ -90,11 +99,77 @@ enum {
 	CORE_CLK_DIV_SHIFT	= 0,
 	CORE_CLK_DIV_MASK	= 0x1f << CORE_CLK_DIV_SHIFT,
 
+	/* CLKSEL_CON1 */
+	PCLK_DBG_DIV_CON_SHIFT		= 4,
+	PCLK_DBG_DIV_CON_MASK		= 0xf << PCLK_DBG_DIV_CON_SHIFT,
+	ACLK_CORE_DIV_CON_SHIFT		= 0,
+	ACLK_CORE_DIV_CON_MASK		= 7 << ACLK_CORE_DIV_CON_SHIFT,
+
+	/* CLKSEL_CON2 */
+	ACLK_BUS_PLL_SEL_SHIFT		= 8,
+	ACLK_BUS_PLL_SEL_MASK		= 3 << ACLK_BUS_PLL_SEL_SHIFT,
+	ACLK_BUS_PLL_SEL_GPLL		= 0,
+	ACLK_BUS_PLL_SEL_APLL		= 1,
+	ACLK_BUS_PLL_SEL_DPLL		= 2,
+	ACLK_BUS_DIV_CON_SHIFT		= 0,
+	ACLK_BUS_DIV_CON_MASK		= 0x1f << ACLK_BUS_DIV_CON_SHIFT,
+	ACLK_BUS_DIV_CON_WIDTH		= 5,
+
+	/* CLKSEL_CON3 */
+	PCLK_BUS_DIV_CON_SHIFT		= 8,
+	PCLK_BUS_DIV_CON_MASK		= 0x1f << PCLK_BUS_DIV_CON_SHIFT,
+	HCLK_BUS_DIV_CON_SHIFT		= 0,
+	HCLK_BUS_DIV_CON_MASK		= 0x1f,
+
+	/* CLKSEL_CON4 */
+	CLK_DDR_PLL_SEL_SHIFT		= 8,
+	CLK_DDR_PLL_SEL_MASK		= 0x3 << CLK_DDR_PLL_SEL_SHIFT,
+	CLK_DDR_DIV_CON_SHIFT		= 0,
+	CLK_DDR_DIV_CON_MASK		= 0x3 << CLK_DDR_DIV_CON_SHIFT,
+
+	/* CLKSEL_CON19 */
+	CLK_I2C1_PLL_SEL_SHIFT		= 15,
+	CLK_I2C1_PLL_SEL_MASK		= 1 << CLK_I2C1_PLL_SEL_SHIFT,
+	CLK_I2C1_PLL_SEL_DPLL		= 0,
+	CLK_I2C1_PLL_SEL_GPLL		= 1,
+	CLK_I2C1_DIV_CON_SHIFT		= 8,
+	CLK_I2C1_DIV_CON_MASK		= 0x7f << CLK_I2C1_DIV_CON_SHIFT,
+	CLK_I2C0_PLL_SEL_SHIFT		= 7,
+	CLK_I2C0_PLL_SEL_MASK		= 1 << CLK_I2C0_PLL_SEL_SHIFT,
+	CLK_I2C0_DIV_CON_SHIFT		= 0,
+	CLK_I2C0_DIV_CON_MASK		= 0x7f,
+	I2C_DIV_CON_WIDTH		= 7,
+
+	/* CLKSEL_CON20 */
+	CLK_I2C3_PLL_SEL_SHIFT		= 15,
+	CLK_I2C3_PLL_SEL_MASK		= 1 << CLK_I2C3_PLL_SEL_SHIFT,
+	CLK_I2C3_PLL_SEL_DPLL		= 0,
+	CLK_I2C3_PLL_SEL_GPLL		= 1,
+	CLK_I2C3_DIV_CON_SHIFT		= 8,
+	CLK_I2C3_DIV_CON_MASK		= 0x7f << CLK_I2C3_DIV_CON_SHIFT,
+	CLK_I2C2_PLL_SEL_SHIFT		= 7,
+	CLK_I2C2_PLL_SEL_MASK		= 1 << CLK_I2C2_PLL_SEL_SHIFT,
+	CLK_I2C2_DIV_CON_SHIFT		= 0,
+	CLK_I2C2_DIV_CON_MASK		= 0x7f,
+
 	/* CLKSEL_CON22 */
 	CLK_SARADC_DIV_CON_SHIFT= 0,
 	CLK_SARADC_DIV_CON_MASK	= GENMASK(9, 0),
 	CLK_SARADC_DIV_CON_WIDTH= 10,
 
+	/* CLKSEL_CON23 */
+	ACLK_PERI_PLL_SEL_SHIFT		= 15,
+	ACLK_PERI_PLL_SEL_MASK		= 1 << ACLK_PERI_PLL_SEL_SHIFT,
+	ACLK_PERI_PLL_SEL_GPLL		= 0,
+	ACLK_PERI_PLL_SEL_DPLL		= 1,
+	PCLK_PERI_DIV_CON_SHIFT		= 10,
+	PCLK_PERI_DIV_CON_MASK		= 0x1f << PCLK_PERI_DIV_CON_SHIFT,
+	HCLK_PERI_DIV_CON_SHIFT		= 5,
+	HCLK_PERI_DIV_CON_MASK		= 0x1f << HCLK_PERI_DIV_CON_SHIFT,
+	ACLK_PERI_DIV_CON_SHIFT		= 0,
+	ACLK_PERI_DIV_CON_MASK		= 0x1f,
+	PERI_DIV_CON_WIDTH		= 5,
+
 	/* CLKSEL24_CON */
 	MAC_PLL_SEL_SHIFT	= 12,
 	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,

@@ -105,6 +180,16 @@ enum {
 	MAC_CLK_DIV_MASK	= 0x1f,
 	MAC_CLK_DIV_SHIFT	= 0,
 
+	/* CLKSEL25_CON */
+	EMMC_PLL_SEL_SHIFT	= 12,
+	EMMC_PLL_SEL_MASK	= 3 << EMMC_PLL_SEL_SHIFT,
+	EMMC_PLL_SEL_DPLL	= 0,
+	EMMC_PLL_SEL_GPLL,
+
+	/* CLKSEL26_CON */
+	EMMC_CLK_DIV_SHIFT	= 8,
+	EMMC_CLK_DIV_MASK	= 0xff << EMMC_CLK_DIV_SHIFT,
+
 	/* CLKSEL27_CON */
 	SFC_PLL_SEL_SHIFT	= 7,
 	SFC_PLL_SEL_MASK	= 1 << SFC_PLL_SEL_SHIFT,

@@ -112,5 +197,61 @@ enum {
 	SFC_PLL_SEL_GPLL	= 1,
 	SFC_CLK_DIV_SHIFT	= 0,
 	SFC_CLK_DIV_MASK	= 0x3f << SFC_CLK_DIV_SHIFT,
+
+	/* CLKSEL28_CON */
+	ACLK_VIO1_PLL_SEL_SHIFT		= 14,
+	ACLK_VIO1_PLL_SEL_MASK		= 3 << ACLK_VIO1_PLL_SEL_SHIFT,
+	VIO_PLL_SEL_DPLL		= 0,
+	VIO_PLL_SEL_GPLL		= 1,
+	ACLK_VIO1_CLK_DIV_SHIFT		= 8,
+	ACLK_VIO1_CLK_DIV_MASK		= 0x1f << ACLK_VIO1_CLK_DIV_SHIFT,
+	CLK_VIO_DIV_CON_WIDTH		= 5,
+	ACLK_VIO0_PLL_SEL_SHIFT		= 6,
+	ACLK_VIO0_PLL_SEL_MASK		= 3 << ACLK_VIO0_PLL_SEL_SHIFT,
+	ACLK_VIO0_CLK_DIV_SHIFT		= 0,
+	ACLK_VIO0_CLK_DIV_MASK		= 0x1f << ACLK_VIO0_CLK_DIV_SHIFT,
+
+	/* CLKSEL29_CON */
+	PCLK_VIO_CLK_DIV_SHIFT		= 8,
+	PCLK_VIO_CLK_DIV_MASK		= 0x1f << PCLK_VIO_CLK_DIV_SHIFT,
+	HCLK_VIO_CLK_DIV_SHIFT		= 0,
+	HCLK_VIO_CLK_DIV_MASK		= 0x1f << HCLK_VIO_CLK_DIV_SHIFT,
+
+	/* CLKSEL32_CON */
+	DCLK_VOP_SEL_SHIFT		= 7,
+	DCLK_VOP_SEL_MASK		= 1 << DCLK_VOP_SEL_SHIFT,
+	DCLK_VOP_SEL_HDMI		= 0,
+	DCLK_VOP_SEL_PLL		= 1,
+	DCLK_VOP_PLL_SEL_SHIFT		= 6,
+	DCLK_VOP_PLL_SEL_MASK		= 1 << DCLK_VOP_PLL_SEL_SHIFT,
+	DCLK_VOP_PLL_SEL_GPLL		= 0,
+	DCLK_VOP_PLL_SEL_DPLL		= 1,
+	DCLK_VOP_CLK_DIV_SHIFT		= 0,
+	DCLK_VOP_CLK_DIV_MASK		= 0x3f << DCLK_VOP_CLK_DIV_SHIFT,
+	DCLK_VOP_DIV_CON_WIDTH		= 6,
+
+	/* SOFTRST1_CON*/
+	DDRPHY_SRSTN_CLKDIV_REQ_SHIFT	= 0,
+	DDRPHY_SRSTN_CLKDIV_REQ		= 1,
+	DDRPHY_SRSTN_CLKDIV_DIS		= 0,
+	DDRPHY_SRSTN_CLKDIV_REQ_MASK	= 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT,
+	DDRPHY_SRSTN_REQ_SHIFT		= 1,
+	DDRPHY_SRSTN_REQ		= 1,
+	DDRPHY_SRSTN_DIS		= 0,
+	DDRPHY_SRSTN_REQ_MASK		= 1 << DDRPHY_SRSTN_REQ_SHIFT,
+	DDRPHY_PSRSTN_REQ_SHIFT		= 2,
+	DDRPHY_PSRSTN_REQ		= 1,
+	DDRPHY_PSRSTN_DIS		= 0,
+	DDRPHY_PSRSTN_REQ_MASK		= 1 << DDRPHY_PSRSTN_REQ_SHIFT,
+
+	/* SOFTRST2_CON*/
+	DDRUPCTL_PSRSTN_REQ_SHIFT	= 0,
+	DDRUPCTL_PSRSTN_REQ		= 1,
+	DDRUPCTL_PSRSTN_DIS		= 0,
+	DDRUPCTL_PSRSTN_REQ_MASK	= 1 << DDRUPCTL_PSRSTN_REQ_SHIFT,
+	DDRUPCTL_NSRSTN_REQ_SHIFT	= 1,
+	DDRUPCTL_NSRSTN_REQ		= 1,
+	DDRUPCTL_NSRSTN_DIS		= 0,
+	DDRUPCTL_NSRSTN_REQ_MASK	= 1 << DDRUPCTL_NSRSTN_REQ_SHIFT,
 };
 #endif

drivers/clk/rockchip/clk_rv1108.c +453 -4

504 lines not on this page · raw message

include/dt-bindings/clock/rv1108-cru.h +111 ~~-43~~

235 lines not on this page · raw message

Signature · 1 line

2.19.1

Otavio Salvador

author

2018-10-23 13:35 UTC #6 lore raw

PATCH v2 4/6 rv1108: Enable eMMC support

In reply to Otavio Salvador

In order to be able to build the Rockchip eMMC driver on rv1108, the CONFIG_BOUNCE_BUFFER option needs to be selected.

Select it like it is done on the other Rockchip SoC common files.

This also adds the pinctrl handles to enable the use of eMMC on custom boards (as minievk) and makes it easier for later addition.

Signed-off-by Otavio Salvador <[email protected]>

---

Changes in v2: None

 arch/arm/dts/rv1108.dtsi        | 29 +++++++++++++++++++++++++++++
 include/configs/rv1108_common.h |  3 +++
 2 files changed, 32 insertions(+)

arch/arm/dts/rv1108.dtsi +29 -0

index acfd97e18d..23a44bfaca 100644
@@ -427,6 +427,35 @@
 			};
 		};
 
+		emmc {
+			emmc_clk: emmc-clk {
+				rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+			};
+
+			emmc_cmd: emmc-cmd {
+				rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+			};
+
+			emmc_pwren: emmc-pwren {
+				rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+			};
+
+			emmc_bus1: emmc-bus1 {
+				rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+			};
+
+			emmc_bus8: emmc-bus8 {
+				rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+						<2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+			};
+		};
+
 		sdmmc {
 			sdmmc_clk: sdmmc-clk {
 				rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;

include/configs/rv1108_common.h +3 -0

index 2ab3b85e0c..cc0384e2f4 100644
@@ -17,6 +17,9 @@
 #define CONFIG_SYS_TIMER_BASE		0x10350020
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x2000000)

Signature · 1 line

2.19.1

Otavio Salvador

author

2018-10-23 13:35 UTC #7 lore raw

PATCH v2 5/6 rv1108: Make USB OTG functional

In reply to Otavio Salvador

Like it is done for other Rockchip SoCs, introduce a board_usb_init() function so that USB OTG can be functional on rv1108 too.

Signed-off-by Otavio Salvador <[email protected]>

---

Changes in v2: None

 arch/arm/dts/rv1108.dtsi              | 45 ++++++++++++++-
 arch/arm/mach-rockchip/Makefile       |  1 +
 arch/arm/mach-rockchip/rv1108-board.c | 81 +++++++++++++++++++++++++++
 3 files changed, 124 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rv1108-board.c

arch/arm/dts/rv1108.dtsi +42 -3

index 23a44bfaca..215d885225 100644
@@ -121,8 +121,35 @@
 	};
 
 	grf: syscon at 10300000 {
-		compatible = "rockchip,rv1108-grf", "syscon";
+		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
 		reg = <0x10300000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy: usb2-phy at 100 {
+			compatible = "rockchip,rv1108-usb2phy";
+			reg = <0x100 0x0c>;
+			clocks = <&cru SCLK_USBPHY>;
+			clock-names = "phyclk";
+			#clock-cells = <0>;
+			clock-output-names = "usbphy";
+			rockchip,usbgrf = <&usbgrf>;
+			status = "disabled";
+
+			u2phy_otg: otg-port {
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-mux";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			u2phy_host: host-port {
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
 	};
 
 	saradc: saradc at 1038c000 {

@@ -141,6 +168,11 @@
 		reg = <0x20060000 0x1000>;
 	};
 
+	usbgrf: syscon at 202a0000 {
+		compatible = "rockchip,rv1108-usbgrf", "syscon";
+		reg = <0x202a0000 0x1000>;
+	};
+
 	cru: clock-controller at 20200000 {
 		compatible = "rockchip,rv1108-cru";
 		reg = <0x20200000 0x1000>;

@@ -200,12 +232,19 @@
 	};
 
 	usb20_otg: usb at 30180000 {
-		compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
+		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
 			     "snps,dwc2";
 		reg = <0x30180000 0x40000>;
 		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-		hnp-srp-disable;
+		clocks = <&cru HCLK_OTG>;
+		clock-names = "otg";
 		dr_mode = "otg";
+		g-np-tx-fifo-size = <16>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
+		g-use-dma;
+		phys = <&u2phy_otg>;
+		phy-names = "usb2-phy";
 		status = "disabled";
 	};

arch/arm/mach-rockchip/Makefile +1 -0

index 05706c472a..368302e1da 100644
@@ -33,6 +33,7 @@ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
+obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o
 endif
 
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o

arch/arm/mach-rockchip/rv1108-board.c new file +81 -0

81 lines not on this page · raw message

Signature · 1 line

2.19.1

Otavio Salvador

author

2018-10-23 13:35 UTC #8 lore raw

PATCH v2 6/6 rv1108: Add support for default distro_bootcmd

In reply to Otavio Salvador

This allow easier integration of RV1108 based boards on generic distributions and build systems.

Signed-off-by Otavio Salvador <[email protected]>

---

Changes in v2:
- new patch

 include/configs/rv1108_common.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

include/configs/rv1108_common.h +14 -0

index cc0384e2f4..99aa56ab35 100644
@@ -28,3 +28,17 @@
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
 #endif
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	"partitions=" PARTS_DEFAULT \
+	BOOTENV
+#endif

Signature · 1 line

2.19.1

Tom Rini

NAK

2018-11-16 15:03 UTC #9 lore raw

PATCH v2 1/6 ARM: vexpress-ca9x4_defconfig: Enable CMD_UBI support

In reply to Otavio Salvador

Quoted 5 lines · Otavio Salvador

This allow for convenient use of QEMU machine to test loading of UBI filesystem.
Acked-by Linus Walleij <[email protected]>
Signed-off-by Otavio Salvador <[email protected]>

NAK:
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s vexpress_ca9x4_defconfig
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s -j8
09:59:16 ../drivers/mtd/ubi/build.c:57:2: error: #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k 09:59:16 #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k
09:59:16 ^~~~~
09:59:16 ../scripts/Makefile.build:278: recipe for target 'drivers/mtd/ubi/build.o' failed

Signature · 8 lines

Tom
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Otavio Salvador

2018-11-16 16:42 UTC #10 lore raw

PATCH v2 1/6 ARM: vexpress-ca9x4_defconfig: Enable CMD_UBI support

Quoted 7 lines · Tom Rini

Quoted 5 lines · Otavio Salvador
This allow for convenient use of QEMU machine to test loading of UBI filesystem.
Acked-by Linus Walleij <[email protected]>
Signed-off-by Otavio Salvador <[email protected]>

Quoted 7 lines

NAK:
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s vexpress_ca9x4_defconfig
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s -j8
09:59:16 ../drivers/mtd/ubi/build.c:57:2: error: #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k 09:59:16 #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k
09:59:16 ^~~~~
09:59:16 ../scripts/Makefile.build:278: recipe for target 'drivers/mtd/ubi/build.o' failed

It used to work fine, it is likely a side effect of a new change.

Linus, it is fine for me to update the malloc length?

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750

Linus Walleij

2018-11-18 19:13 UTC #11 lore raw

PATCH v2 1/6 ARM: vexpress-ca9x4_defconfig: Enable CMD_UBI support

Quoted 16 lines · Otavio Salvador

Quoted 7 lines · Tom Rini
Quoted 5 lines · Otavio Salvador
This allow for convenient use of QEMU machine to test loading of UBI filesystem.
Acked-by Linus Walleij <[email protected]>
Signed-off-by Otavio Salvador <[email protected]>
Quoted 7 lines
NAK:
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s vexpress_ca9x4_defconfig
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s -j8
09:59:16 ../drivers/mtd/ubi/build.c:57:2: error: #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k 09:59:16 #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k
09:59:16 ^~~~~
09:59:16 ../scripts/Makefile.build:278: recipe for target 'drivers/mtd/ubi/build.o' failed

Quoted 3 lines

It used to work fine, it is likely a side effect of a new change.
Linus, it is fine for me to update the malloc length?

I THINK so but check with the ARM people!

I guess, just send a patch for it and see what they say :D

Yours,
Linus Walleij

Otavio Salvador

2018-11-18 20:51 UTC #12 lore raw

PATCH v2 1/6 ARM: vexpress-ca9x4_defconfig: Enable CMD_UBI support

Quoted 19 lines · Linus Walleij

Quoted 16 lines · Otavio Salvador
Quoted 14 lines · Tom Rini
Quoted 5 lines · Otavio Salvador
This allow for convenient use of QEMU machine to test loading of UBI filesystem.
Acked-by Linus Walleij <[email protected]>
Signed-off-by Otavio Salvador <[email protected]>
NAK:
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s vexpress_ca9x4_defconfig
09:59:16 +make O=/home/jenkins/u-boot/build-vexpress_ca9x4 -s -j8
09:59:16 ../drivers/mtd/ubi/build.c:57:2: error: #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k 09:59:16 #error Malloc area too small for UBI, increase CONFIG_SYS_MALLOC_LEN to >= 512k
09:59:16 ^~~~~
09:59:16 ../scripts/Makefile.build:278: recipe for target 'drivers/mtd/ubi/build.o' failed

Quoted 7 lines

Quoted 3 lines
It used to work fine, it is likely a side effect of a new change.
Linus, it is fine for me to update the malloc length?
I THINK so but check with the ARM people!
I guess, just send a patch for it and see what they say :D

I prepared a new patch which does this to all vexpress configurations, so it doesn't diverges.

Please take a look and let me know what do you think.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854          Mobile: +1 (347) 903-9750