drm/amdgpu: enable paging queue doorbell support v3
Subsystems (2)
PATCH 1/1 drm/amdgpu: enable paging queue doorbell support v3
Because increase SDMA_DOORBELL_RANGE to add new SDMA doorbell for paging queue will break SRIOV, instead we can reserve and map two doorbell pages for amdgpu, paging queues doorbell index use same index as SDMA gfx queues index but on second page.
For Vega20, after we change doorbell layout to increase SDMA doorbell for 8 SDMA RLC queues later, we could use new doorbell index for paging queue.
--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +++++++++++++--------- 2 files changed, 33 insertions(+), 13 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +13 -0
@@ -534,6 +534,19 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)if (adev->doorbell.num_doorbells ==0 )return -EINVAL ; +/* For Vega, reserve and map two pages on doorbell BAR since SDMA +* paging queue doorbell use the second page +*/ +switch (adev->asic_type) { +case CHIP_VEGA10 : +case CHIP_VEGA12 : +case CHIP_VEGA20 : + adev->doorbell.num_doorbells *=2 ; +break ; +default : +break ; + } + adev->doorbell.ptr =ioremap (adev->doorbell.base, adev->doorbell.num_doorbells *sizeof (u32));
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +20 -13
@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) OFFSET, ring->doorbell_index);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL, doorbell);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); -/* TODO: enable doorbell support */ -/*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, -ring->doorbell_index);*/ -sdma_v4_0_ring_set_wptr (ring); +/* paging queue doorbell index is already enabled at sdma_v4_0_gfx_resume */ +sdma_v4_0_page_ring_set_wptr (ring);/* set minor_ptr_update to 0 after wptr programed */ WREG32_SDMA (i, mmSDMA0_PAGE_MINOR_PTR_UPDATE,0 );
@@ -1504,18 +1502,14 @@ static int sdma_v4_0_sw_init(void *handle) ring->ring_obj =NULL ; ring->use_doorbell = true; -DRM_INFO ("use_doorbell being set to: [%s]\n" , - ring->use_doorbell?"true" :"false" ); -if (adev->asic_type ==CHIP_VEGA10 ) ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords else ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset - + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords sprintf (ring->name,"sdma%d" , i); r = amdgpu_ring_init(adev, ring, 1024,
@@ -1529,7 +1523,20 @@ static int sdma_v4_0_sw_init(void *handle)if (adev->sdma.has_page_queue) { ring = &adev->sdma.instance[i].page; ring->ring_obj =NULL ; - ring->use_doorbell = false; + ring->use_doorbell = true; + +/* paging queue use same doorbell index/routing as gfx queue +* with 0x400 (4096 dwords) offset on second doorbell page +*/ +if (adev->asic_type ==CHIP_VEGA10 ) + ring->doorbell_index = (i ==0 ) ? + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); +else + ring->doorbell_index = (i ==0 ) ? + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index +=0x400 ;sprintf (ring->name,"page%d" , i); r = amdgpu_ring_init(adev, ring, 1024,
Signature · 6 lines
2.17.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Looks good to me. Reviewed-by: Felix Kuehling <[email protected]>
I hope Alex or Christian can also review this in case I'm missing something about how doorbells are used in amdgpu.
Regards,
Felix
Quoted 91 lines · Philip
Because increase
SDMA_DOORBELL_RANGEto add new SDMA doorbell for paging queue will break SRIOV, instead we can reserve and map two doorbell pages for amdgpu, paging queues doorbell index use same index as SDMA gfx queues index but on second page.For Vega20, after we change doorbell layout to increase SDMA doorbell for 8 SDMA RLC queues later, we could use new doorbell index for paging queue.
Change-Id I9adb965f16ee4089d261d9a22231337739184e49Signed-off-by Philip Yang <[email protected]>--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +++++++++++++--------- 2 files changed, 33 insertions(+), 13 deletions(-)drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +13
-0@@ -534,6 +534,19 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)if (adev->doorbell.num_doorbells ==0 )return -EINVAL ; +/* For Vega, reserve and map two pages on doorbell BAR since SDMA +* paging queue doorbell use the second page +*/ +switch (adev->asic_type) { +case CHIP_VEGA10 : +case CHIP_VEGA12 : +case CHIP_VEGA20 : + adev->doorbell.num_doorbells *=2 ; +break ; +default : +break ; + } + adev->doorbell.ptr =ioremap (adev->doorbell.base, adev->doorbell.num_doorbells *sizeof (u32));drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +13
-13@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) OFFSET, ring->doorbell_index);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL, doorbell);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); -/* TODO: enable doorbell support */ -/*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, -ring->doorbell_index);*/ -sdma_v4_0_ring_set_wptr (ring); +/* paging queue doorbell index is already enabled at sdma_v4_0_gfx_resume */ +sdma_v4_0_page_ring_set_wptr (ring);/* set minor_ptr_update to 0 after wptr programed */ WREG32_SDMA (i, mmSDMA0_PAGE_MINOR_PTR_UPDATE,0 );@@ -1504,18 +1502,14 @@ static int sdma_v4_0_sw_init(void *handle) ring->ring_obj =NULL ; ring->use_doorbell = true; -DRM_INFO ("use_doorbell being set to: [%s]\n" , - ring->use_doorbell?"true" :"false" ); -if (adev->asic_type ==CHIP_VEGA10 ) ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords else ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset - + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords sprintf (ring->name,"sdma%d" , i); r = amdgpu_ring_init(adev, ring, 1024,@@ -1529,7 +1523,20 @@ static int sdma_v4_0_sw_init(void *handle)if (adev->sdma.has_page_queue) { ring = &adev->sdma.instance[i].page; ring->ring_obj =NULL ; - ring->use_doorbell = false; + ring->use_doorbell = true; + +/* paging queue use same doorbell index/routing as gfx queue +* with 0x400 (4096 dwords) offset on second doorbell page +*/ +if (adev->asic_type ==CHIP_VEGA10 ) + ring->doorbell_index = (i == 0) ?
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static int sdma_v4_0_sw_init(void *handle) · line 1542
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +7
-0+ (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); + else + ring->doorbell_index = (i == 0) ? + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index +=0x400 ;sprintf (ring->name,"page%d" , i); r = amdgpu_ring_init(adev, ring, 1024,
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Quoted 26 lines · Philip
Because increase
SDMA_DOORBELL_RANGEto add new SDMA doorbell for paging queue will break SRIOV, instead we can reserve and map two doorbell pages for amdgpu, paging queues doorbell index use same index as SDMA gfx queues index but on second page.For Vega20, after we change doorbell layout to increase SDMA doorbell for 8 SDMA RLC queues later, we could use new doorbell index for paging queue.
Change-Id I9adb965f16ee4089d261d9a22231337739184e49Signed-off-by Philip Yang <[email protected]>--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +++++++++++++--------- 2 files changed, 33 insertions(+), 13 deletions(-)drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +3
-0@@ -534,6 +534,19 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)if (adev->doorbell.num_doorbells ==0 )return -EINVAL ; +/* For Vega, reserve and map two pages on doorbell BAR since SDMA +* paging queue doorbell use the second page +*/
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) · line 549
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +10
-0+switch (adev->asic_type) { +case CHIP_VEGA10 : +case CHIP_VEGA12 : +case CHIP_VEGA20 : + adev->doorbell.num_doorbells *=2 ; +break ; +default : +break ; + } +
To future proof this, maybe we should just change this to:
if (asic_type >= VEGA10)
number_doorbells *= 2;
Quoted 8 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +0
-0adev->doorbell.ptr =ioremap (adev->doorbell.base, adev->doorbell.num_doorbells *sizeof (u32));drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +0
-0
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) · line 930
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +2
-4@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) OFFSET, ring->doorbell_index);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL, doorbell);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); -/* TODO: enable doorbell support */ -/*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, -ring->doorbell_index);*/ -sdma_v4_0_ring_set_wptr (ring); +/* paging queue doorbell index is already enabled at sdma_v4_0_gfx_resume */ +sdma_v4_0_page_ring_set_wptr (ring);
This looks like a bug fix that should be a separate patch.
Quoted 35 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +8
-9/* set minor_ptr_update to 0 after wptr programed */ WREG32_SDMA (i, mmSDMA0_PAGE_MINOR_PTR_UPDATE,0 );@@ -1504,18 +1502,14 @@ static int sdma_v4_0_sw_init(void *handle) ring->ring_obj =NULL ; ring->use_doorbell = true; -DRM_INFO ("use_doorbell being set to: [%s]\n" , - ring->use_doorbell?"true" :"false" ); -if (adev->asic_type ==CHIP_VEGA10 ) ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords else ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset - + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords sprintf (ring->name,"sdma%d" , i); r = amdgpu_ring_init(adev, ring, 1024,@@ -1529,7 +1523,20 @@ static int sdma_v4_0_sw_init(void *handle)if (adev->sdma.has_page_queue) { ring = &adev->sdma.instance[i].page; ring->ring_obj =NULL ; - ring->use_doorbell = false; + ring->use_doorbell = true; + +/* paging queue use same doorbell index/routing as gfx queue +* with 0x400 (4096 dwords) offset on second doorbell page
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static int sdma_v4_0_sw_init(void *handle) · line 1539
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +10
-0+*/ +if (adev->asic_type ==CHIP_VEGA10 ) + ring->doorbell_index = (i ==0 ) ? + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); +else + ring->doorbell_index = (i ==0 ) ? + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index +=0x400 ;
I don't quite understand how this works. Why don't we have to adjust the doorbell range registers in the nbio code?
Alex
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +0
-1sprintf (ring->name,"page%d" , i); r = amdgpu_ring_init(adev, ring, 1024, --2.17.1
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A message that is not in the archive (sent off-list or not yet received): CADnq5_M_FFga1hxj187yt0bf2DPLNj-OggUe-B=9TDYYRdMYVA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org
Quoted 23 lines · Alex Deucher
Quoted 22 lines · Philip
Because increase
SDMA_DOORBELL_RANGEto add new SDMA doorbell for paging queue will break SRIOV, instead we can reserve and map two doorbell pages for amdgpu, paging queues doorbell index use same index as SDMA gfx queues index but on second page.For Vega20, after we change doorbell layout to increase SDMA doorbell for 8 SDMA RLC queues later, we could use new doorbell index for paging queue.
Change-Id I9adb965f16ee4089d261d9a22231337739184e49Signed-off-by Philip Yang <[email protected]>--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +++++++++++++--------- 2 files changed, 33 insertions(+), 13 deletions(-)drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +0
-0@@ -534,6 +534,19 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)if (adev->doorbell.num_doorbells ==0 )return -EINVAL ;
Quoted 17 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) · line 549
Quoted 13 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +13
-0+/* For Vega, reserve and map two pages on doorbell BAR since SDMA +* paging queue doorbell use the second page +*/ +switch (adev->asic_type) { +case CHIP_VEGA10 : +case CHIP_VEGA12 : +case CHIP_VEGA20 : + adev->doorbell.num_doorbells *=2 ; +break ; +default : +break ; + } +To future proof this, maybe we should just change this to:
if (asic_type>= VEGA10)
number_doorbells*= 2;
OK
Quoted 15 lines
Quoted 15 lines
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +0
-0adev->doorbell.ptr =ioremap (adev->doorbell.base, adev->doorbell.num_doorbells *sizeof (u32));drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +0
-3@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) OFFSET, ring->doorbell_index);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL, doorbell);WREG32_SDMA (i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); -/* TODO: enable doorbell support */ -/*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, -ring->doorbell_index);*/
Quoted 4 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) · line 930
Quoted 3 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +2
-1-sdma_v4_0_ring_set_wptr (ring); +/* paging queue doorbell index is already enabled at sdma_v4_0_gfx_resume */ +sdma_v4_0_page_ring_set_wptr (ring);This looks like a bug fix that should be a separate patch.
OK
Quoted 47 lines
Quoted 34 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +8
-9/* set minor_ptr_update to 0 after wptr programed */ WREG32_SDMA (i, mmSDMA0_PAGE_MINOR_PTR_UPDATE,0 );@@ -1504,18 +1502,14 @@ static int sdma_v4_0_sw_init(void *handle) ring->ring_obj =NULL ; ring->use_doorbell = true; -DRM_INFO ("use_doorbell being set to: [%s]\n" , - ring->use_doorbell?"true" :"false" ); -if (adev->asic_type ==CHIP_VEGA10 ) ring->doorbell_index = (i ==0 ) ? - (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords else ring->doorbell_index = (i ==0 ) ? - (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )//get DWORD offset - : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// get DWORD offset - + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 )// doorbell size 2 dwords + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 );// doorbell size 2 dwords sprintf (ring->name,"sdma%d" , i); r = amdgpu_ring_init(adev, ring, 1024,@@ -1529,7 +1523,20 @@ static int sdma_v4_0_sw_init(void *handle)if (adev->sdma.has_page_queue) { ring = &adev->sdma.instance[i].page; ring->ring_obj =NULL ; - ring->use_doorbell = false; + ring->use_doorbell = true; + +/* paging queue use same doorbell index/routing as gfx queue +* with 0x400 (4096 dwords) offset on second doorbell page drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static int sdma_v4_0_sw_init(void *handle) · line 1539
Quoted 10 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +10
-0+*/ +if (adev->asic_type ==CHIP_VEGA10 ) + ring->doorbell_index = (i ==0 ) ? + (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 <<1 ); +else + ring->doorbell_index = (i ==0 ) ? + (AMDGPU_DOORBELL64_sDMA_ENGINE0 <<1 ) + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 <<1 ); + ring->doorbell_index +=0x400 ;I don't quite understand how this works. Why don't we have to adjust the doorbell range registers in the nbio code?
Quoted 1 line
Alex
nbio doorbell routing use low bits (11bits or 12bits?), so doorbell index 0x1E0 and 0x5E0 (dwords
address 0x780 and 0x1780) will both route to same SDMA engine0.
Philip
Quoted 9 lines
Quoted 9 lines
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +0
-1sprintf (ring->name,"page%d" , i); r = amdgpu_ring_init(adev, ring, 1024, --2.17.1
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Quoted 3 lines · Alex Deucher
Quoted 1 line
+
ring->doorbell_index+=0x400;I don't quite understand how this works. Why don't we have to adjust the doorbell range registers in the nbio code?
NBIO only looks at the lower 12 bits of the doorbell address. So adding 0x400 dwords or 0x1000 bytes has no effect on the doorbell routing.
That's also how we can use SDMA doorbells in our per-process doorbell pages at higher addresses.
Regards,
Felix
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