Enable all asynchronous abort exceptions taken to EL3
cover Enable all asynchronous abort exceptions taken to EL3
From: "Ang, Chee Hong" <[email protected]>
This patchset allow PSCI exception vectors to handle all external abort and SError exception from all exception levels. This will allow EL3 to handle asynchronous abort exceptions such as ECC DBE (Double Bit Error) taken from OS running at lower exception level.
Chee Hong Ang (3):
ARMv8: Enable all asynchronous abort exceptions taken to EL3
ARMv8: Add EL3 exception handling for ARMv8's Kconfig
ARMv8: SError exception handling in PSCI exception vectors
arch/arm/cpu/armv8/Kconfig | 7 +++++++ arch/arm/cpu/armv8/psci.S | 26 ++++++++++++++++++++++++++ arch/arm/include/asm/macro.h | 4 ++++ arch/arm/include/asm/system.h | 1 + 4 files changed, 38 insertions(+)
Signature · 1 line
2.7.4
PATCH 1/3 ARMv8: Enable all asynchronous abort exceptions taken to EL3
From: Chee Hong Ang <[email protected]>
Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels.
--- arch/arm/include/asm/macro.h | 4 ++++ arch/arm/include/asm/system.h | 1 + 2 files changed, 5 insertions(+)
arch/arm/include/asm/macro.h +4 -0
@@ -193,6 +193,10 @@ lr .req x30 SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ SCR_EL3_NS_EN)#endif + +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + orr \tmp, \tmp, #SCR_EL3_EA_EN +#endif msr scr_el3, \tmp/* Return to the EL2_SP2 mode from EL3 */
arch/arm/include/asm/system.h +1 -0
@@ -29,6 +29,7 @@#define SCR_EL3_HCE_EN (1 << 8)/* Hypervisor Call enable */ #define SCR_EL3_SMD_DIS (1 << 7)/* Secure Monitor Call disable */ #define SCR_EL3_RES1 (3 << 4)/* Reserved, RES1 */ +#define SCR_EL3_EA_EN (1 << 3)/* External aborts taken to EL3 */ #define SCR_EL3_NS_EN (1 << 0)/* EL0 and EL1 in Non-scure state */ /*
Signature · 1 line
2.7.4
PATCH 1/3 ARMv8: Enable all asynchronous abort exceptions taken to EL3
Quoted 6 lines · chee.hong.ang at intel.com
From: Chee Hong Ang <[email protected]>
Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels.
Signed-off-by Chee Hong Ang <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH 2/3 ARMv8: Add EL3 exception handling for ARMv8's Kconfig
In reply to chee.hong.ang at intel.comFrom: Chee Hong Ang <[email protected]>
Kconfig option to allow all External Abort and SError exception taken to EL3.
--- arch/arm/cpu/armv8/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/cpu/armv8/Kconfig +7 -0
@@ -144,6 +144,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. +config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" + default n + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. + if SYS_HAS_ARMV8_SECURE_BASE config ARMV8_SECURE_BASE
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2.7.4
PATCH 2/3 ARMv8: Add EL3 exception handling for ARMv8's Kconfig
Quoted 6 lines · chee.hong.ang at intel.com
From: Chee Hong Ang <[email protected]>
Kconfigoption to allow all External Abort and SError exception taken to EL3.Signed-off-by Chee Hong Ang <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH 3/3 ARMv8: SError exception handling in PSCI exception vectors
In reply to chee.hong.ang at intel.comFrom: Chee Hong Ang <[email protected]>
Allow platform vendors to handle SError interrupt exceptions from ARMv8 PSCI exception vectors by overriding this weak function 'plat_error_handler'.
--- arch/arm/cpu/armv8/psci.S | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
arch/arm/cpu/armv8/psci.S +26 -0
@@ -236,6 +236,28 @@ handle_sync: b unhandled_exception +#ifdef CONFIG_ARMV8_EA_EL3_FIRST +/* + * Override this function if custom error handling is + * needed for asynchronous aborts + */ +ENTRY(plat_error_handler) + ret +ENDPROC(plat_error_handler) +.weak plat_error_handler + +handle_error: + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov x9, #1 + msr spsel, x9 + mov sp, x0 + + bl plat_error_handler /* Platform specific error handling */ +deadloop: + b deadloop /* Never return */ +#endif + .align 11 .globl el3_exception_vectors el3_exception_vectors:
@@ -261,7 +283,11 @@ el3_exception_vectors: .align 7 b unhandled_exception /* FIQ, Lower EL using AArch64 */ .align 7 +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + b handle_error /* SError, Lower EL using AArch64 */ +#else b unhandled_exception /* SError, Lower EL using AArch64 */ +#endif .align 7 b unhandled_exception /* Sync, Lower EL using AArch32 */ .align 7
Signature · 1 line
2.7.4
PATCH 3/3 ARMv8: SError exception handling in PSCI exception vectors
Quoted 7 lines · chee.hong.ang at intel.com
From: Chee Hong Ang <[email protected]>
Allow platform vendors to handle SError interrupt exceptions from ARMv8 PSCI exception vectors by overriding this weak function '
plat_error_handler'.Signed-off-by Chee Hong Ang <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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