ARM: dts: rockchip: Remove @0 from the veyron memory node

The Coreboot version on veyron ChromeOS devices seems to ignore memory at 0 nodes when updating the available memory and instead inserts another memory node without the address.

This leads to 4GB systems only ever be using 2GB as the memory at 0 node takes precedence. So remove the @0 for veyron devices.

---
 arch/arm/boot/dts/rk3288-veyron.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

index 2075120cfc4d..d8bf939a3aff 100644
@@ -10,7 +10,11 @@
 #include "rk3288.dtsi"
 
 / {
-	memory at 0 {
+	/*
+	 * The default coreboot on veyron devices ignores memory at 0 nodes
+	 * and would instead create another memory node.
+	 */
+	memory {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};

2.18.0