lib/batchbuffer: Set bpp in igt_buf.
PATCH 1/3 lib/batchbuffer: Set bpp in igt_buf.
We want to allow bpp = 8 or 16, so make sure we set the bpp in igt_buf. This way we can extend rendercopy to support other values for bpp.
Signed-off-by Maarten Lankhorst <[email protected]>
--- lib/igt_draw.c | 2 ++ lib/intel_batchbuffer.c | 7 ++++--- lib/intel_batchbuffer.h | 2 ++ tests/i915/gem_concurrent_all.c | 2 ++ tests/i915/gem_gpgpu_fill.c | 1 + tests/i915/gem_media_fill.c | 1 + tests/i915/gem_ppgtt.c | 2 ++ tests/i915/gem_read_read_speed.c | 2 ++ tests/i915/gem_render_copy.c | 2 ++ tests/i915/gem_render_copy_redux.c | 1 + tests/i915/gem_render_linear_blits.c | 6 ++++++ tests/i915/gem_render_tiled_blits.c | 2 ++ tests/i915/gem_ring_sync_copy.c | 1 + tests/i915/gem_stress.c | 1 + tests/kms_psr.c | 1 + tests/perf.c | 1 + tests/pm_sseu.c | 1 + 17 files changed, 32 insertions(+), 3 deletions(-)
lib/igt_draw.c +2 -0
@@ -602,10 +602,12 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, src_buf.stride = tmp.stride; src_buf.tiling =I915_TILING_NONE ; src_buf.size = tmp.size; + src_buf.bpp =32 ; dst_buf.bo = dst; dst_buf.stride = buf->stride; dst_buf.tiling = tiling; dst_buf.size = buf->size; + dst_buf.bpp =32 ; batch =intel_batchbuffer_alloc (cmd_data->bufmgr, devid);igt_assert (batch);
lib/intel_batchbuffer.c +4 -3
@@ -511,7 +511,7 @@ intel_copy_bo(struct intel_batchbuffer *batch,*/ unsigned igt_buf_width (const struct igt_buf *buf) { -return buf->stride/sizeof (uint32_t ); +return buf->stride/(buf->bpp /8 ); }/**
@@ -764,7 +764,6 @@ void igt_blitter_fast_copy__raw(int fd,* @src_y: source pixel y-coordination * @width: width of the copied rectangle * @height: height of the copied rectangle -* @bpp: source and destination bits per pixel * @dst: destination i-g-t buffer object * @dst_delta: offset into the destination i-g-t bo * @dst_x: destination pixel x-coordination
@@ -785,10 +784,12 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,uint32_t src_pitch, dst_pitch;uint32_t dword0, dword1; +igt_assert (src->bpp == dst->bpp); + src_pitch =fast_copy_pitch (src->stride, src->tiling); dst_pitch =fast_copy_pitch (dst->stride, src->tiling); dword0 =fast_copy_dword0 (src->tiling, dst->tiling); - dword1 =fast_copy_dword1 (src->tiling, dst->tiling, bpp); + dword1 =fast_copy_dword1 (src->tiling, dst->tiling, dst->bpp);#define CHECK_RANGE (x) ((x) >= 0 && (x) < (1 << 15)) assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&
lib/intel_batchbuffer.h +2 -0
@@ -215,6 +215,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,* @bo: underlying libdrm buffer object * @stride: stride of the buffer * @tiling: tiling mode bits +* @bpp: bits per pixel, 8, 16 or 32. * @data: pointer to the memory mapping of the buffer * @size: size of the buffer object *
@@ -226,6 +227,7 @@ struct igt_buf {drm_intel_bo *bo;uint32_t stride;uint32_t tiling; +uint32_t bpp;uint32_t *data;uint32_t size;struct {
tests/i915/gem_concurrent_all.c +2 -0
@@ -854,11 +854,13 @@ static void render_copy_bo(struct buffers *b, drm_intel_bo *dst, drm_intel_bo *s .size = b->npixels * 4, .num_tiles = b->npixels * 4, .stride = b->width * 4, + .bpp =32 , }, s = { .bo = src, .size = b->npixels * 4, .num_tiles = b->npixels * 4, .stride = b->width * 4, + .bpp = 32, };uint32_t swizzle;
tests/i915/gem_gpgpu_fill.c +1 -0
@@ -78,6 +78,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; } static void
tests/i915/gem_media_fill.c +1 -0
@@ -81,6 +81,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; } static void
tests/i915/gem_ppgtt.c +2 -0
@@ -76,6 +76,7 @@ static void scratch_buf_init(struct igt_buf *buf, buf->stride =STRIDE ; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; }static void scratch_buf_fini (struct igt_buf *buf)
@@ -132,6 +133,7 @@ static void fork_rcs_copy(int target, drm_intel_bo **dst, int count, unsigned fl buf.stride =STRIDE ; buf.tiling =I915_TILING_NONE ; buf.size =SIZE ; + buf.bpp =32 ;for (int i =0 ; i <= target; i++) {struct igt_buf src;
tests/i915/gem_read_read_speed.c +2 -0
@@ -56,11 +56,13 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo *dst, drm_intel_bo *src) .size = width * height * 4, .num_tiles = width * height * 4, .stride = width * 4, + .bpp =32 , }, s = { .bo = src, .size = width * height * 4, .num_tiles = width * height * 4, .stride = width * 4, + .bpp = 32, };uint32_t swizzle;drm_intel_bo *bo = batch->bo;
tests/i915/gem_render_copy.c +2 -0
@@ -287,6 +287,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride =ALIGN (width *4 ,128 ); buf->size = buf->stride * height; buf->tiling = tiling; + buf->bpp =32 ; aux_width =scratch_buf_aux_width (buf); aux_height =scratch_buf_aux_height (buf);
@@ -309,6 +310,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = pitch; buf->tiling = tiling; buf->size = pitch * height; + buf->bpp =32 ;; }igt_assert (igt_buf_width (buf) == width);
tests/i915/gem_render_copy_redux.c +1 -0
@@ -109,6 +109,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; }static void scratch_buf_fini (data_t *data,struct igt_buf *buf)
tests/i915/gem_render_linear_blits.c +6 -0
@@ -111,11 +111,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[(i +1 ) % count]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[(i +1 ) % count] = start_val[i % count];
@@ -134,11 +136,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[i % count]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[i % count] = start_val[(i +1 ) % count];
@@ -159,11 +163,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[d]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[d] = start_val[s];
tests/i915/gem_render_tiled_blits.c +2 -0
@@ -69,6 +69,7 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val) tmp.stride =STRIDE ; tmp.tiling =I915_TILING_NONE ; tmp.size =SIZE ; + tmp.bpp =32 ;render_copy (batch,NULL , buf,0 ,0 ,WIDTH ,HEIGHT , &tmp,0 ,0 );if (snoop) {
@@ -134,6 +135,7 @@ static void run_test (int fd, int count) buf[i].stride = pitch; buf[i].tiling = tiling; buf[i].size =SIZE ; + buf[i].bpp =32 ; start_val[i] = start;
tests/i915/gem_ring_sync_copy.c +1 -0
@@ -137,6 +137,7 @@ static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo) buf->stride =4 *WIDTH ; buf->tiling =I915_TILING_NONE ; buf->size =4 *WIDTH *HEIGHT ; + buf->bpp =32 ; } static void scratch_buf_init(data_t *data, struct igt_buf *buf,
tests/i915/gem_stress.c +1 -0
@@ -485,6 +485,7 @@ static void init_buffer(struct igt_buf *buf, unsigned size)igt_assert (buf->bo); buf->tiling =I915_TILING_NONE ; buf->stride =4096 ; + buf->bpp =32 ;sanitize_stride (buf);
tests/kms_psr.c +1 -0
@@ -153,6 +153,7 @@ static void scratch_buf_init(struct igt_buf *buf, drm_intel_bo *bo, buf->stride = stride; buf->tiling =I915_TILING_X ; buf->size = size; + buf->bpp =32 ; }static void fill_render (data_t *data,uint32_t handle,unsigned char color)
tests/perf.c +1 -0
@@ -501,6 +501,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size = size; + buf->bpp =32 ; } static void
tests/pm_sseu.c +1 -0
@@ -303,6 +303,7 @@ gem_init(void) gem.buf.tiling =I915_TILING_NONE ; gem.buf.size = gem.buf.stride; gem.buf.bo =drm_intel_bo_alloc (gem.bufmgr,"" , gem.buf.size,4096 ); + gem.buf.bpp =32 ;igt_assert (gem.buf.bo); gem.init =4 ;
Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
PATCH 2/3 lib/rendercopy: Implement support for 8/16 bpp
To handle drawing 16 bpp formats correctly with odd x/w, we need to use the correct bpp to rendercopy. Now that everything sets bpp in igt_buf, fix the rendercopy support to use it and set the correct format.
Signed-off-by Maarten Lankhorst <[email protected]>
--- lib/rendercopy_gen4.c | 15 +++++++++------ lib/rendercopy_gen6.c | 16 ++++++++++------ lib/rendercopy_gen7.c | 16 ++++++++++------ lib/rendercopy_gen8.c | 18 +++++++++--------- lib/rendercopy_gen9.c | 15 +++++++++------ lib/rendercopy_i830.c | 20 ++++++++++++++++++-- lib/rendercopy_i915.c | 23 +++++++++++++++++++---- 7 files changed, 84 insertions(+), 39 deletions(-)
lib/rendercopy_gen4.c +9 -6
@@ -136,7 +136,7 @@ gen4_render_flush(struct intel_batchbuffer *batch,static uint32_t gen4_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) +int is_dst) {struct gen4_surface_state *ss;uint32_t write_domain, read_domain;
@@ -152,7 +152,12 @@ gen4_bind_buf(struct intel_batchbuffer *batch, ss =intel_batchbuffer_subdata_alloc (batch,sizeof (*ss),32 ); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.data_return_format =SURFACERETURNFORMAT_FLOAT32 ; ss->ss0.color_blend =1 ;
@@ -182,10 +187,8 @@ gen4_bind_surfaces(struct intel_batchbuffer *batch, binding_table =intel_batchbuffer_subdata_alloc (batch,32 ,32 ); - binding_table[0 ] = -gen4_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen4_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen4_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen4_bind_buf (batch, src,0 );return intel_batchbuffer_subdata_offset (batch, binding_table); }
lib/rendercopy_gen6.c +10 -6
@@ -73,7 +73,7 @@ gen6_render_flush(struct intel_batchbuffer *batch,static uint32_t gen6_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) +int is_dst) {struct gen6_surface_state *ss;uint32_t write_domain, read_domain;
@@ -88,7 +88,13 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss =intel_batchbuffer_subdata_alloc (batch,sizeof (*ss),32 ); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; + +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.data_return_format =SURFACERETURNFORMAT_FLOAT32 ; ss->ss0.color_blend =1 ;
@@ -118,10 +124,8 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch, binding_table =intel_batchbuffer_subdata_alloc (batch,32 ,32 ); - binding_table[0 ] = -gen6_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen6_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen6_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen6_bind_buf (batch, src,0 );return intel_batchbuffer_subdata_offset (batch, binding_table); }
lib/rendercopy_gen7.c +10 -6
@@ -59,13 +59,19 @@ gen7_tiling_bits(uint32_t tiling)static uint32_t gen7_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) { -uint32_t *ss; +uint32_t format, *ss;uint32_t write_domain, read_domain;int ret; +switch (buf->bpp) { +case 8 : format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } +if (is_dst) { write_domain = read_domain =I915_GEM_DOMAIN_RENDER ; }else {
@@ -186,10 +192,8 @@ gen7_bind_surfaces(struct intel_batchbuffer *batch, binding_table =intel_batchbuffer_subdata_alloc (batch,8 ,32 ); - binding_table[0 ] = -gen7_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen7_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen7_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen7_bind_buf (batch, src,0 );return intel_batchbuffer_subdata_offset (batch, binding_table); }
lib/rendercopy_gen8.c +9 -9
@@ -144,8 +144,7 @@ gen6_render_flush(struct intel_batchbuffer *batch,static uint32_t gen8_bind_buf (struct intel_batchbuffer *batch,struct annotations_context *aub, -const struct igt_buf *buf, -uint32_t format,int is_dst) +const struct igt_buf *buf,int is_dst) {struct gen8_surface_state *ss;uint32_t write_domain, read_domain, offset;
@@ -163,7 +162,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch,annotation_add_state (aub,AUB_TRACE_SURFACE_STATE , offset,sizeof (*ss)); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.render_cache_read_write =1 ; ss->ss0.vertical_alignment =1 ;/* align 4 */ ss->ss0.horizontal_alignment =1 ;/* align 4 */
@@ -205,12 +209,8 @@ gen8_bind_surfaces(struct intel_batchbuffer *batch, offset =intel_batchbuffer_subdata_offset (batch, binding_table);annotation_add_state (aub,AUB_TRACE_BINDING_TABLE , offset,8 ); - binding_table[0 ] = -gen8_bind_buf (batch, aub, - dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen8_bind_buf (batch, aub, - src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen8_bind_buf (batch, aub, dst,1 ); + binding_table[1 ] =gen8_bind_buf (batch, aub, src,0 );return offset; }
lib/rendercopy_gen9.c +9 -6
@@ -175,7 +175,7 @@ gen6_render_flush(struct intel_batchbuffer *batch,/* Mostly copy+paste from gen6, except height, width, pitch moved */ static uint32_t gen8_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) { +int is_dst) {struct gen8_surface_state *ss;uint32_t write_domain, read_domain, offset;int ret;
@@ -193,7 +193,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, offset, sizeof(*ss)); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.render_cache_read_write =1 ; ss->ss0.vertical_alignment =1 ;/* align 4 */ ss->ss0.horizontal_alignment =1 ;/* align 4 */
@@ -249,10 +254,8 @@ gen8_bind_surfaces(struct intel_batchbuffer *batch,annotation_add_state (&aub_annotations,AUB_TRACE_BINDING_TABLE , offset,8 ); - binding_table[0 ] = -gen8_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen8_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen8_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen8_bind_buf (batch, src,0 );return offset; }
lib/rendercopy_i830.c +18 -2
@@ -136,6 +136,14 @@ static void gen2_emit_target(struct intel_batchbuffer *batch, const struct igt_buf *dst) {uint32_t tiling; +uint32_t format; + +switch (dst->bpp) { +case 8 : format =COLR_BUF_8BIT ;break ; +case 16 : format =COLR_BUF_RGB565 ;break ; +case 32 : format =COLR_BUF_ARGB8888 ;break ; +default :igt_assert (0 ); + } tiling =0 ;if (dst->tiling !=I915_TILING_NONE )
@@ -148,7 +156,7 @@ static void gen2_emit_target(struct intel_batchbuffer *batch,OUT_RELOC (dst->bo,I915_GEM_DOMAIN_RENDER ,I915_GEM_DOMAIN_RENDER ,0 );OUT_BATCH (_3DSTATE_DST_BUF_VARS_CMD); -OUT_BATCH (COLR_BUF_ARGB8888 | +OUT_BATCH (format |DSTORG_HORT_BIAS (0x8 ) |DSTORG_VERT_BIAS (0x8 ));
@@ -165,6 +173,14 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch, int unit) {uint32_t tiling; +uint32_t format; + +switch (src->bpp) { +case 8 : format =MAPSURF_8BIT |MT_8BIT_L8 ;break ; +case 16 : format =MAPSURF_16BIT |MT_16BIT_RGB565 ;break ; +case 32 : format =MAPSURF_32BIT |MT_32BIT_ARGB8888 ;break ; +default :igt_assert (0 ); + } tiling =0 ;if (src->tiling !=I915_TILING_NONE )
@@ -176,7 +192,7 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch,OUT_RELOC (src->bo,I915_GEM_DOMAIN_SAMPLER ,0 ,0 );OUT_BATCH ((igt_buf_height (src) -1 ) <<TM0S1_HEIGHT_SHIFT | (igt_buf_width (src) -1 ) <<TM0S1_WIDTH_SHIFT | -MAPSURF_32BIT |MT_32BIT_ARGB8888 | tiling); + format | tiling);OUT_BATCH ((src->stride /4 -1 ) <<TM0S2_PITCH_SHIFT |TM0S2_MAP_2D ); OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
lib/rendercopy_i915.c +19 -4
@@ -84,17 +84,23 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,/* samler state */ {#define TEX_COUNT 1 -uint32_t tiling_bits =0 ; +uint32_t format_bits, tiling_bits =0 ;if (src->tiling !=I915_TILING_NONE ) tiling_bits =MS3_TILED_SURFACE ;if (src->tiling ==I915_TILING_Y ) tiling_bits |=MS3_TILE_WALK ; +switch (src->bpp) { +case 8 : format_bits =MAPSURF_8BIT |MT_8BIT_L8 ;break ; +case 16 : format_bits =MAPSURF_16BIT |MT_16BIT_RGB565 ;break ; +case 32 : format_bits =MAPSURF_32BIT |MT_32BIT_ARGB8888 ;break ; +default :igt_assert (0 ); + } +OUT_BATCH (_3DSTATE_MAP_STATE | (3 *TEX_COUNT ));OUT_BATCH ((1 <<TEX_COUNT ) -1 );OUT_RELOC (src->bo,I915_GEM_DOMAIN_SAMPLER ,0 ,0 ); -OUT_BATCH (MAPSURF_32BIT |MT_32BIT_ARGB8888 | - tiling_bits | +OUT_BATCH (format_bits | tiling_bits | (igt_buf_height (src) -1 ) <<MS3_HEIGHT_SHIFT | (igt_buf_width (src) -1 ) <<MS3_WIDTH_SHIFT );OUT_BATCH ((src->stride/4 -1 ) <<MS4_PITCH_SHIFT );
@@ -113,6 +119,15 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,/* render target state */ {uint32_t tiling_bits =0 ; +uint32_t format_bits; + +switch (dst->bpp) { +case 8 : format_bits =COLR_BUF_8BIT ;break ; +case 16 : format_bits =COLR_BUF_RGB565 ;break ; +case 32 : format_bits =COLR_BUF_ARGB8888 ;break ; +default :igt_assert (0 ); + } +if (dst->tiling !=I915_TILING_NONE ) tiling_bits =BUF_3D_TILED_SURFACE ;if (dst->tiling ==I915_TILING_Y )
@@ -124,7 +139,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,OUT_RELOC (dst->bo,I915_GEM_DOMAIN_RENDER ,I915_GEM_DOMAIN_RENDER ,0 );OUT_BATCH (_3DSTATE_DST_BUF_VARS_CMD); -OUT_BATCH (COLR_BUF_ARGB8888 | +OUT_BATCH (format_bits |DSTORG_HORT_BIAS (0x8 ) |DSTORG_VERT_BIAS (0x8 ));
Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Re: [igt-dev] [PATCH i-g-t 2/3] lib/rendercopy: Implement support for 8/16 bpp
Quoted 30 lines · Maarten Lankhorst
To handle drawing 16 bpp formats correctly with odd x/w, we need to use the correct bpp to rendercopy. Now that everything sets bpp in
igt_buf, fix the rendercopy support to use it and set the correct format.Signed-off-by Maarten Lankhorst <[email protected]>--- lib/rendercopy_gen4.c | 15 +++++++++------ lib/rendercopy_gen6.c | 16 ++++++++++------ lib/rendercopy_gen7.c | 16 ++++++++++------ lib/rendercopy_gen8.c | 18 +++++++++--------- lib/rendercopy_gen9.c | 15 +++++++++------ lib/rendercopy_i830.c | 20 ++++++++++++++++++-- lib/rendercopy_i915.c | 23 +++++++++++++++++++---- 7 files changed, 84 insertions(+), 39 deletions(-)lib/rendercopy_gen4.c +1
-1@@ -136,7 +136,7 @@ gen4_render_flush(struct intel_batchbuffer *batch,static uint32_t gen4_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) +int is_dst) {struct gen4_surface_state *ss;uint32_t write_domain, read_domain;
lib/rendercopy_gen4.c gen4_bind_buf(struct intel_batchbuffer *batch, · line 159
Quoted 9 lines
lib/rendercopy_gen4.c +5
-1@@ -152,7 +152,12 @@ gen4_bind_buf(struct intel_batchbuffer *batch, ss =intel_batchbuffer_subdata_alloc (batch,sizeof (*ss),32 ); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 );
Hmm. Maybe we actually want to specify a format rather than bpp? That way we could convert between different sized pixel formats, and interpolation would also be possible so we could even scale the image. But as not all formats could be supported so I guess a 1:1 copy is a pretty good starting point at least. It's what we do with 32bpp currently anyway.
Looks like all of these formats are supported by the sampler and render target on all gens. So that makes this nice and simple.
Quoted 185 lines
lib/rendercopy_gen4.c +3
-4+ } ss->ss0.data_return_format =SURFACERETURNFORMAT_FLOAT32 ; ss->ss0.color_blend =1 ;@@ -182,10 +187,8 @@ gen4_bind_surfaces(struct intel_batchbuffer *batch, binding_table =intel_batchbuffer_subdata_alloc (batch,32 ,32 ); - binding_table[0 ] = -gen4_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen4_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen4_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen4_bind_buf (batch, src,0 );return intel_batchbuffer_subdata_offset (batch, binding_table); }lib/rendercopy_gen6.c +10
-6@@ -73,7 +73,7 @@ gen6_render_flush(struct intel_batchbuffer *batch,static uint32_t gen6_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) +int is_dst) {struct gen6_surface_state *ss;uint32_t write_domain, read_domain;@@ -88,7 +88,13 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss =intel_batchbuffer_subdata_alloc (batch,sizeof (*ss),32 ); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; + +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.data_return_format =SURFACERETURNFORMAT_FLOAT32 ; ss->ss0.color_blend =1 ;@@ -118,10 +124,8 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch, binding_table =intel_batchbuffer_subdata_alloc (batch,32 ,32 ); - binding_table[0 ] = -gen6_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen6_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen6_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen6_bind_buf (batch, src,0 );return intel_batchbuffer_subdata_offset (batch, binding_table); }lib/rendercopy_gen7.c +10
-6@@ -59,13 +59,19 @@ gen7_tiling_bits(uint32_t tiling)static uint32_t gen7_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) { -uint32_t *ss; +uint32_t format, *ss;uint32_t write_domain, read_domain;int ret; +switch (buf->bpp) { +case 8 : format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } +if (is_dst) { write_domain = read_domain =I915_GEM_DOMAIN_RENDER ; }else {@@ -186,10 +192,8 @@ gen7_bind_surfaces(struct intel_batchbuffer *batch, binding_table =intel_batchbuffer_subdata_alloc (batch,8 ,32 ); - binding_table[0 ] = -gen7_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen7_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen7_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen7_bind_buf (batch, src,0 );return intel_batchbuffer_subdata_offset (batch, binding_table); }lib/rendercopy_gen8.c +9
-9@@ -144,8 +144,7 @@ gen6_render_flush(struct intel_batchbuffer *batch,static uint32_t gen8_bind_buf (struct intel_batchbuffer *batch,struct annotations_context *aub, -const struct igt_buf *buf, -uint32_t format,int is_dst) +const struct igt_buf *buf,int is_dst) {struct gen8_surface_state *ss;uint32_t write_domain, read_domain, offset;@@ -163,7 +162,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch,annotation_add_state (aub,AUB_TRACE_SURFACE_STATE , offset,sizeof (*ss)); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.render_cache_read_write =1 ; ss->ss0.vertical_alignment =1 ;/* align 4 */ ss->ss0.horizontal_alignment =1 ;/* align 4 */ @@ -205,12 +209,8 @@ gen8_bind_surfaces(struct intel_batchbuffer *batch, offset =intel_batchbuffer_subdata_offset (batch, binding_table);annotation_add_state (aub,AUB_TRACE_BINDING_TABLE , offset,8 ); - binding_table[0 ] = -gen8_bind_buf (batch, aub, - dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen8_bind_buf (batch, aub, - src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen8_bind_buf (batch, aub, dst,1 ); + binding_table[1 ] =gen8_bind_buf (batch, aub, src,0 );return offset; }lib/rendercopy_gen9.c +9
-6@@ -175,7 +175,7 @@ gen6_render_flush(struct intel_batchbuffer *batch,/* Mostly copy+paste from gen6, except height, width, pitch moved */ static uint32_t gen8_bind_buf (struct intel_batchbuffer *batch,const struct igt_buf *buf, -uint32_t format,int is_dst) { +int is_dst) {struct gen8_surface_state *ss;uint32_t write_domain, read_domain, offset;int ret;@@ -193,7 +193,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, offset, sizeof(*ss)); ss->ss0.surface_type =SURFACE_2D ; - ss->ss0.surface_format = format; +switch (buf->bpp) { +case 8 : ss->ss0.surface_format =SURFACEFORMAT_R8_UNORM ;break ; +case 16 : ss->ss0.surface_format =SURFACEFORMAT_R8G8_UNORM ;break ; +case 32 : ss->ss0.surface_format =SURFACEFORMAT_B8G8R8A8_UNORM ;break ; +default :igt_assert (0 ); + } ss->ss0.render_cache_read_write =1 ; ss->ss0.vertical_alignment =1 ;/* align 4 */ ss->ss0.horizontal_alignment =1 ;/* align 4 */ @@ -249,10 +254,8 @@ gen8_bind_surfaces(struct intel_batchbuffer *batch,annotation_add_state (&aub_annotations,AUB_TRACE_BINDING_TABLE , offset,8 ); - binding_table[0 ] = -gen8_bind_buf (batch, dst,SURFACEFORMAT_B8G8R8A8_UNORM ,1 ); - binding_table[1 ] = -gen8_bind_buf (batch, src,SURFACEFORMAT_B8G8R8A8_UNORM ,0 ); + binding_table[0 ] =gen8_bind_buf (batch, dst,1 ); + binding_table[1 ] =gen8_bind_buf (batch, src,0 );return offset; }lib/rendercopy_i830.c +0
-0
lib/rendercopy_i830.c static void gen2_emit_target(struct intel_batchbuffer *batch, · line 142
Quoted 7 lines
lib/rendercopy_i830.c +4
-0@@ -136,6 +136,14 @@ static void gen2_emit_target(struct intel_batchbuffer *batch, const struct igt_buf *dst) {uint32_t tiling; +uint32_t format; + +switch (dst->bpp) { +case 8 : format =COLR_BUF_8BIT ;break ;
This one writes the green channel...
Quoted 17 lines
lib/rendercopy_i830.c +5
-1+case 16 : format =COLR_BUF_RGB565 ;break ; +case 32 : format =COLR_BUF_ARGB8888 ;break ; +default :igt_assert (0 ); + } tiling =0 ;if (dst->tiling !=I915_TILING_NONE )@@ -148,7 +156,7 @@ static void gen2_emit_target(struct intel_batchbuffer *batch,OUT_RELOC (dst->bo,I915_GEM_DOMAIN_RENDER ,I915_GEM_DOMAIN_RENDER ,0 );OUT_BATCH (_3DSTATE_DST_BUF_VARS_CMD); -OUT_BATCH (COLR_BUF_ARGB8888 | +OUT_BATCH (format |DSTORG_HORT_BIAS (0x8 ) |DSTORG_VERT_BIAS (0x8 ));
lib/rendercopy_i830.c static void gen2_emit_texture(struct intel_batchbuffer *batch, · line 179
Quoted 7 lines
lib/rendercopy_i830.c +4
-0@@ -165,6 +173,14 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch, int unit) {uint32_t tiling; +uint32_t format; + +switch (src->bpp) { +case 8 : format =MAPSURF_8BIT |MT_8BIT_L8 ;break ;
.. and L8 replicates the same 8 bit value to RGB, so looks like this should work just fine. Same for gen3.
Reviewed-by Ville Syrjälä <[email protected]>
Quoted 79 lines
lib/rendercopy_i830.c +5
-1+case 16 : format =MAPSURF_16BIT |MT_16BIT_RGB565 ;break ; +case 32 : format =MAPSURF_32BIT |MT_32BIT_ARGB8888 ;break ; +default :igt_assert (0 ); + } tiling =0 ;if (src->tiling !=I915_TILING_NONE )@@ -176,7 +192,7 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch,OUT_RELOC (src->bo,I915_GEM_DOMAIN_SAMPLER ,0 ,0 );OUT_BATCH ((igt_buf_height (src) -1 ) <<TM0S1_HEIGHT_SHIFT | (igt_buf_width (src) -1 ) <<TM0S1_WIDTH_SHIFT | -MAPSURF_32BIT |MT_32BIT_ARGB8888 | tiling); + format | tiling);OUT_BATCH ((src->stride /4 -1 ) <<TM0S2_PITCH_SHIFT |TM0S2_MAP_2D ); OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT | FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |lib/rendercopy_i915.c +19
-4@@ -84,17 +84,23 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,/* samler state */ {#define TEX_COUNT 1 -uint32_t tiling_bits =0 ; +uint32_t format_bits, tiling_bits =0 ;if (src->tiling !=I915_TILING_NONE ) tiling_bits =MS3_TILED_SURFACE ;if (src->tiling ==I915_TILING_Y ) tiling_bits |=MS3_TILE_WALK ; +switch (src->bpp) { +case 8 : format_bits =MAPSURF_8BIT |MT_8BIT_L8 ;break ; +case 16 : format_bits =MAPSURF_16BIT |MT_16BIT_RGB565 ;break ; +case 32 : format_bits =MAPSURF_32BIT |MT_32BIT_ARGB8888 ;break ; +default :igt_assert (0 ); + } +OUT_BATCH (_3DSTATE_MAP_STATE | (3 *TEX_COUNT ));OUT_BATCH ((1 <<TEX_COUNT ) -1 );OUT_RELOC (src->bo,I915_GEM_DOMAIN_SAMPLER ,0 ,0 ); -OUT_BATCH (MAPSURF_32BIT |MT_32BIT_ARGB8888 | - tiling_bits | +OUT_BATCH (format_bits | tiling_bits | (igt_buf_height (src) -1 ) <<MS3_HEIGHT_SHIFT | (igt_buf_width (src) -1 ) <<MS3_WIDTH_SHIFT );OUT_BATCH ((src->stride/4 -1 ) <<MS4_PITCH_SHIFT );@@ -113,6 +119,15 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,/* render target state */ {uint32_t tiling_bits =0 ; +uint32_t format_bits; + +switch (dst->bpp) { +case 8 : format_bits =COLR_BUF_8BIT ;break ; +case 16 : format_bits =COLR_BUF_RGB565 ;break ; +case 32 : format_bits =COLR_BUF_ARGB8888 ;break ; +default :igt_assert (0 ); + } +if (dst->tiling !=I915_TILING_NONE ) tiling_bits =BUF_3D_TILED_SURFACE ;if (dst->tiling ==I915_TILING_Y )@@ -124,7 +139,7 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,OUT_RELOC (dst->bo,I915_GEM_DOMAIN_RENDER ,I915_GEM_DOMAIN_RENDER ,0 );OUT_BATCH (_3DSTATE_DST_BUF_VARS_CMD); -OUT_BATCH (COLR_BUF_ARGB8888 | +OUT_BATCH (format_bits |DSTORG_HORT_BIAS (0x8 ) |DSTORG_VERT_BIAS (0x8 ));Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Signature · 6 lines
Ville Syrjälä Intel _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
PATCH 3/3 lib/igt_draw: Pass bpp along to rendercopy.
In reply to Maarten LankhorstNow that rendercopy can perform copies for 8 bpp and 16 bpp, there's no reason we have to skip on odd x/w any more for 16 bpp.
Pass the correct bpp to rendercopy, and prevent tests from skipping.
Signed-off-by Maarten Lankhorst <[email protected]>
--- lib/igt_draw.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-)
lib/igt_draw.c +4 -21
@@ -573,16 +573,9 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,uint32_t tiling, swizzle;struct buf_data tmp;int pixel_size = buf->bpp /8 ; -unsigned adjusted_w, adjusted_dst_x;igt_skip_on (!rendercopy); -/* Rendercopy works at 32bpp, so if you try to do copies on buffers with -* smaller bpps you won't succeeed if you need to copy "half" of a 32bpp -* pixel or something similar. */ -igt_skip_on (rect->x % (32 / buf->bpp) !=0 || - rect->w % (32 / buf->bpp) !=0 ); -igt_require (gem_get_tiling (fd, buf->handle, &tiling, &swizzle));/* We create a temporary buffer and copy from it using rendercopy. */
@@ -602,28 +595,18 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, src_buf.stride = tmp.stride; src_buf.tiling =I915_TILING_NONE ; src_buf.size = tmp.size; - src_buf.bpp =32 ; + src_buf.bpp = buf->bpp; dst_buf.bo = dst; dst_buf.stride = buf->stride; dst_buf.tiling = tiling; dst_buf.size = buf->size; - dst_buf.bpp =32 ; + dst_buf.bpp = buf->bpp; batch =intel_batchbuffer_alloc (cmd_data->bufmgr, devid);igt_assert (batch); -switch (buf->bpp) { -case 16 : -case 32 : - adjusted_w = rect->w / (32 / buf->bpp); - adjusted_dst_x = rect->x / (32 / buf->bpp); -break ; -default : -igt_assert (false); - } - -rendercopy (batch, cmd_data->context, &src_buf,0 ,0 , adjusted_w, - rect->h, &dst_buf, adjusted_dst_x, rect->y); +rendercopy (batch, cmd_data->context, &src_buf,0 ,0 , rect->w, + rect->h, &dst_buf, rect->x, rect->y);intel_batchbuffer_free (batch);drm_intel_bo_unreference (src);
Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Re: [igt-dev] [PATCH i-g-t 3/3] lib/igt_draw: Pass bpp along to rendercopy.
Quoted 32 lines · Maarten Lankhorst
Now that rendercopy can perform copies for 8 bpp and 16 bpp, there's no reason we have to skip on odd x/w any more for 16 bpp.
Pass the correct bpp to rendercopy, and prevent tests from skipping.
Signed-off-by Maarten Lankhorst <[email protected]>--- lib/igt_draw.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-)lib/igt_draw.c +0
-7@@ -573,16 +573,9 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,uint32_t tiling, swizzle;struct buf_data tmp;int pixel_size = buf->bpp /8 ; -unsigned adjusted_w, adjusted_dst_x;igt_skip_on (!rendercopy); -/* Rendercopy works at 32bpp, so if you try to do copies on buffers with -* smaller bpps you won't succeeed if you need to copy "half" of a 32bpp -* pixel or something similar. */ -igt_skip_on (rect->x % (32 / buf->bpp) !=0 || - rect->w % (32 / buf->bpp) !=0 ); -igt_require (gem_get_tiling (fd, buf->handle, &tiling, &swizzle));/* We create a temporary buffer and copy from it using rendercopy. */
lib/igt_draw.c static void draw_rect_render(int fd, struct cmd_data *cmd_data, · line 598
Quoted 5 lines
lib/igt_draw.c +1
-1@@ -602,28 +595,18 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, src_buf.stride = tmp.stride; src_buf.tiling =I915_TILING_NONE ; src_buf.size = tmp.size; - src_buf.bpp =32 ; + src_buf.bpp = buf->bpp;
tmp.bpp ?
Reviewed-by Ville Syrjälä <[email protected]>
Quoted 34 lines
lib/igt_draw.c +3
-13dst_buf.bo = dst; dst_buf.stride = buf->stride; dst_buf.tiling = tiling; dst_buf.size = buf->size; - dst_buf.bpp =32 ; + dst_buf.bpp = buf->bpp; batch =intel_batchbuffer_alloc (cmd_data->bufmgr, devid);igt_assert (batch); -switch (buf->bpp) { -case 16 : -case 32 : - adjusted_w = rect->w / (32 / buf->bpp); - adjusted_dst_x = rect->x / (32 / buf->bpp); -break ; -default : -igt_assert (false); - } - -rendercopy (batch, cmd_data->context, &src_buf,0 ,0 , adjusted_w, - rect->h, &dst_buf, adjusted_dst_x, rect->y); +rendercopy (batch, cmd_data->context, &src_buf,0 ,0 , rect->w, + rect->h, &dst_buf, rect->x, rect->y);intel_batchbuffer_free (batch);drm_intel_bo_unreference (src);Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Signature · 6 lines
Ville Syrjälä Intel _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Patchwork
CI[igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,1/3] lib/batchbuffer: Set bpp in igt_buf.
In reply to Maarten Lankhorst== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/batchbuffer: Set bpp in igt_buf.
URL : https://patchwork.freedesktop.org/series/52620/
State : failure
== Summary ==
= CI Bug Log - changes from IGT_4718 -> IGTPW_2072 =
== Summary - FAILURE ==
Serious unknown changes coming with IGTPW_2072 absolutely need to be verified manually.
If you think the reported changes have nothing to do with the changes introduced in IGTPW_2072, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52620/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_2072:
=== IGT changes ===
==== Possible regressions ====
igt@gem_render_tiled_blits@basic:
fi-skl-iommu: PASS -> FAIL
fi-cfl-guc: PASS -> FAIL
fi-icl-u2: PASS -> FAIL
fi-whl-u: PASS -> FAIL
fi-cfl-8700k: PASS -> FAIL
fi-cfl-8109u: PASS -> FAIL
fi-glk-j4005: PASS -> FAIL
fi-skl-guc: PASS -> FAIL
fi-kbl-r: PASS -> FAIL
fi-icl-u: PASS -> FAIL
fi-skl-6260u: PASS -> FAIL
fi-skl-6770hq: PASS -> FAIL
fi-kbl-7560u: PASS -> FAIL
fi-skl-6600u: PASS -> FAIL
fi-apl-guc: PASS -> FAIL
fi-bxt-dsi: PASS -> FAIL
fi-cnl-u: PASS -> FAIL
fi-kbl-guc: PASS -> FAIL
fi-skl-6700hq: PASS -> FAIL
fi-bxt-j4205: PASS -> FAIL
fi-kbl-x1275: PASS -> FAIL
fi-skl-gvtdvm: PASS -> FAIL
fi-glk-dsi: PASS -> FAIL== Known issues ==
Here are the changes found in IGTPW_2072 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ctx_create@basic-files:
fi-icl-u2: PASS -> DMESG-WARN (fdo#107724)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
fi-snb-2520m: PASS -> DMESG-FAIL (fdo#103713)
igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-icl-u: PASS -> INCOMPLETE (fdo#107713)
==== Possible fixes ====
igt@i915_selftest@live_contexts:
fi-bsw-kefka: DMESG-FAIL (fdo#108656) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
== Participating hosts (49 -> 46) ==
Additional (1): fi-gdg-551
Missing (4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-hsw-4200u
== Build changes ==
* IGT: IGT_4718 -> IGTPW_2072
CI_DRM_5150: ab97324c7fb98fc8cadbe5ae4e50f36fb0137308 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2072: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2072/
IGT_4718: 8ac5cfb4db9c7bc593beec18a6be1e2ff163106c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2072/issues.html
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev
Quoted 190 lines · Maarten Lankhorst
We want to allow bpp = 8 or 16, so make sure we set the bpp in
igt_buf. This way we can extend rendercopy to support other values for bpp.Signed-off-by Maarten Lankhorst <[email protected]>--- lib/igt_draw.c | 2 ++ lib/intel_batchbuffer.c | 7 ++++--- lib/intel_batchbuffer.h | 2 ++ tests/i915/gem_concurrent_all.c | 2 ++ tests/i915/gem_gpgpu_fill.c | 1 + tests/i915/gem_media_fill.c | 1 + tests/i915/gem_ppgtt.c | 2 ++ tests/i915/gem_read_read_speed.c | 2 ++ tests/i915/gem_render_copy.c | 2 ++ tests/i915/gem_render_copy_redux.c | 1 + tests/i915/gem_render_linear_blits.c | 6 ++++++ tests/i915/gem_render_tiled_blits.c | 2 ++ tests/i915/gem_ring_sync_copy.c | 1 + tests/i915/gem_stress.c | 1 + tests/kms_psr.c | 1 + tests/perf.c | 1 + tests/pm_sseu.c | 1 + 17 files changed, 32 insertions(+), 3 deletions(-)lib/igt_draw.c +2
-0@@ -602,10 +602,12 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, src_buf.stride = tmp.stride; src_buf.tiling =I915_TILING_NONE ; src_buf.size = tmp.size; + src_buf.bpp =32 ; dst_buf.bo = dst; dst_buf.stride = buf->stride; dst_buf.tiling = tiling; dst_buf.size = buf->size; + dst_buf.bpp =32 ; batch =intel_batchbuffer_alloc (cmd_data->bufmgr, devid);igt_assert (batch);lib/intel_batchbuffer.c +4
-3@@ -511,7 +511,7 @@ intel_copy_bo(struct intel_batchbuffer *batch,*/ unsigned igt_buf_width (const struct igt_buf *buf) { -return buf->stride/sizeof (uint32_t ); +return buf->stride/(buf->bpp /8 ); }/** @@ -764,7 +764,6 @@ void igt_blitter_fast_copy__raw(int fd,* @src_y: source pixel y-coordination * @width: width of the copied rectangle * @height: height of the copied rectangle -* @bpp: source and destination bits per pixel * @dst: destination i-g-t buffer object * @dst_delta: offset into the destination i-g-t bo * @dst_x: destination pixel x-coordination @@ -785,10 +784,12 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,uint32_t src_pitch, dst_pitch;uint32_t dword0, dword1; +igt_assert (src->bpp == dst->bpp); + src_pitch =fast_copy_pitch (src->stride, src->tiling); dst_pitch =fast_copy_pitch (dst->stride, src->tiling); dword0 =fast_copy_dword0 (src->tiling, dst->tiling); - dword1 =fast_copy_dword1 (src->tiling, dst->tiling, bpp); + dword1 =fast_copy_dword1 (src->tiling, dst->tiling, dst->bpp);#define CHECK_RANGE (x) ((x) >= 0 && (x) < (1 << 15)) assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&lib/intel_batchbuffer.h +2
-0@@ -215,6 +215,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,* @bo: underlying libdrm buffer object * @stride: stride of the buffer * @tiling: tiling mode bits +* @bpp: bits per pixel, 8, 16 or 32. * @data: pointer to the memory mapping of the buffer * @size: size of the buffer object * @@ -226,6 +227,7 @@ struct igt_buf {drm_intel_bo *bo;uint32_t stride;uint32_t tiling; +uint32_t bpp;uint32_t *data;uint32_t size;struct {tests/i915/gem_concurrent_all.c +2
-0@@ -854,11 +854,13 @@ static void render_copy_bo(struct buffers *b, drm_intel_bo *dst, drm_intel_bo *s .size = b->npixels * 4, .num_tiles = b->npixels * 4, .stride = b->width * 4, + .bpp =32 , }, s = { .bo = src, .size = b->npixels * 4, .num_tiles = b->npixels * 4, .stride = b->width * 4, + .bpp = 32, };uint32_t swizzle;tests/i915/gem_gpgpu_fill.c +1
-0@@ -78,6 +78,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; } static voidtests/i915/gem_media_fill.c +1
-0@@ -81,6 +81,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; } static voidtests/i915/gem_ppgtt.c +2
-0@@ -76,6 +76,7 @@ static void scratch_buf_init(struct igt_buf *buf, buf->stride =STRIDE ; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; }static void scratch_buf_fini (struct igt_buf *buf)@@ -132,6 +133,7 @@ static void fork_rcs_copy(int target, drm_intel_bo **dst, int count, unsigned fl buf.stride =STRIDE ; buf.tiling =I915_TILING_NONE ; buf.size =SIZE ; + buf.bpp =32 ;for (int i =0 ; i <= target; i++) {struct igt_buf src;tests/i915/gem_read_read_speed.c +2
-0@@ -56,11 +56,13 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo *dst, drm_intel_bo *src) .size = width * height * 4, .num_tiles = width * height * 4, .stride = width * 4, + .bpp =32 , }, s = { .bo = src, .size = width * height * 4, .num_tiles = width * height * 4, .stride = width * 4, + .bpp = 32, };uint32_t swizzle;drm_intel_bo *bo = batch->bo;tests/i915/gem_render_copy.c +1
-0@@ -287,6 +287,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride =ALIGN (width *4 ,128 ); buf->size = buf->stride * height; buf->tiling = tiling; + buf->bpp =32 ; aux_width =scratch_buf_aux_width (buf); aux_height =scratch_buf_aux_height (buf);
tests/i915/gem_render_copy.c static void scratch_buf_init(data_t *data, struct igt_buf *buf, · line 313
Quoted 4 lines
tests/i915/gem_render_copy.c +1
-0@@ -309,6 +310,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = pitch; buf->tiling = tiling; buf->size = pitch * height; + buf->bpp =32 ;;
double ;;
Otherwise lgtm
Reviewed-by Ville Syrjälä <[email protected]>
Quoted 148 lines
tests/i915/gem_render_copy.c +0
-0}igt_assert (igt_buf_width (buf) == width);tests/i915/gem_render_copy_redux.c +1
-0@@ -109,6 +109,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; }static void scratch_buf_fini (data_t *data,struct igt_buf *buf)tests/i915/gem_render_linear_blits.c +6
-0@@ -111,11 +111,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[(i +1 ) % count]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[(i +1 ) % count] = start_val[i % count];@@ -134,11 +136,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[i % count]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[i % count] = start_val[(i +1 ) % count];@@ -159,11 +163,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[d]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[d] = start_val[s];tests/i915/gem_render_tiled_blits.c +2
-0@@ -69,6 +69,7 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val) tmp.stride =STRIDE ; tmp.tiling =I915_TILING_NONE ; tmp.size =SIZE ; + tmp.bpp =32 ;render_copy (batch,NULL , buf,0 ,0 ,WIDTH ,HEIGHT , &tmp,0 ,0 );if (snoop) {@@ -134,6 +135,7 @@ static void run_test (int fd, int count) buf[i].stride = pitch; buf[i].tiling = tiling; buf[i].size =SIZE ; + buf[i].bpp =32 ; start_val[i] = start;tests/i915/gem_ring_sync_copy.c +1
-0@@ -137,6 +137,7 @@ static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo) buf->stride =4 *WIDTH ; buf->tiling =I915_TILING_NONE ; buf->size =4 *WIDTH *HEIGHT ; + buf->bpp =32 ; } static void scratch_buf_init(data_t *data, struct igt_buf *buf,tests/i915/gem_stress.c +1
-0@@ -485,6 +485,7 @@ static void init_buffer(struct igt_buf *buf, unsigned size)igt_assert (buf->bo); buf->tiling =I915_TILING_NONE ; buf->stride =4096 ; + buf->bpp =32 ;sanitize_stride (buf);tests/kms_psr.c +1
-0@@ -153,6 +153,7 @@ static void scratch_buf_init(struct igt_buf *buf, drm_intel_bo *bo, buf->stride = stride; buf->tiling =I915_TILING_X ; buf->size = size; + buf->bpp =32 ; }static void fill_render (data_t *data,uint32_t handle,unsigned char color)tests/perf.c +1
-0@@ -501,6 +501,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size = size; + buf->bpp =32 ; } static voidtests/pm_sseu.c +1
-0@@ -303,6 +303,7 @@ gem_init(void) gem.buf.tiling =I915_TILING_NONE ; gem.buf.size = gem.buf.stride; gem.buf.bo =drm_intel_bo_alloc (gem.bufmgr,"" , gem.buf.size,4096 ); + gem.buf.bpp =32 ;igt_assert (gem.buf.bo); gem.init =4 ;Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Signature · 6 lines
Ville Syrjälä Intel _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Op 16-11-18 om 18:00 schreef Ville Syrjälä:
Quoted 341 lines · Maarten Lankhorst
Quoted 190 lines
We want to allow bpp = 8 or 16, so make sure we set the bpp in
igt_buf. This way we can extend rendercopy to support other values for bpp.Signed-off-by Maarten Lankhorst <[email protected]>--- lib/igt_draw.c | 2 ++ lib/intel_batchbuffer.c | 7 ++++--- lib/intel_batchbuffer.h | 2 ++ tests/i915/gem_concurrent_all.c | 2 ++ tests/i915/gem_gpgpu_fill.c | 1 + tests/i915/gem_media_fill.c | 1 + tests/i915/gem_ppgtt.c | 2 ++ tests/i915/gem_read_read_speed.c | 2 ++ tests/i915/gem_render_copy.c | 2 ++ tests/i915/gem_render_copy_redux.c | 1 + tests/i915/gem_render_linear_blits.c | 6 ++++++ tests/i915/gem_render_tiled_blits.c | 2 ++ tests/i915/gem_ring_sync_copy.c | 1 + tests/i915/gem_stress.c | 1 + tests/kms_psr.c | 1 + tests/perf.c | 1 + tests/pm_sseu.c | 1 + 17 files changed, 32 insertions(+), 3 deletions(-)lib/igt_draw.c +2
-0@@ -602,10 +602,12 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data, src_buf.stride = tmp.stride; src_buf.tiling =I915_TILING_NONE ; src_buf.size = tmp.size; + src_buf.bpp =32 ; dst_buf.bo = dst; dst_buf.stride = buf->stride; dst_buf.tiling = tiling; dst_buf.size = buf->size; + dst_buf.bpp =32 ; batch =intel_batchbuffer_alloc (cmd_data->bufmgr, devid);igt_assert (batch);lib/intel_batchbuffer.c +4
-3@@ -511,7 +511,7 @@ intel_copy_bo(struct intel_batchbuffer *batch,*/ unsigned igt_buf_width (const struct igt_buf *buf) { -return buf->stride/sizeof (uint32_t ); +return buf->stride/(buf->bpp /8 ); }/** @@ -764,7 +764,6 @@ void igt_blitter_fast_copy__raw(int fd,* @src_y: source pixel y-coordination * @width: width of the copied rectangle * @height: height of the copied rectangle -* @bpp: source and destination bits per pixel * @dst: destination i-g-t buffer object * @dst_delta: offset into the destination i-g-t bo * @dst_x: destination pixel x-coordination @@ -785,10 +784,12 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,uint32_t src_pitch, dst_pitch;uint32_t dword0, dword1; +igt_assert (src->bpp == dst->bpp); + src_pitch =fast_copy_pitch (src->stride, src->tiling); dst_pitch =fast_copy_pitch (dst->stride, src->tiling); dword0 =fast_copy_dword0 (src->tiling, dst->tiling); - dword1 =fast_copy_dword1 (src->tiling, dst->tiling, bpp); + dword1 =fast_copy_dword1 (src->tiling, dst->tiling, dst->bpp);#define CHECK_RANGE (x) ((x) >= 0 && (x) < (1 << 15)) assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&lib/intel_batchbuffer.h +2
-0@@ -215,6 +215,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,* @bo: underlying libdrm buffer object * @stride: stride of the buffer * @tiling: tiling mode bits +* @bpp: bits per pixel, 8, 16 or 32. * @data: pointer to the memory mapping of the buffer * @size: size of the buffer object * @@ -226,6 +227,7 @@ struct igt_buf {drm_intel_bo *bo;uint32_t stride;uint32_t tiling; +uint32_t bpp;uint32_t *data;uint32_t size;struct {tests/i915/gem_concurrent_all.c +2
-0@@ -854,11 +854,13 @@ static void render_copy_bo(struct buffers *b, drm_intel_bo *dst, drm_intel_bo *s .size = b->npixels * 4, .num_tiles = b->npixels * 4, .stride = b->width * 4, + .bpp =32 , }, s = { .bo = src, .size = b->npixels * 4, .num_tiles = b->npixels * 4, .stride = b->width * 4, + .bpp = 32, };uint32_t swizzle;tests/i915/gem_gpgpu_fill.c +1
-0@@ -78,6 +78,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; } static voidtests/i915/gem_media_fill.c +1
-0@@ -81,6 +81,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; } static voidtests/i915/gem_ppgtt.c +2
-0@@ -76,6 +76,7 @@ static void scratch_buf_init(struct igt_buf *buf, buf->stride =STRIDE ; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; }static void scratch_buf_fini (struct igt_buf *buf)@@ -132,6 +133,7 @@ static void fork_rcs_copy(int target, drm_intel_bo **dst, int count, unsigned fl buf.stride =STRIDE ; buf.tiling =I915_TILING_NONE ; buf.size =SIZE ; + buf.bpp =32 ;for (int i =0 ; i <= target; i++) {struct igt_buf src;tests/i915/gem_read_read_speed.c +2
-0@@ -56,11 +56,13 @@ static drm_intel_bo *rcs_copy_bo(drm_intel_bo *dst, drm_intel_bo *src) .size = width * height * 4, .num_tiles = width * height * 4, .stride = width * 4, + .bpp =32 , }, s = { .bo = src, .size = width * height * 4, .num_tiles = width * height * 4, .stride = width * 4, + .bpp = 32, };uint32_t swizzle;drm_intel_bo *bo = batch->bo;tests/i915/gem_render_copy.c +1
-0@@ -287,6 +287,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride =ALIGN (width *4 ,128 ); buf->size = buf->stride * height; buf->tiling = tiling; + buf->bpp =32 ; aux_width =scratch_buf_aux_width (buf); aux_height =scratch_buf_aux_height (buf);tests/i915/gem_render_copy.c static void scratch_buf_init(data_t *data, struct igt_buf *buf, · line 313
Quoted 4 lines
tests/i915/gem_render_copy.c +1
-0@@ -309,6 +310,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = pitch; buf->tiling = tiling; buf->size = pitch * height; + buf->bpp =32 ;;double ;;
Otherwise lgtm
Reviewed-by Ville Syrjälä <[email protected]>Quoted 141 lines
tests/i915/gem_render_copy.c +0
-0}igt_assert (igt_buf_width (buf) == width);tests/i915/gem_render_copy_redux.c +1
-0@@ -109,6 +109,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size =SIZE ; + buf->bpp =32 ; }static void scratch_buf_fini (data_t *data,struct igt_buf *buf)tests/i915/gem_render_linear_blits.c +6
-0@@ -111,11 +111,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[(i +1 ) % count]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[(i +1 ) % count] = start_val[i % count];@@ -134,11 +136,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[i % count]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[i % count] = start_val[(i +1 ) % count];@@ -159,11 +163,13 @@ static void run_test (int fd, int count) src.stride =STRIDE ; src.tiling =I915_TILING_NONE ; src.size =SIZE ; + src.bpp =32 ; dst.bo = bo[d]; dst.stride =STRIDE ; dst.tiling =I915_TILING_NONE ; dst.size =SIZE ; + dst.bpp =32 ;render_copy (batch,NULL , &src,0 ,0 ,WIDTH ,HEIGHT , &dst,0 ,0 ); start_val[d] = start_val[s];tests/i915/gem_render_tiled_blits.c +2
-0@@ -69,6 +69,7 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val) tmp.stride =STRIDE ; tmp.tiling =I915_TILING_NONE ; tmp.size =SIZE ; + tmp.bpp =32 ;render_copy (batch,NULL , buf,0 ,0 ,WIDTH ,HEIGHT , &tmp,0 ,0 );if (snoop) {@@ -134,6 +135,7 @@ static void run_test (int fd, int count) buf[i].stride = pitch; buf[i].tiling = tiling; buf[i].size =SIZE ; + buf[i].bpp =32 ; start_val[i] = start;tests/i915/gem_ring_sync_copy.c +1
-0@@ -137,6 +137,7 @@ static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo) buf->stride =4 *WIDTH ; buf->tiling =I915_TILING_NONE ; buf->size =4 *WIDTH *HEIGHT ; + buf->bpp =32 ; } static void scratch_buf_init(data_t *data, struct igt_buf *buf,tests/i915/gem_stress.c +1
-0@@ -485,6 +485,7 @@ static void init_buffer(struct igt_buf *buf, unsigned size)igt_assert (buf->bo); buf->tiling =I915_TILING_NONE ; buf->stride =4096 ; + buf->bpp =32 ;sanitize_stride (buf);tests/kms_psr.c +1
-0@@ -153,6 +153,7 @@ static void scratch_buf_init(struct igt_buf *buf, drm_intel_bo *bo, buf->stride = stride; buf->tiling =I915_TILING_X ; buf->size = size; + buf->bpp =32 ; }static void fill_render (data_t *data,uint32_t handle,unsigned char color)tests/perf.c +1
-0@@ -501,6 +501,7 @@ scratch_buf_init(drm_intel_bufmgr *bufmgr, buf->stride = stride; buf->tiling =I915_TILING_NONE ; buf->size = size; + buf->bpp =32 ; } static voidtests/pm_sseu.c +1
-0@@ -303,6 +303,7 @@ gem_init(void) gem.buf.tiling =I915_TILING_NONE ; gem.buf.size = gem.buf.stride; gem.buf.bo =drm_intel_bo_alloc (gem.bufmgr,"" , gem.buf.size,4096 ); + gem.buf.bpp =32 ;igt_assert (gem.buf.bo); gem.init =4 ;
Quoted 7 lines
Quoted 7 lines
Signature · 6 lines
2.19.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Thanks, pushed with fixups and assertion added to make sure src->bpp == dst->bpp. :)
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev
Patchwork
CI[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] lib/batchbuffer: Set bpp in igt_buf.
In reply to Maarten Lankhorst== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/batchbuffer: Set bpp in igt_buf.
URL : https://patchwork.freedesktop.org/series/52620/
State : success
== Summary ==
= CI Bug Log - changes from IGT_4720 -> IGTPW_2076 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52620/revisions/1/mbox/
== Known issues ==
Here are the changes found in IGTPW_2076 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ctx_create@basic-files:
fi-icl-u2: PASS -> DMESG-WARN (fdo#107724)
==== Possible fixes ====
igt@gem_exec_suspend@basic-s3:
fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS
igt@i915_selftest@live_sanitycheck:
fi-gdg-551: INCOMPLETE (fdo#108789) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
fdo#108789 https://bugs.freedesktop.org/show_bug.cgi?id=108789
== Participating hosts (53 -> 47) ==
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* IGT: IGT_4720 -> IGTPW_2076
CI_DRM_5159: af98442486c4eeed23ed036dfa2b556def4203bd @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2076: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2076/
IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2076/issues.html
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev
Patchwork
CI[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/3] lib/batchbuffer: Set bpp in igt_buf.
In reply to Maarten Lankhorst== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/batchbuffer: Set bpp in igt_buf.
URL : https://patchwork.freedesktop.org/series/52620/
State : success
== Summary ==
= CI Bug Log - changes from IGT_4720_full -> IGTPW_2076_full =
== Summary - WARNING ==
Minor unknown changes coming with IGTPW_2076_full need to be verified manually.
If you think the reported changes have nothing to do with the changes introduced in IGTPW_2076_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52620/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_2076_full:
=== IGT changes ===
==== Warnings ====
igt@kms_draw_crc@draw-method-rgb565-render-untiled:
shard-glk: SKIP -> PASS +3
shard-hsw: SKIP -> PASS +2
igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
shard-kbl: SKIP -> PASS +4
shard-apl: SKIP -> PASS +3
igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
shard-snb: SKIP -> PASS +2
igt@perf_pmu@rc6:
shard-kbl: PASS -> SKIP== Known issues ==
Here are the changes found in IGTPW_2076_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_atomic_transition@2x-modeset-transitions-fencing:
shard-hsw: PASS -> DMESG-FAIL (fdo#102614)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +2
igt@kms_color@pipe-a-legacy-gamma:
shard-apl: PASS -> FAIL (fdo#104782, fdo#108145)
igt@kms_color@pipe-c-ctm-max:
shard-apl: PASS -> FAIL (fdo#108147) +1
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-64x64-onscreen:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
shard-glk: PASS -> FAIL (fdo#103167) +2
igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
shard-kbl: NOTRUN -> FAIL (fdo#108145, fdo#108590)
igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
shard-kbl: NOTRUN -> FAIL (fdo#108145)
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: PASS -> FAIL (fdo#103166) +3
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166) +1
shard-kbl: PASS -> FAIL (fdo#103166)
igt@kms_sysfs_edid_timing:
shard-kbl: NOTRUN -> FAIL (fdo#100047)
igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
==== Possible fixes ====
igt@gem_eio@in-flight-1us:
shard-glk: FAIL (fdo#107799) -> PASS +1
igt@gem_eio@unwedge-stress:
shard-glk: FAIL -> PASS
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: INCOMPLETE (fdo#103665, fdo#106023, fdo#106887) -> PASS
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: FAIL (fdo#106641) -> PASS
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
shard-kbl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge:
shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-glk: FAIL (fdo#103232) -> PASS +3
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
shard-apl: FAIL (fdo#103167) -> PASS +1
shard-kbl: FAIL (fdo#103167) -> PASS +1
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
shard-glk: FAIL (fdo#103167) -> PASS +2
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-glk: FAIL (fdo#103166) -> PASS +2
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-apl: FAIL (fdo#103166) -> PASS +1
igt@kms_setmode@basic:
shard-hsw: FAIL (fdo#99912) -> PASS
igt@perf@blocking:
shard-hsw: FAIL (fdo#102252) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
fdo#107799 https://bugs.freedesktop.org/show_bug.cgi?id=107799
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
fdo#108590 https://bugs.freedesktop.org/show_bug.cgi?id=108590
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (7 -> 5) ==
Missing (2): shard-skl shard-iclb
== Build changes ==
* IGT: IGT_4720 -> IGTPW_2076
CI_DRM_5159: af98442486c4eeed23ed036dfa2b556def4203bd @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2076: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2076/
IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2076/shards.html
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