ARM: dts: at91: sama5d2: use the divided clock for SMC
PATCH 1/1 ARM: dts: at91: sama5d2: use the divided clock for SMC
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
--- arch/arm/boot/dts/sama5d2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/sama5d2.dtsi +1 -1
@@ -308,7 +308,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&h32ck>; status = "disabled"; nand_controller: nand-controller {
Signature · 1 line
2.17.1
Hello Romain,
Quoted 21 lines · Romain Izard
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
Signed-off-by Romain Izard <[email protected]>--- arch/arm/boot/dts/sama5d2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm/boot/dts/sama5d2.dtsi +0
-0
arch/arm/boot/dts/sama5d2.dtsi line 311
Quoted 5 lines
arch/arm/boot/dts/sama5d2.dtsi +1
-1@@ -308,7 +308,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&h32ck>;
You will have to rebase on top of at91-dt. And if I'm not mistaken, this line should be:
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
Quoted 6 lines
arch/arm/boot/dts/sama5d2.dtsi +0
-0status = "disabled"; nand_controller: nand-controller {Signature · 1 line
2.17.1
Signature · 3 lines
Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Le mar. 20 nov. 2018 ? 18:16, Alexandre Belloni
<[email protected]> a ?crit :
Quoted 34 lines
Hello Romain,
Quoted 21 lines · Romain Izard
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
Signed-off-by Romain Izard <[email protected]>--- arch/arm/boot/dts/sama5d2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm/boot/dts/sama5d2.dtsi +0
-0arch/arm/boot/dts/sama5d2.dtsi line 311
Quoted 5 lines
arch/arm/boot/dts/sama5d2.dtsi +1
-1@@ -308,7 +308,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&h32ck>;You will have to rebase on top of at91-dt. And if I'm not mistaken, this line should be:
Quoted 5 lines
+ clocks = <&pmc
PMC_TYPE_COREPMC_MCK2>;Quoted 3 lines
arch/arm/boot/dts/sama5d2.dtsi +0
-0status = "disabled"; nand_controller: nand-controller {
I guess you're right but this will only reach mainline in 4.21. I get slow flash access with 4.19 as well...
After a second look, it looks like the SAMA5D4 is affected too.
Best regards,
Signature · 1 line
Romain Izard
Quoted 36 lines · Romain Izard
Le mar. 20 nov. 2018 ? 18:16, Alexandre Belloni
<[email protected]> a ?crit :Quoted 34 lines
Hello Romain,
Quoted 21 lines · Romain Izard
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
Signed-off-by Romain Izard <[email protected]>--- arch/arm/boot/dts/sama5d2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm/boot/dts/sama5d2.dtsi +0
-0arch/arm/boot/dts/sama5d2.dtsi line 311
Quoted 5 lines
arch/arm/boot/dts/sama5d2.dtsi +1
-1@@ -308,7 +308,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&h32ck>;You will have to rebase on top of at91-dt. And if I'm not mistaken, this line should be:
Quoted 9 lines
Quoted 5 lines
+ clocks = <&pmc
PMC_TYPE_COREPMC_MCK2>;Quoted 3 lines
arch/arm/boot/dts/sama5d2.dtsi +0
-0status = "disabled"; nand_controller: nand-controller {I guess you're right but this will only reach mainline in 4.21. I get slow flash access with 4.19 as well...
Ok, this is super annoying, I'll try to get that as fixes on v4.20 and I'll rebase at91-dt on top of that...
Signature · 3 lines
Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Quoted 41 lines · Alexandre Belloni
Quoted 40 lines · Romain Izard
Le mar. 20 nov. 2018 ? 18:16, Alexandre Belloni
<[email protected]> a ?crit :Quoted 38 lines
Hello Romain,
Quoted 21 lines · Romain Izard
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
Signed-off-by Romain Izard <[email protected]>--- arch/arm/boot/dts/sama5d2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm/boot/dts/sama5d2.dtsi +0
-0arch/arm/boot/dts/sama5d2.dtsi line 311
Quoted 5 lines
arch/arm/boot/dts/sama5d2.dtsi +1
-1@@ -308,7 +308,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&h32ck>;You will have to rebase on top of at91-dt. And if I'm not mistaken, this line should be:
+ clocks = <&pmc
PMC_TYPE_COREPMC_MCK2>;Quoted 2 lines
arch/arm/boot/dts/sama5d2.dtsi +0
-0status = "disabled";
Quoted 9 lines
Quoted 5 lines
Quoted 1 line
arch/arm/boot/dts/sama5d2.dtsi line 314
Quoted 1 line
arch/arm/boot/dts/sama5d2.dtsi +0
-0nand_controller: nand-controller {I guess you're right but this will only reach mainline in 4.21. I get slow flash access with 4.19 as well...
Ok, this is super annoying, I'll try to get that as fixes on v4.20 and I'll rebase at91-dt on top of that...
So, I did that just now.
Signature · 3 lines
Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com