gpu: host1x: Resize channel register region on Tegra186 and later

From: Thierry Reding <[email protected]>

The number of syncpoints on Tegra186 is 576 and therefore no longer fits into 8 bits. Increase the size of the syncpoint ID field to 10 in order to accomodate all syncpoints.

Signed-off-by Thierry Reding <[email protected]>

---
  drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

drivers/gpu/host1x/hw/hw_host1x06_uclass.h +0 -0

index 4457486c72b0..e599e15bf999 100644

From: Thierry Reding <[email protected]>

The host1x hardware found on Tegra194 is very similar to the version found on Tegra186, with the notable exceptions of the increased number of syncpoints and mlocks. In addition, some rarely used features such as syncpoint wait bases were dropped and some registers had to move around to accomodate the increased number of syncpoints.

Signed-off-by Thierry Reding <[email protected]>

---
  drivers/gpu/host1x/Makefile                   |   3 +-
  drivers/gpu/host1x/dev.c                      |  13 ++
  drivers/gpu/host1x/hw/host1x07.c              |  44 +++++
  drivers/gpu/host1x/hw/host1x07.h              |  26 +++
  drivers/gpu/host1x/hw/host1x07_hardware.h     | 142 ++++++++++++++
  .../gpu/host1x/hw/hw_host1x07_hypervisor.h    |  32 ++++
  drivers/gpu/host1x/hw/hw_host1x07_uclass.h    | 181 ++++++++++++++++++
  drivers/gpu/host1x/hw/hw_host1x07_vm.h        |  46 +++++
  drivers/gpu/host1x/hw/syncpt_hw.c             |   4 +
  9 files changed, 490 insertions(+), 1 deletion(-)

create mode 100644 drivers/gpu/host1x/hw/host1x07.c create mode 100644 drivers/gpu/host1x/hw/host1x07.h create mode 100644 drivers/gpu/host1x/hw/host1x07_hardware.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_uclass.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_vm.h

...
+++ b/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h

drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h new file +21 -0

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#define HOST1X_HV_SYNCPT_PROT_EN			0x1ac4
+#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN			BIT(1)
+#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x)		(0x2020 + (x * 4))
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL			0x233c

drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h new file +1 -0

+#define HOST1X_HV_ICG_EN_OVERRIDE			0x2aa8

drivers/gpu/host1x/hw/hw_host1x07_uclass.h new file +181 -0

new file mode 100644
index 000000000000..7e4e3b377f91
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef HOST1X_HW_HOST1X07_UCLASS_H
+#define HOST1X_HW_HOST1X07_UCLASS_H
+
+static inline u32 host1x_uclass_incr_syncpt_r(void)
+{
+	return 0x0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT \
+	host1x_uclass_incr_syncpt_r()
+static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
+{
+	return (v & 0xff) << 10;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
+	host1x_uclass_incr_syncpt_cond_f(v)
+static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
+	host1x_uclass_incr_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_r(void)
+{
+	return 0x8;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT \
+	host1x_uclass_wait_syncpt_r()
+static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
+	host1x_uclass_wait_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
+	host1x_uclass_wait_syncpt_thresh_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_r(void)
+{
+	return 0x9;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
+	host1x_uclass_wait_syncpt_base_r()
+static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
+	host1x_uclass_wait_syncpt_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 16;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
+	host1x_uclass_wait_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
+	host1x_uclass_wait_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_r(void)
+{
+	return 0xb;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
+	host1x_uclass_load_syncpt_base_r()
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
+	host1x_uclass_load_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
+	host1x_uclass_load_syncpt_base_value_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
+	host1x_uclass_incr_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
+	host1x_uclass_incr_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_indoff_r(void)
+{
+	return 0x2d;
+}
+#define HOST1X_UCLASS_INDOFF \
+	host1x_uclass_indoff_r()
+static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
+{
+	return (v & 0xf) << 28;
+}
+#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
+	host1x_uclass_indoff_indbe_f(v)
+static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
+{
+	return (v & 0x1) << 27;
+}
+#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
+	host1x_uclass_indoff_autoinc_f(v)
+static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
+{
+	return (v & 0xff) << 18;
+}
+#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
+	host1x_uclass_indoff_indmodid_f(v)
+static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
+{
+	return (v & 0xffff) << 2;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+	host1x_uclass_indoff_indroffset_f(v)
+static inline u32 host1x_uclass_indoff_rwn_read_v(void)
+{
+	return 1;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+	host1x_uclass_indoff_indroffset_f(v)
+
+#endif

drivers/gpu/host1x/hw/hw_host1x07_vm.h new file +46 -0

new file mode 100644
index 000000000000..7e4629e77a2a
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#define HOST1X_CHANNEL_DMASTART				0x0000
+#define HOST1X_CHANNEL_DMASTART_HI			0x0004
+#define HOST1X_CHANNEL_DMAPUT				0x0008
+#define HOST1X_CHANNEL_DMAPUT_HI			0x000c
+#define HOST1X_CHANNEL_DMAGET				0x0010
+#define HOST1X_CHANNEL_DMAGET_HI			0x0014
+#define HOST1X_CHANNEL_DMAEND				0x0018
+#define HOST1X_CHANNEL_DMAEND_HI			0x001c
+#define HOST1X_CHANNEL_DMACTRL				0x0020
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP			BIT(0)
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST		BIT(1)
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET		BIT(2)
+#define HOST1X_CHANNEL_CMDFIFO_STAT			0x0024
+#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY		BIT(13)
+#define HOST1X_CHANNEL_CMDFIFO_RDATA			0x0028
+#define HOST1X_CHANNEL_CMDP_OFFSET			0x0030
+#define HOST1X_CHANNEL_CMDP_CLASS			0x0034
+#define HOST1X_CHANNEL_CHANNELSTAT			0x0038
+#define HOST1X_CHANNEL_CMDPROC_STOP			0x0048
+#define HOST1X_CHANNEL_TEARDOWN				0x004c
+
+#define HOST1X_SYNC_SYNCPT_CPU_INCR(x)			(0x6400 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x)	(0x6464 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x)	(0x652c + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x)	(0x6590 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT(x)				(0x8080 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_INT_THRESH(x)		(0x8d00 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP(x)			(0xa604 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v)			(((v) & 0x3f) << 8)

drivers/gpu/host1x/hw/syncpt_hw.c +2 -0

index a23bb3352d02..d946660d47f8 100644
@@ -37,10 +37,12 @@ static void syncpt_restore(struct host1x_syncpt *sp)
   */
  static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
  {
+#if HOST1X_HW < 7
  	struct host1x *host = sp->host;
 
  	host1x_sync_writel(host, sp->base_val,
  			   HOST1X_SYNC_SYNCPT_BASE(sp->id));
+#endif
  }
 
  /*

@@ -48,10 +50,12 @@ static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
   */
  static void syncpt_read_wait_base(struct host1x_syncpt *sp)

From: Thierry Reding <[email protected]>

The Video Image Composer (VIC) generation found on Tegra194 is the same as its predecessor found on Tegra186.

Signed-off-by Thierry Reding <[email protected]>

---
  drivers/gpu/drm/tegra/drm.c |  1 +
  drivers/gpu/drm/tegra/vic.c | 11 +++++++++++
  2 files changed, 12 insertions(+)

drivers/gpu/drm/tegra/drm.c +1 -0

index 65ea4988b332..4b70ce664c41 100644
@@ -1274,6 +1274,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
  	{ .compatible = "nvidia,tegra194-display", },
  	{ .compatible = "nvidia,tegra194-dc", },
  	{ .compatible = "nvidia,tegra194-sor", },
+	{ .compatible = "nvidia,tegra194-vic", },
  	{ /* sentinel */ }
  };
 

drivers/gpu/drm/tegra/vic.c +8 -0

index 9f657a63b0bb..94dd85c38e39 100644
@@ -282,10 +282,18 @@ static const struct vic_config vic_t186_config = {
  	.version = 0x18,
  };
 
+#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
+
+static const struct vic_config vic_t194_config = {
+	.firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
+	.version = 0x19,
+};
+
  static const struct of_device_id vic_match[] = {
  	{ .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
  	{ .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
  	{ .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
+	{ .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
  	{ },
  };
 

From: Thierry Reding <[email protected]>

The register region allocated per channel was decreased from 16384 bytes to 256 bytes on Tegra186 and later. Resize the region to make sure every channel (instead of only the first) is properly programmed.

Suggested-by Mikko Perttunen <[email protected]>

Signed-off-by Thierry Reding <[email protected]>

---
  drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)

drivers/gpu/host1x/hw/channel_hw.c +0 -1

index d188f9068b91..95ea81172a83 100644
@@ -26,7 +26,6 @@
  #include "../intr.h"
  #include "../job.h"
 
-#define HOST1X_CHANNEL_SIZE 16384
  #define TRACE_MAX_LENGTH 128U
 
  static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,

@@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
  static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
  			       unsigned int index)

From: Thierry Reding <[email protected]>

The register region allocated per channel was decreased from 16384 bytes to 256 bytes on Tegra186 and later. Resize the region to make sure every channel (instead of only the first) is properly programmed.

Suggested-by Mikko Perttunen <[email protected]>

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

drivers/gpu/host1x/hw/channel_hw.c +0 -1

index d188f9068b91..95ea81172a83 100644
@@ -26,7 +26,6 @@
 #include "../intr.h"
 #include "../job.h"
 
-#define HOST1X_CHANNEL_SIZE 16384
 #define TRACE_MAX_LENGTH 128U
 
 static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,

Quoted 24 lines · Thierry Reding

From: Thierry Reding <[email protected]>

The register region allocated per channel was decreased from 16384 bytes to 256 bytes on Tegra186 and later. Resize the region to make sure every channel (instead of only the first) is properly programmed.

Suggested-by Mikko Perttunen <[email protected]>

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

drivers/gpu/host1x/hw/channel_hw.c +0 -1

index d188f9068b91..95ea81172a83 100644
@@ -26,7 +26,6 @@
 #include "../intr.h"
 #include "../job.h"
 
-#define HOST1X_CHANNEL_SIZE 16384
 #define TRACE_MAX_LENGTH 128U
 

drivers/gpu/host1x/hw/channel_hw.c static void enable_gather_filter(struct host1x *host, · line 209

Quoted 11 lines

drivers/gpu/host1x/hw/channel_hw.c +5 -1

 static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,

@@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
 static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
                               unsigned int index)
 {
-       ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
+#if HOST1X_HW < 6
+       ch->regs = dev->regs + index * 0x4000;
+#else
+       ch->regs = dev->regs + index * 0x100;
+#endif

Just an observation ... this makes it impossible to build this module for multiple host1x hw revisions in the same kernel. I believe that supporting multiple platforms is frequently desirable, but perhaps there's more going on here (like arm64 vs arm32, etc).

Quoted 25 lines · Ilia Mirkin

Quoted 24 lines · Thierry Reding

From: Thierry Reding <[email protected]>

The register region allocated per channel was decreased from 16384 bytes to 256 bytes on Tegra186 and later. Resize the region to make sure every channel (instead of only the first) is properly programmed.

Suggested-by Mikko Perttunen <[email protected]>

Signed-off-by Thierry Reding <[email protected]>

---
 drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

drivers/gpu/host1x/hw/channel_hw.c +0 -1

index d188f9068b91..95ea81172a83 100644
@@ -26,7 +26,6 @@
 #include "../intr.h"
 #include "../job.h"
 
-#define HOST1X_CHANNEL_SIZE 16384
 #define TRACE_MAX_LENGTH 128U
 

Quoted 16 lines

drivers/gpu/host1x/hw/channel_hw.c static void enable_gather_filter(struct host1x *host, · line 209

Quoted 11 lines

drivers/gpu/host1x/hw/channel_hw.c +5 -1

 static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,

@@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
 static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
                               unsigned int index)
 {
-       ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
+#if HOST1X_HW < 6
+       ch->regs = dev->regs + index * 0x4000;
+#else
+       ch->regs = dev->regs + index * 0x100;
+#endif

Just an observation ... this makes it impossible to build this module for multiple host1x hw revisions in the same kernel. I believe that supporting multiple platforms is frequently desirable, but perhaps there's more going on here (like arm64 vs arm32, etc).

It actually does work. If you look close enough this file is included multiple times by generation specific source files. It's sort of like a template if you want.

It's not a design that's entirely to my liking, but it's not been a strong enough itch to scratch for me to have gotten around to changing how it works.