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dt-bindings: Add compatible string for LS1028A-QDS

PATCH New Bhaskar Upadhaya 3 participants 6 messages Nov 14, 2018 – Dec 8, 2018

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape
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Bhaskar Upadhaya

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#0 lore raw

PATCH v3 1/2 dt-bindings: Add compatible string for LS1028A-QDS

Signed-off-by Sudhanshu Gupta <[email protected]>
Signed-off-by Rai Harninder <[email protected]>
Signed-off-by Rajesh Bhagat <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>
Reviewed-by Rob Herring <[email protected]>

---
changes in v3:
no change

 Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
Documentation/devicetree/bindings/arm/fsl.txt +12 -0
index a6e0471..b2f20ede 100644
@@ -168,6 +168,18 @@ LS1012A ARMv8 based QDS Board
 Required root node properties:
     - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
 
+LS1028A SoC
+Required root node properties:
+    - compatible = "fsl,ls1028a";
+
+LS1028A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"
+
+LS1028A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
+
 LS1043A SoC
 Required root node properties:
     - compatible = "fsl,ls1043a";
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH v3 2/2 arm64: dts: Add support for NXP LS1028A SoC

LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache

Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC
Two PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Two high-speed USB 3.0 controllers with integrated PHY

Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:

- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.

- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.

- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board

Signed-off-by Sudhanshu Gupta <[email protected]>
Signed-off-by Rai Harninder <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>

---
changes in v3:
- provide spaces between child node and property
- move memory node from silicon file to board level DTS
- use macro IRQ_TYPE_LEVEL_HIGH instead of numbers

 arch/arm64/boot/dts/freescale/Makefile            |   2 +
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |  93 ++++++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |  73 +++++
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi    | 339 ++++++++++++++++++++++
 4 files changed, 507 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
arch/arm64/boot/dts/freescale/Makefile +2 -0
index 9a88530..7748e6d 100644
@@ -3,6 +3,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts new file +93 -0

93 lines not on this page · raw message

arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts new file +73 -0

73 lines not on this page · raw message

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi new file +339 -0

339 lines not on this page · raw message

Signature · 1 line
1.9.1
#2 lore raw

PATCH v3 2/2 arm64: dts: Add support for NXP LS1028A SoC

Quoted 25 lines · Bhaskar Upadhaya

LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache

Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC
Two PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Two high-speed USB 3.0 controllers with integrated PHY

Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:

- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.

- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.

Quoted 6 lines

- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board

Signed-off-by Sudhanshu Gupta <[email protected]>
Signed-off-by Rai Harninder <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>

@Leo, looks good to you?

Shawn

#3 lore raw

PATCH v3 2/2 arm64: dts: Add support for NXP LS1028A SoC

Quoted 36 lines

-----Original Message-----
From: Shawn Guo <[email protected]>
Sent: Monday, November 26, 2018 8:42 AM
To: Bhaskar Upadhaya <[email protected]>
Cc: devicetree at vger.kernel.org; Harninder Rai <[email protected]>; Sudhanshu Gupta <[email protected]>; linux-arm-
kernel at lists.infradead.org; Leo Li <[email protected]>
Subject: Re: [PATCH v3 2/2] arm64: dts: Add support for NXP LS1028A SoC

Quoted 24 lines · Bhaskar Upadhaya

LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache

Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC Two PCIe 3.0
controllers One serial ATA (SATA 3.0) controller Two high-speed USB 3.0 controllers with integrated PHY

Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:

- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.

- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.

Quoted 8 lines
Quoted 6 lines

- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board

Signed-off-by Sudhanshu Gupta <[email protected]>
Signed-off-by Rai Harninder <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>

@Leo, looks good to you?

Yes.

Acked-by Li Yang <[email protected]>

Regards,
Leo

Applied
#4 lore raw

PATCH v3 1/2 dt-bindings: Add compatible string for LS1028A-QDS

In reply to Bhaskar Upadhaya
Quoted 11 lines · Bhaskar Upadhaya
Signed-off-by Sudhanshu Gupta <[email protected]>
Signed-off-by Rai Harninder <[email protected]>
Signed-off-by Rajesh Bhagat <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>
Reviewed-by Rob Herring <[email protected]>

---
changes in v3:
no change

 Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Applied both, thanks.

#5 lore raw
Quoted 10 lines · Shawn Guo
Quoted 9 lines · Bhaskar Upadhaya
Signed-off-by Sudhanshu Gupta <[email protected]>
Signed-off-by Rai Harninder <[email protected]>
Signed-off-by Rajesh Bhagat <[email protected]>
Signed-off-by Bhaskar Upadhaya <[email protected]>
Reviewed-by Rob Herring <[email protected]>

---
changes in v3:
no change

Quoted 4 lines
Quoted 2 lines
 Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Applied both, thanks.

I dropped this patch from my 4.21 queue for now, as Rob is moving the bindings to json-schema during this development cycle. I will add the compatible back using json-schema format after 4.21-rc1 is available.

Shawn