dmaengine: xilinx_dma: commonize DMA copy size calculation
Subsystems (3)
PATCH v6 1/7 dmaengine: xilinx_dma: commonize DMA copy size calculation
This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size, and prepares for changes to the copy size calculation that will happen in following patches.
---
Changes in v4:
- introduce this patch in the patch series
Changes in v5:
None
Changes in v6:
- 2/7 was basically redoing what done here. Anticipate here the introduction of a local temporary variable so that 2/7 just add stuff
- add dma chan ptr argument to xilinx_calc_cma_copysize() to prepare for 2/7
- introduce max_buffer_len variable in advance, to prepare for 4/7
- reword for above changes
--- drivers/dma/xilinx/xilinx_dma.c | 39 ++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 8 deletions(-)
drivers/dma/xilinx/xilinx_dma.c +31 -8
@@ -423,6 +423,7 @@ struct xilinx_dma_config {* @rxs_clk: DMA s2mm stream clock * @nr_channels: Number of channels DMA device supports * @chan_id: DMA channel identifier +* @max_buffer_len: Max buffer length */ struct xilinx_dma_device {void __iomem *regs;
@@ -442,6 +443,7 @@ struct xilinx_dma_device {struct clk *rxs_clk;u32 nr_channels;u32 chan_id; +u32 max_buffer_len; };/* Macros */
@@ -957,6 +959,25 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)return 0 ; } +/** +* xilinx_dma_calc_copysize - Calculate the amount of data to copy +* @chan: Driver specific DMA channel +* @size: Total data that needs to be copied +* @done: Amount of data that has been already copied +* +* Return: Amount of data that has to be copied +*/ +static int xilinx_dma_calc_copysize (struct xilinx_dma_chan *chan, +int size,int done) +{ +size_t copy; + + copy =min_t (size_t, size - done, + chan->xdev->max_buffer_len); + +return copy; +} +/** * xilinx_dma_tx_status - Get DMA transaction status * @dchan: DMA channel
@@ -990,7 +1011,7 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,list_for_each_entry (segment, &desc->segments, node) { hw = &segment->hw; residue += (hw->control - hw->status) & -XILINX_DMA_MAX_TRANS_LEN ; + chan->xdev->max_buffer_len; } }spin_unlock_irqrestore (&chan->lock, flags);
@@ -1250,7 +1271,7 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)/* Start the transfer */ dma_ctrl_write (chan,XILINX_DMA_REG_BTT , - hw->control &XILINX_DMA_MAX_TRANS_LEN ); + hw->control & chan->xdev->max_buffer_len); }list_splice_tail_init (&chan->pending_list, &chan->active_list);
@@ -1353,7 +1374,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)/* Start the transfer */ dma_ctrl_write (chan,XILINX_DMA_REG_BTT , - hw->control &XILINX_DMA_MAX_TRANS_LEN ); + hw->control & chan->xdev->max_buffer_len); }list_splice_tail_init (&chan->pending_list, &chan->active_list);
@@ -1714,7 +1735,7 @@ xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,struct xilinx_cdma_tx_segment *segment;struct xilinx_cdma_desc_hw *hw; -if (!len || len >XILINX_DMA_MAX_TRANS_LEN ) +if (!len || len > chan->xdev->max_buffer_len)return NULL ; desc =xilinx_dma_alloc_tx_descriptor (chan);
@@ -1804,8 +1825,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(* Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy =min_t (size_t,sg_dma_len (sg) - sg_used, -XILINX_DMA_MAX_TRANS_LEN ); + copy =xilinx_dma_calc_copysize (chan,sg_dma_len (sg), + sg_used); hw = &segment->hw;/* Fill in the descriptor */
@@ -1909,8 +1930,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(* Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy =min_t (size_t, period_len - sg_used, -XILINX_DMA_MAX_TRANS_LEN ); + copy =xilinx_dma_calc_copysize (chan, period_len, + sg_used); hw = &segment->hw;xilinx_axidma_buf (chan, hw, buf_addr, sg_used, period_len * i);
@@ -2624,6 +2645,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)/* Retrieve the DMA engine properties from the device tree */ xdev->has_sg =of_property_read_bool (node,"xlnx,include-sg" ); + xdev->max_buffer_len =XILINX_DMA_MAX_TRANS_LEN ; +if (xdev->dma_config->dmatype ==XDMA_TYPE_AXIDMA ) xdev->mcdma =of_property_read_bool (node,"xlnx,mcdma" );
PATCH v6 2/7 dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors
Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length.
This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled.
This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address.
---
Changes in v2:
- don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey
- reword title
Changes in v3:
- fix bug introduced in v2: wrong copy size when DRE is enabled
- use implementation suggested by Radhey Shyam Pandey
Changes in v4:
- rework on the top of 1/6
Changes in v5:
- fix typo in commit title
- add hint about "DRE" meaning in commit message
Changes in v6:
None
--- drivers/dma/xilinx/xilinx_dma.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/dma/xilinx/xilinx_dma.c +9 -0
@@ -975,6 +975,15 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, copy =min_t (size_t, size - done, chan->xdev->max_buffer_len); +if ((copy + done < size) && + chan->xdev->common.copy_align) { +/* +* If this is not the last descriptor, make sure +* the next one will be properly aligned +*/ + copy =rounddown (copy, + (1 << chan->xdev->common.copy_align)); + }return copy; }
PATCH v6 3/7 dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
In reply to Andrea MerelloThe width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it.
---
Changes in v2:
- change property name
- property is now optional
- cc DT maintainer
Changes in v3:
- reword
- cc DT maintainerS and ML
Changes in v4:
- specify the unit, the valid range and the default value
Changes in v5:
- commit message trivial fix
- fix spaces before tab
Changes in v6:
None
--- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +4 -0
@@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
Rob Herring
maintainerRe: [PATCH v6 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
Quoted 24 lines · Andrea Merello
The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it.
Cc Rob Herring <[email protected]>Cc Mark Rutland <[email protected]>Cc Radhey Shyam Pandey <[email protected]>Signed-off-by Andrea Merello <[email protected]>Reviewed-by Radhey Shyam Pandey <[email protected]>---
Changes in v2:
- change property name
- property is now optional
- cc DT maintainer
Changes in v3:
- reword
- cc DT maintainerS and ML
Changes in v4:
- specify the unit, the valid range and the default value
Changes in v5:
- commit message trivial fix
- fix spaces before tab
Changes in v6:
None
Quoted 3 lines
--- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+)
Please add acks/reviewed-bys when posting new versions.
PATCH v6 4/7 dmaengine: xilinx_dma: program hardware supported buffer length
In reply to Andrea MerelloFrom: Radhey Shyam Pandey <[email protected]>
AXI-DMA IP supports configurable (c_sg_length_width) buffer length register width, hence read buffer length (xlnx,sg-length-width) DT property and ensure that driver doesn't program buffer length exceeding the supported limit. For VDMA and CDMA there is no change.
---
Changes in v2:
- drop original patch and replace with the one in Xilinx tree
Changes in v3:
- cc DT maintainers/ML
Changes in v4:
- upper bound for the property should be 26, not 23
- add warn for width > 23 as per xilinx original patch
- rework due to changes introduced in 1/6
Changes in v5:
None
Changes in v6:
None
--- drivers/dma/xilinx/xilinx_dma.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-)
drivers/dma/xilinx/xilinx_dma.c +20 -4
@@ -161,7 +161,9 @@#define XILINX_DMA_REG_BTT 0x28/* AXI DMA Specific Masks/Bit fields */ -#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) +#define XILINX_DMA_MAX_TRANS_LEN_MIN 8 +#define XILINX_DMA_MAX_TRANS_LEN_MAX 23 +#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26#define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)#define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)#define XILINX_DMA_CR_COALESCE_SHIFT 16
@@ -2622,7 +2624,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)struct xilinx_dma_device *xdev;struct device_node *child, *np = pdev->dev.of_node;struct resource *io; -u32 num_frames, addr_width; +u32 num_frames, addr_width, len_width;int i, err;/* Allocate and initialize the DMA engine structure */
@@ -2654,10 +2656,24 @@ static int xilinx_dma_probe(struct platform_device *pdev)/* Retrieve the DMA engine properties from the device tree */ xdev->has_sg =of_property_read_bool (node,"xlnx,include-sg" ); - xdev->max_buffer_len =XILINX_DMA_MAX_TRANS_LEN ; + xdev->max_buffer_len =GENMASK (XILINX_DMA_MAX_TRANS_LEN_MAX -1 ,0 ); -if (xdev->dma_config->dmatype ==XDMA_TYPE_AXIDMA ) +if (xdev->dma_config->dmatype ==XDMA_TYPE_AXIDMA ) { xdev->mcdma =of_property_read_bool (node,"xlnx,mcdma" ); +if (!of_property_read_u32 (node,"xlnx,sg-length-width" , + &len_width)) { +if (len_width <XILINX_DMA_MAX_TRANS_LEN_MIN || + len_width >XILINX_DMA_V2_MAX_TRANS_LEN_MAX ) { +dev_warn (xdev->dev, +"invalid xlnx,sg-length-width property value. Using default width\n" ); + }else { +if (len_width >XILINX_DMA_MAX_TRANS_LEN_MAX ) +dev_warn (xdev->dev,"Please ensure that IP supports buffer length > 23 bits\n" ); + xdev->max_buffer_len = +GENMASK (len_width -1 ,0 ); + } + } + }if (xdev->dma_config->dmatype ==XDMA_TYPE_VDMA ) { err = of_property_read_u32(node, "xlnx,num-fstores",
PATCH v6 5/7 dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather
In reply to Andrea MerelloThe AXIDMA and CDMA HW can be either direct-access or scatter-gather version. These are SW incompatible.
The driver can handle both versions: a DT property was used to tell the driver whether to assume the HW is in scatter-gather mode.
This patch makes the driver to autodetect this information. The DT property is not required anymore.
No changes for VDMA.
---
Changes in v2:
- autodetect only in !VDMA case
Changes in v3:
- cc DT maintainers/ML
Changes in v4:
- fix typos in commit message
Changes in v5:
None
Changes in v6:
None
--- drivers/dma/xilinx/xilinx_dma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
drivers/dma/xilinx/xilinx_dma.c +10 -4
@@ -86,6 +86,7 @@#define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)#define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)#define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) +#define XILINX_DMA_DMASR_SG_MASK BIT(3)#define XILINX_DMA_DMASR_IDLE BIT(1)#define XILINX_DMA_DMASR_HALTED BIT(0)#define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
@@ -412,7 +413,6 @@ struct xilinx_dma_config {* @dev: Device Structure * @common: DMA device structure * @chan: Driver specific DMA channel -* @has_sg: Specifies whether Scatter-Gather is present or not * @mcdma: Specifies whether Multi-Channel is present or not * @flush_on_fsync: Flush on frame sync * @ext_addr: Indicates 64 bit addressing is supported by dma device
@@ -432,7 +432,6 @@ struct xilinx_dma_device {struct device *dev;struct dma_device common;struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE ]; -bool has_sg;bool mcdma;u32 flush_on_fsync;bool ext_addr;
@@ -2417,7 +2416,6 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->dev = xdev->dev; chan->xdev = xdev; - chan->has_sg = xdev->has_sg; chan->desc_pendingcount =0x0 ; chan->ext_addr = xdev->ext_addr;/* This variable ensures that descriptors are not
@@ -2517,6 +2515,15 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->stop_transfer = xilinx_dma_stop_transfer; } +/* check if SG is enabled (only for AXIDMA and CDMA) */ +if (xdev->dma_config->dmatype !=XDMA_TYPE_VDMA ) { +if (dma_ctrl_read (chan,XILINX_DMA_REG_DMASR ) & +XILINX_DMA_DMASR_SG_MASK ) + chan->has_sg = true; +dev_dbg (chan->dev,"ch %d: SG %s\n" , chan->id, + chan->has_sg ?"enabled" :"disabled" ); + } +/* Initialize the tasklet */ tasklet_init (&chan->tasklet, xilinx_dma_do_tasklet, (unsigned long )chan);
@@ -2655,7 +2662,6 @@ static int xilinx_dma_probe(struct platform_device *pdev)return PTR_ERR (xdev->regs);/* Retrieve the DMA engine properties from the device tree */ - xdev->has_sg =of_property_read_bool (node,"xlnx,include-sg" ); xdev->max_buffer_len =GENMASK (XILINX_DMA_MAX_TRANS_LEN_MAX -1 ,0 );if (xdev->dma_config->dmatype ==XDMA_TYPE_AXIDMA ) {
PATCH v6 6/7 dt-bindings: dmaengine: xilinx_dma: drop include-sg property
In reply to Andrea MerelloThis property is not needed anymore, because the driver now autodetects it. Delete references in documentation.
---
Changes in v2:
- cc DT maintainer
Changes in v3:
- cc DT maintainerS/ML
Changes in v4:
None
Changes in v5:
None
Changes in v6:
Fix wrong property name in commit title
--- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 --- 1 file changed, 3 deletions(-)
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +0 -3
@@ -37,9 +37,6 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. -Optional properties: -- xlnx,include-sg: Tells configured for Scatter-mode in - the hardware. Optional properties for AXI DMA: - xlnx,sg-length-width: Should be set to the width in bits of the length register as configured in h/w. Takes values {8...26}. If the property
PATCH v6 7/7 dmaengine: xilinx_dma: Drop SG support for VDMA IP
In reply to Andrea Merelloxilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP.
This patch drops the never-taken branches.
---
Changes in V4: introduced this patch in series
Changes in v5:
None
Changes in v6:
None
--- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-)
drivers/dma/xilinx/xilinx_dma.c +32 -52
@@ -1100,6 +1100,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)struct xilinx_dma_tx_descriptor *desc, *tail_desc;u32 reg, j;struct xilinx_vdma_tx_segment *tail_segment; +struct xilinx_vdma_tx_segment *segment, *last =NULL ; +int i =0 ;/* This function was invoked with lock held */ if (chan->err)
@@ -1119,14 +1121,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment =list_last_entry (&tail_desc->segments, struct xilinx_vdma_tx_segment, node); -/* -* If hardware is idle, then all descriptors on the running lists are -* done, start new transfers -*/ -if (chan->has_sg) -dma_ctrl_write (chan,XILINX_DMA_REG_CURDESC , - desc->async_tx.phys); -/* Configure the hardware using info in the config structure */ if (chan->has_vflip) { reg =dma_read (chan,XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP );
@@ -1143,15 +1137,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN ; -/* -* With SG, start with circular mode, so that BDs can be fetched. -* In direct register mode, if not parking, enable circular mode -*/ -if (chan->has_sg || !config->park) - reg |=XILINX_DMA_DMACR_CIRC_EN ; - +/* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN ; +else + reg |=XILINX_DMA_DMACR_CIRC_EN ;dma_ctrl_write (chan,XILINX_DMA_REG_DMACR , reg);
@@ -1173,48 +1163,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)return ;/* Start the transfer */ -if (chan->has_sg) { -dma_ctrl_write (chan,XILINX_DMA_REG_TAILDESC , - tail_segment->phys); -list_splice_tail_init (&chan->pending_list, &chan->active_list); - chan->desc_pendingcount =0 ; - }else { -struct xilinx_vdma_tx_segment *segment, *last =NULL ; -int i =0 ; - -if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - -list_for_each_entry (segment, &desc->segments, node) { -if (chan->ext_addr) -vdma_desc_write_64 (chan, -XILINX_VDMA_REG_START_ADDRESS_64 (i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); -else -vdma_desc_write (chan, +if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + +list_for_each_entry (segment, &desc->segments, node) { +if (chan->ext_addr) +vdma_desc_write_64 (chan, +XILINX_VDMA_REG_START_ADDRESS_64 (i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); +else +vdma_desc_write (chan,XILINX_VDMA_REG_START_ADDRESS (i++), segment->hw.buf_addr); - last = segment; - } - -if (!last) -return ; + last = segment; + } -/* HW expects these parameters to be same for one transaction */ -vdma_desc_write (chan,XILINX_DMA_REG_HSIZE , last->hw.hsize); -vdma_desc_write (chan,XILINX_DMA_REG_FRMDLY_STRIDE , - last->hw.stride); -vdma_desc_write (chan,XILINX_DMA_REG_VSIZE , last->hw.vsize); +if (!last) +return ; - chan->desc_submitcount++; - chan->desc_pendingcount--; -list_del (&desc->node); -list_add_tail (&desc->node, &chan->active_list); -if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount =0 ; - } +/* HW expects these parameters to be same for one transaction */ +vdma_desc_write (chan,XILINX_DMA_REG_HSIZE , last->hw.hsize); +vdma_desc_write (chan,XILINX_DMA_REG_FRMDLY_STRIDE , + last->hw.stride); +vdma_desc_write (chan,XILINX_DMA_REG_VSIZE , last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; +list_del (&desc->node); +list_add_tail (&desc->node, &chan->active_list); +if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount =0 ; chan->idle = false; }
Quoted 4 lines · Andrea Merello
This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size, and prepares for changes to the copy size calculation that will happen in following patches.
Applied all, thanks