armv7r: K3: Allow SPL to run only on core 0
Subsystems (3)
PATCH 1/1 armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode.
If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode.
If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour.
---
- Depends on the series: https://patchwork.ozlabs.org/project/uboot/list/?series=73801
arch/arm/mach-k3/Makefile | 2 +- arch/arm/mach-k3/lowlevel_init.S | 20 ++++++++++++++++++++ include/configs/am65x_evm.h | 2 ++ 3 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-k3/lowlevel_init.S
arch/arm/mach-k3/Makefile +1 -1
@@ -5,5 +5,5 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o -obj-$(CONFIG_CPU_V7R) += r5_mpu.o +obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-y += common.o
arch/arm/mach-k3/lowlevel_init.S new file +20 -0
@@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <[email protected]> + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + and r0, #0xff + cmp r0, #0x0 + bne park_cpu + bx lr +park_cpu: + wfi + b park_cpu + +ENDPROC(lowlevel_init)
include/configs/am65x_evm.h +2 -0
@@ -29,7 +29,9 @@#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"#endif +#ifndef CONFIG_CPU_V7R #define CONFIG_SKIP_LOWLEVEL_INIT +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
Signature · 1 line
2.19.1
PATCH 1/1 armv7r: K3: Allow SPL to run only on core 0
Quoted 6 lines · Lokesh Vutla
Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode.
If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode.
Quoted 7 lines
If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour.
Signed-off-by Lokesh Vutla <[email protected]>
Signature · 8 lines
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Quoted 6 lines · Lokesh Vutla
Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode.
If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode.
Quoted 8 lines
If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour.
Signed-off-by Lokesh Vutla <[email protected]>Reviewed-by Tom Rini <[email protected]>
Applied to u-boot/master, thanks!
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