Add support for DM_USB and DM_USB_DEV for TI's DRA7 EVMs and AM57 EVMs platforms.

index 303e166..661cf61 100644
@@ -53,6 +53,29 @@ static int syscon_pre_probe(struct udevice *dev)
 #endif
 }
 
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+					       const char *name)
+{
+	struct udevice *syscon;
+	struct regmap *r;
+	int err;
+
+	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+					   name, &syscon);
+	if (err) {
+		dev_dbg(dev, "unable to find syscon device\n");
+		return ERR_PTR(err);
+	}
+
+	r = syscon_get_regmap(syscon);
+	if (!r) {
+		dev_dbg(dev, "unable to find regmap\n");
+		return ERR_PTR(-ENODEV);
+	}
+
+	return r;
+}
+
 int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 {
 	struct udevice *dev;

index 2aa73e5..3df96e3 100644
@@ -74,6 +74,19 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp);
 struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data);
 
 /**
+ * syscon_regmap_lookup_by_phandle() - Look up a controller by a phandle
+ *
+ * This operates by looking up the given name in the device (device
+ * tree property) of the device using the system controller.
+ *
+ * @dev:	Device using the system controller
+ * @name:	Name of property referring to the system controller
+ * @return	A pointer to the regmap if found, ERR_PTR(-ve) on error
+ */
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+					       const char *name);
+
+/**
  * syscon_get_first_range() - get the first memory range from a syscon regmap
  *
  * @driver_data:	Driver data value to look up

index 77c7928..a294dda 100644
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
+#include <regmap.h>
 #include <asm/test.h>
 #include <dm/test.h>
 #include <test/ut.h>

@@ -43,3 +44,31 @@ static int dm_test_syscon_by_driver_data(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_syscon_by_driver_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test system controller by phandle */
+static int dm_test_syscon_by_phandle(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct regmap *map;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_TEST_PROBE, "test4",
+					      &dev));
+
+	ut_assertok_ptr(syscon_regmap_lookup_by_phandle(dev, "first-syscon"));
+	map = syscon_regmap_lookup_by_phandle(dev, "first-syscon");
+	ut_assert(map);
+	ut_assert(!IS_ERR(map));
+	ut_asserteq(1, map->range_count);
+
+	ut_assertok_ptr(syscon_regmap_lookup_by_phandle(dev,
+							"second-sys-ctrl"));
+	map = syscon_regmap_lookup_by_phandle(dev, "second-sys-ctrl");
+	ut_assert(map);
+	ut_assert(!IS_ERR(map));
+	ut_asserteq(4, map->range_count);
+
+	ut_assert(IS_ERR(syscon_regmap_lookup_by_phandle(dev, "not-present")));
+
+	return 0;
+}
+DM_TEST(dm_test_syscon_by_phandle, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

index b22bbaf..e7e78e3 100644
@@ -141,7 +141,7 @@ static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 
 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
-	val &= ~PLL_SELFREQDCO_MASK;
+	val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 

@@ -265,10 +265,13 @@ static int pipe3_exit(struct phy *phy)
 		return -EBUSY;
 	}
 
-	val = readl(pipe3->pll_reset_reg);
-	writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
-	mdelay(1);
-	writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+	if (pipe3->pll_reset_reg) {
+		val = readl(pipe3->pll_reset_reg);
+		writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+		mdelay(1);
+		writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+	}
+
 	return 0;
 }
 

@@ -331,9 +334,11 @@ static int pipe3_phy_probe(struct udevice *dev)
 	if (!pipe3->power_reg)
 		return -EINVAL;
 
-	pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
-	if (!pipe3->pll_reset_reg)
-		return -EINVAL;
+	if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
+		pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
+		if (!pipe3->pll_reset_reg)
+			return -EINVAL;
+	}
 
 	pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
 

@@ -350,8 +355,19 @@ static struct pipe3_dpll_map dpll_map_sata[] = {
 	{ },                                    /* Terminator */
 };
 
+static struct pipe3_dpll_map dpll_map_usb[] = {
+	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
+	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
+	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
+	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
+	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
+	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
+	{ },					/* Terminator */
+};
+
 static const struct udevice_id pipe3_phy_ids[] = {
 	{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
+	{ .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
 	{ }
 };
 

196 lines not on this page · raw message

index 6d9be9b..bc6bba1 100644
@@ -119,6 +119,90 @@ struct dwc3_glue_ops {
 			       enum usb_dr_mode mode);
 };
 
+void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
+			    enum usb_dr_mode mode)
+{
+#define USBOTGSS_UTMI_OTG_STATUS		0x0084
+#define USBOTGSS_UTMI_OTG_OFFSET		0x0480
+
+/* UTMI_OTG_STATUS REGISTER */
+#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	BIT(31)
+#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	BIT(9)
+#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
+#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		BIT(4)
+#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	BIT(3)
+#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	BIT(2)
+#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	BIT(1)
+enum dwc3_omap_utmi_mode {
+	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
+	DWC3_OMAP_UTMI_MODE_HW,
+	DWC3_OMAP_UTMI_MODE_SW,
+};
+
+	u32 use_id_pin;
+	u32 host_mode;
+	u32 reg;
+	u32 utmi_mode;
+	u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
+
+	struct dwc3_glue_data *glue = dev_get_platdata(dev);
+	void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
+
+	if (device_is_compatible(dev, "ti,am437x-dwc3"))
+		utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
+
+	utmi_mode = dev_read_u32_default(dev, "utmi-mode",
+					 DWC3_OMAP_UTMI_MODE_UNKNOWN);
+	if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
+		debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
+		      dev->name);
+		mode = USB_DR_MODE_PERIPHERAL;
+	}
+
+	switch (mode)  {
+	case USB_DR_MODE_PERIPHERAL:
+		use_id_pin = 0;
+		host_mode = 0;
+		break;
+	case USB_DR_MODE_HOST:
+		use_id_pin = 0;
+		host_mode = 1;
+		break;
+	case USB_DR_MODE_OTG:
+	default:
+		use_id_pin = 1;
+		host_mode = 0;
+		break;
+	}
+
+	reg = readl(base + utmi_status_offset);
+
+	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
+	if (!use_id_pin)
+		reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
+
+	writel(reg, base + utmi_status_offset);
+
+	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
+		USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
+		USBOTGSS_UTMI_OTG_STATUS_IDDIG);
+
+	reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
+		USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
+
+	if (!host_mode)
+		reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
+			USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
+
+	writel(reg, base + utmi_status_offset);
+
+	unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops ti_ops = {
+	.select_dr_mode = dwc3_ti_select_dr_mode,
+};
+
 static int dwc3_glue_bind(struct udevice *parent)
 {
 	const void *fdt = gd->fdt_blob;

@@ -258,6 +342,7 @@ static int dwc3_glue_remove(struct udevice *dev)
 
 static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "xlnx,zynqmp-dwc3" },
+	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
 	{ }
 };
 

index bbe5445..b46bda2 100644
@@ -646,6 +646,19 @@ int dram_init_banksize(void)
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

@@ -685,6 +698,12 @@ int board_late_init(void)
 	if (board_is_dra71x_evm())
 		palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
 #endif
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3_1 at 48880000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3_2 at 488c0000"))
+		enable_usb_clocks(1);
+#endif
 	return 0;
 }
 

index 177a324..8c24d17 100644
@@ -675,6 +675,19 @@ out:
 	return;
 }
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+static int device_okay(const char *path)
+{
+	int node;
+
+	node = fdt_path_offset(gd->fdt_blob, path);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_is_enabled(gd->fdt_blob, node);
+}
+#endif
+
 int board_late_init(void)
 {
 	setup_board_eeprom_env();

@@ -714,6 +727,12 @@ int board_late_init(void)
 	board_ti_set_ethaddr(2);
 #endif
 
+#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
+	if (device_okay("/ocp/omap_dwc3_1 at 48880000"))
+		enable_usb_clocks(0);
+	if (device_okay("/ocp/omap_dwc3_2 at 488c0000"))
+		enable_usb_clocks(1);
+#endif
 	return 0;
 }
 

index b46bda2..0ddca29 100644
@@ -915,7 +915,7 @@ const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) && !CONFIG_IS_ENABLED(DM_USB)
 static struct dwc3_device usb_otg_ss1 = {
 	.maximum_speed = USB_SPEED_SUPER,
 	.base = DRA7_USB_OTG_SS1_BASE,

index 8c24d17..bed2eb3 100644
@@ -883,7 +883,7 @@ int spl_start_uboot(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) && !CONFIG_IS_ENABLED(DM_USB)
 static struct dwc3_device usb_otg_ss2 = {
 	.maximum_speed = USB_SPEED_HIGH,
 	.base = DRA7_USB_OTG_SS2_BASE,

@@ -912,9 +912,7 @@ int usb_gadget_handle_interrupts(int index)
 
 	return 0;
 }
-#endif /* CONFIG_USB_DWC3 */
 
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);

index 0ddca29..d69641e 100644
@@ -915,110 +915,6 @@ const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 }
 #endif
 
-#if defined(CONFIG_USB_DWC3) && !CONFIG_IS_ENABLED(DM_USB)
-static struct dwc3_device usb_otg_ss1 = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = DRA7_USB_OTG_SS1_BASE,
-	.tx_fifo_resize = false,
-	.index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
-	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
-	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
-	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
-	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
-	.index = 0,
-};
-
-static struct dwc3_device usb_otg_ss2 = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = DRA7_USB_OTG_SS2_BASE,
-	.tx_fifo_resize = false,
-	.index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
-	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
-	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
-	.index = 1,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	enable_usb_clocks(index);
-	switch (index) {
-	case 0:
-		if (init == USB_INIT_DEVICE) {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-		}
-
-		ti_usb_phy_uboot_init(&usb_phy1_device);
-		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
-		dwc3_uboot_init(&usb_otg_ss1);
-		break;
-	case 1:
-		if (init == USB_INIT_DEVICE) {
-			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-		}
-
-		ti_usb_phy_uboot_init(&usb_phy2_device);
-		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-		dwc3_uboot_init(&usb_otg_ss2);
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	switch (index) {
-	case 0:
-	case 1:
-		ti_usb_phy_uboot_exit(index);
-		dwc3_uboot_exit(index);
-		dwc3_omap_uboot_exit(index);
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-	disable_usb_clocks(index);
-	return 0;
-}
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 int spl_start_uboot(void)
 {

index bed2eb3..8dfb2ee 100644
@@ -883,91 +883,6 @@ int spl_start_uboot(void)
 }
 #endif
 
-#if defined(CONFIG_USB_DWC3) && !CONFIG_IS_ENABLED(DM_USB)
-static struct dwc3_device usb_otg_ss2 = {
-	.maximum_speed = USB_SPEED_HIGH,
-	.base = DRA7_USB_OTG_SS2_BASE,
-	.tx_fifo_resize = false,
-	.index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
-	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
-	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
-	.index = 1,
-};
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	enable_usb_clocks(index);
-	switch (index) {
-	case 0:
-		if (init == USB_INIT_DEVICE) {
-			printf("port %d can't be used as device\n", index);
-			disable_usb_clocks(index);
-			return -EINVAL;
-		}
-		break;
-	case 1:
-		if (init == USB_INIT_DEVICE) {
-#ifdef CONFIG_USB_DWC3
-			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-			ti_usb_phy_uboot_init(&usb_phy2_device);
-			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-			dwc3_uboot_init(&usb_otg_ss2);
-#endif
-		} else {
-			printf("port %d can't be used as host\n", index);
-			disable_usb_clocks(index);
-			return -EINVAL;
-		}
-
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-#ifdef CONFIG_USB_DWC3
-	switch (index) {
-	case 0:
-	case 1:
-		if (init == USB_INIT_DEVICE) {
-			ti_usb_phy_uboot_exit(index);
-			dwc3_uboot_exit(index);
-			dwc3_omap_uboot_exit(index);
-		}
-		break;
-	default:
-		printf("Invalid Controller Index\n");
-	}
-#endif
-	disable_usb_clocks(index);
-	return 0;
-}
-#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
-
 #ifdef CONFIG_DRIVER_TI_CPSW
 
 /* Delay value to add to calibrated value */