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Restore workarounds after engine reset and unify their handling

PATCH Superseded Tvrtko Ursulin 4 participants 25 messages Nov 30, 2018 – Dec 3, 2018

Subsystems (2)
DRM drivers Intel i915

v2 of 4 Superseded Latest is v4 →

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Tvrtko Ursulin

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#0 lore raw

v2 cover Restore workarounds after engine reset and unify their handling

From: Tvrtko Ursulin <[email protected]>

First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds").

But since it was discovered to be unsafe to simply re-apply all of them, against a possibly active GPU, and potentially from IRQ context, the approach taken was to split GT workarounds and per-engine workarounds. Latter so far contain the ones living in the 0x2xxx and 0xbxxx range, which were empirically shown to be lost after RCS reset.

This way only a smaller set of affected workarounds can be applied after engine resetm, which is done with irq safe read-modify-write cycle.

The series is structured like this so first two patches are as standalone as possible so it is easy (easier) to backport them. The rest of the series cleans up the whole workaround handling by moving all four classes of them to a common framework.

v2:
* One patch less due removing verification after engine reset.
* See patch change logs.

Tvrtko Ursulin (7):
drm/i915: Record GT workarounds in a list
drm/i915: Introduce per-engine workarounds
drm/i915: Verify GT workaround state after GPU init drm/i915/selftests: Add tests for GT and engine workaround
verification
drm/i915: Move register white-listing to the common workaround
framework
drm/i915: Fuse per-context workaround handling with the common
framework
drm/i915: Trim unused workaround list entries

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c           |  12 +-
 drivers/gpu/drm/i915/i915_drv.c               |   2 +
 drivers/gpu/drm/i915/i915_drv.h               |  17 +-
 drivers/gpu/drm/i915/i915_gem.c               |   5 +
 drivers/gpu/drm/i915/i915_gem_context.c       |   6 +-
 drivers/gpu/drm/i915/intel_engine_cs.c        |   4 +
 drivers/gpu/drm/i915/intel_lrc.c              |   5 +
 drivers/gpu/drm/i915/intel_ringbuffer.h       |   4 +
 drivers/gpu/drm/i915/intel_workarounds.c      | 879 +++++++++++-------
 drivers/gpu/drm/i915/intel_workarounds.h      |  31 +-
 drivers/gpu/drm/i915/selftests/igt_common.c   |  44 +
 drivers/gpu/drm/i915/selftests/igt_common.h   |  15 +
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  51 +-
 .../drm/i915/selftests/intel_workarounds.c    | 187 +++-
 15 files changed, 823 insertions(+), 440 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.c
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.h
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#1 lore raw

PATCH 1/7 drm/i915: Record GT workarounds in a list

From: Tvrtko Ursulin <[email protected]>

To enable later verification of GT workaround state at various stages of driver lifetime, we record the list of applicable ones per platforms to a list, from which they are also applied.

The added data structure is a simple array of register, mask and value items, which is allocated on demand as workarounds are added to the list.

This is a temporary implementation which later in the series gets fused with the existing per context workaround list handling. It is separated at this stage since the following patch fixes a bug which needs to be as easy to backport as possible.

Also, since in the following patch we will be adding a new class of workarounds (per engine) which can be applied from interrupt context, we straight away make the provision for safe read-modify-write cycle.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.c          |   1 +
 drivers/gpu/drm/i915/i915_drv.h          |   2 +
 drivers/gpu/drm/i915/i915_gem.c          |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 443 +++++++++++++++--------
 drivers/gpu/drm/i915/intel_workarounds.h |  22 ++
 5 files changed, 327 insertions(+), 143 deletions(-)
drivers/gpu/drm/i915/i915_drv.c +1 -0
index e39016713464..2f3dc1cf83a6 100644
@@ -1453,6 +1453,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	intel_uncore_sanitize(dev_priv);
 
+	intel_gt_workarounds_init(dev_priv);
 	i915_gem_load_init_fences(dev_priv);
 
 	/* On the 945G/GM, the chipset reports the MSI capability on the
drivers/gpu/drm/i915/i915_drv.h +2 -0
index 43ac6873a2bb..9ddbcc1f3554 100644
@@ -69,6 +69,7 @@
 #include "intel_ringbuffer.h"
 #include "intel_uncore.h"
 #include "intel_wopcm.h"
+#include "intel_workarounds.h"
 #include "intel_uc.h"
 
 #include "i915_gem.h"

@@ -1652,6 +1653,7 @@ struct drm_i915_private {
 	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
 	struct i915_workarounds workarounds;
+	struct i915_wa_list gt_wa_list;
 
 	struct i915_frontbuffer_tracking fb_tracking;
drivers/gpu/drm/i915/i915_gem.c +2 -0
index c55b1f75c980..18adb3dd1fcd 100644
@@ -5706,6 +5706,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
 	i915_gem_contexts_fini(dev_priv);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
+	intel_wa_list_free(&dev_priv->gt_wa_list);
+
 	intel_cleanup_gt_powersave(dev_priv);
 
 	intel_uc_fini_misc(dev_priv);
drivers/gpu/drm/i915/intel_workarounds.c +300 -143

625 lines not on this page · raw message

drivers/gpu/drm/i915/intel_workarounds.h +22 -0
index b11d0623e626..64aed9cf0200 100644
@@ -7,9 +7,31 @@
 #ifndef _I915_WORKAROUNDS_H_
 #define _I915_WORKAROUNDS_H_
 
+#include <linux/slab.h>
+
+struct i915_wa {
+	i915_reg_t	  reg;
+	u32		  mask;
+	u32		  val;
+};
+
+struct i915_wa_list {
+	const char	*name;
+	unsigned int 	count;
+	struct i915_wa	*list;
+	unsigned int	__size;
+};
+
+static inline void intel_wa_list_free(struct i915_wa_list *wal)
+{
+	kfree(wal->list);
+	memset(wal, 0, sizeof(*wal));
+}
+
 int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv);
 int intel_ctx_workarounds_emit(struct i915_request *rq);
 
+void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
 
 void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
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Reviewed-by on v1 1/7
#2 lore raw

Re: [PATCH 1/7] drm/i915: Record GT workarounds in a list

Quoting Tvrtko Ursulin (2018-11-30 17:44:06)

Quoted 155 lines

From: Tvrtko Ursulin <[email protected]>

To enable later verification of GT workaround state at various stages of driver lifetime, we record the list of applicable ones per platforms to a list, from which they are also applied.

The added data structure is a simple array of register, mask and value items, which is allocated on demand as workarounds are added to the list.

This is a temporary implementation which later in the series gets fused with the existing per context workaround list handling. It is separated at this stage since the following patch fixes a bug which needs to be as easy to backport as possible.

Also, since in the following patch we will be adding a new class of workarounds (per engine) which can be applied from interrupt context, we straight away make the provision for safe read-modify-write cycle.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.c          |   1 +
 drivers/gpu/drm/i915/i915_drv.h          |   2 +
 drivers/gpu/drm/i915/i915_gem.c          |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 443 +++++++++++++++--------
 drivers/gpu/drm/i915/intel_workarounds.h |  22 ++
 5 files changed, 327 insertions(+), 143 deletions(-)
drivers/gpu/drm/i915/i915_drv.c +1 -0
index e39016713464..2f3dc1cf83a6 100644
@@ -1453,6 +1453,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
        intel_uncore_sanitize(dev_priv);
 
+       intel_gt_workarounds_init(dev_priv);
        i915_gem_load_init_fences(dev_priv);
 
        /* On the 945G/GM, the chipset reports the MSI capability on the
drivers/gpu/drm/i915/i915_drv.h +2 -0
index 43ac6873a2bb..9ddbcc1f3554 100644
@@ -69,6 +69,7 @@
 #include "intel_ringbuffer.h"
 #include "intel_uncore.h"
 #include "intel_wopcm.h"
+#include "intel_workarounds.h"
 #include "intel_uc.h"
 
 #include "i915_gem.h"

@@ -1652,6 +1653,7 @@ struct drm_i915_private {
        int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
        struct i915_workarounds workarounds;
+       struct i915_wa_list gt_wa_list;
 
        struct i915_frontbuffer_tracking fb_tracking;
drivers/gpu/drm/i915/i915_gem.c +2 -0
index c55b1f75c980..18adb3dd1fcd 100644
@@ -5706,6 +5706,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
        i915_gem_contexts_fini(dev_priv);
        mutex_unlock(&dev_priv->drm.struct_mutex);
 
+       intel_wa_list_free(&dev_priv->gt_wa_list);
+
        intel_cleanup_gt_powersave(dev_priv);
 
        intel_uc_fini_misc(dev_priv);
drivers/gpu/drm/i915/intel_workarounds.c +62 -2
index e5cd6c6c66c3..ff20ebf9e040 100644
@@ -48,6 +48,18 @@
  * - Public functions to init or apply the given workaround type.
  */
 
+static void wa_init_start(struct i915_wa_list *wal, const char *name)
+{
+       wal->name = name;
+}
+
+static void wa_init_finish(struct i915_wa_list *wal)
+{
+       if (wal->count)
+               DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
+                                wal->count, wal->name);
+}
+
 static void wa_add(struct drm_i915_private *i915,
                   i915_reg_t reg, const u32 mask, const u32 val)
 {

@@ -575,28 +587,88 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
        return 0;
 }
 
-static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+static void
+wal_add(struct i915_wa_list *wal, const struct i915_wa *wa)
+{
+       const unsigned int grow = 4;
+
+       if (wal->__size == wal->count) {
+               struct i915_wa *list;
+
+               list = kcalloc(wal->__size + grow, sizeof(*wa), GFP_KERNEL);
+               if (!list) {
+                       DRM_ERROR("No space for workaround init!\n");
+                       return;
+               }
+
+               if (wal->list)
+                       memcpy(list, wal->list, sizeof(*wa) * wal->count);
+
+               wal->list = list;
+               wal->__size += grow;
+       }
+
+       memcpy(&wal->list[wal->count], wa, sizeof(*wa));
+       wal->count++;
+}
+
+static void
+wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
+       struct i915_wa wa = {
+               .reg = reg,
+               .mask = val,
+               .val = _MASKED_BIT_ENABLE(val)
+       };
+
+       wal_add(wal, &wa);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+                  u32 val)
+{
+       struct i915_wa wa = {
+               .reg = reg,
+               .mask = mask,
+               .val = val
+       };
+
+       wal_add(wal, &wa);
 }
 
-static void chv_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+static void
+wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
+       wa_write_masked_or(wal, reg, ~0, val);

drivers/gpu/drm/i915/intel_workarounds.c int intel_ctx_workarounds_emit(struct i915_request *rq) · line 652

Quoted 10 lines
drivers/gpu/drm/i915/intel_workarounds.c +6 -1
 }
 
-static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+static void
+wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
+       wa_write_masked_or(wal, reg, val, val);
+}
+
+static void gen9_gt_workarounds_init(struct drm_i915_private *dev_priv)

Sneaky observation is that we now don't need dev_priv throughout the init path, so a bonus s/dev_priv/i915/.

Reviewed-by Chris Wilson <[email protected]>

-Chris
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author
#3 lore raw

PATCH 2/7 drm/i915: Introduce per-engine workarounds

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds").

Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far the registers in 0x2xxx and 0xbxxx address range have been identified to be affected.

This losing of applied workarounds has obvious negative effects and can even lead to hard system hangs (see the linked Bugzilla).

Rather than just restoring this re-application, because we have also observed that it is not safe to just re-write all GT workarounds after engine resets (GPU might be live and weird hardware states can happen), we introduce a new class of per-engine workarounds and move only the affected GT workarounds over.

Using the framework introduced in the previous patch, we therefore after engine reset, re-apply only the workarounds living in the affected MMIO address ranges.

Signed-off-by Tvrtko Ursulin <[email protected]>

Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945

Fixes 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds")
Cc Mika Kuoppala <[email protected]>
Cc Ville Syrjälä <[email protected]>
Cc Chris Wilson <[email protected]>
Cc Jani Nikula <[email protected]>
Cc Joonas Lahtinen <[email protected]>
Cc Rodrigo Vivi <[email protected]>
Cc [email protected]
---
 drivers/gpu/drm/i915/intel_engine_cs.c   |   2 +
 drivers/gpu/drm/i915/intel_lrc.c         |   4 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 249 +++++++++++++----------
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 5 files changed, 148 insertions(+), 112 deletions(-)
drivers/gpu/drm/i915/intel_engine_cs.c +2 -0
index 759c0fd58f8c..ef5d202e9d45 100644
@@ -723,6 +723,8 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 	__intel_context_unpin(i915->kernel_context, engine);
 
 	i915_timeline_fini(&engine->timeline);
+
+	intel_wa_list_free(&engine->wa_list);
 }
 
 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
drivers/gpu/drm/i915/intel_lrc.c +4 -0
index 11f4e6148557..dfafc3f710d6 100644
@@ -1617,6 +1617,8 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
 
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
 {
+	intel_engine_workarounds_apply(engine);
+
 	intel_mocs_init_engine(engine);
 
 	intel_engine_reset_breadcrumbs(engine);

@@ -2314,6 +2316,8 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
 			  ret);
 	}
 
+	intel_engine_workarounds_init(engine);
+
 	return 0;
 
 err_cleanup_common:
drivers/gpu/drm/i915/intel_ringbuffer.h +2 -0
index 8a2270b209b0..c5ff3d31cab7 100644
@@ -15,6 +15,7 @@
 #include "i915_selftest.h"
 #include "i915_timeline.h"
 #include "intel_gpu_commands.h"
+#include "intel_workarounds.h"
 
 struct drm_printer;
 struct i915_sched_attr;

@@ -451,6 +452,7 @@ struct intel_engine_cs {
 
 	struct intel_hw_status_page status_page;
 	struct i915_ctx_workarounds wa_ctx;
+	struct i915_wa_list wa_list;
 	struct i915_vma *scratch;
 
 	u32             irq_keep_mask; /* always keep these interrupts */
drivers/gpu/drm/i915/intel_workarounds.c +137 -112

326 lines not on this page · raw message

drivers/gpu/drm/i915/intel_workarounds.h +3 -0
index 64aed9cf0200..2998767d51ca 100644
@@ -36,4 +36,7 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
 
 void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
 
+void intel_engine_workarounds_init(struct intel_engine_cs *engine);
+void intel_engine_workarounds_apply(struct intel_engine_cs *engine);
+
 #endif
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#4 lore raw

Re: [PATCH 2/7] drm/i915: Introduce per-engine workarounds

Quoting Tvrtko Ursulin (2018-11-30 17:44:07)

drivers/gpu/drm/i915/intel_workarounds.c void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine) · line 1240

Quoted 8 lines
drivers/gpu/drm/i915/intel_workarounds.c +8 -0
+static void xcs_engine_wa_init(struct intel_engine_cs *engine)
+{
+       struct drm_i915_private *i915 = engine->i915;
+       struct i915_wa_list *wal = &engine->wa_list;
+
+       if (IS_KABYLAKE(i915)) {
+               /* WaKBLVECSSemaphoreWaitPoll:kbl */
+               if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {

IS_KBL_REVID includes IS_KABYLAKE.
-Chris
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Reviewed-by on v1 2/7
#5 lore raw

Re: [PATCH 2/7] drm/i915: Introduce per-engine workarounds

In reply to Tvrtko Ursulin

Quoting Tvrtko Ursulin (2018-11-30 17:44:07)

Quoted 25 lines

From: Tvrtko Ursulin <[email protected]>

We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds").

Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far the registers in 0x2xxx and 0xbxxx address range have been identified to be affected.

This losing of applied workarounds has obvious negative effects and can even lead to hard system hangs (see the linked Bugzilla).

Rather than just restoring this re-application, because we have also observed that it is not safe to just re-write all GT workarounds after engine resets (GPU might be live and weird hardware states can happen), we introduce a new class of per-engine workarounds and move only the affected GT workarounds over.

Using the framework introduced in the previous patch, we therefore after engine reset, re-apply only the workarounds living in the affected MMIO address ranges.

Signed-off-by Tvrtko Ursulin <[email protected]>

Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945

Quoted 8 lines
Fixes 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds")
Cc Mika Kuoppala <[email protected]>
Cc Ville Syrjälä <[email protected]>
Cc Chris Wilson <[email protected]>
Cc Jani Nikula <[email protected]>
Cc Joonas Lahtinen <[email protected]>
Cc Rodrigo Vivi <[email protected]>
Cc [email protected]

Give or take the naming arguments,

Reviewed-by Chris Wilson <[email protected]>

-Chris
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maintainer Acked-by on v1 2/7
#6 lore raw

Re: [PATCH 2/7] drm/i915: Introduce per-engine workarounds

In reply to Tvrtko Ursulin
Quoted 339 lines · Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds").

Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far the registers in 0x2xxx and 0xbxxx address range have been identified to be affected.

This losing of applied workarounds has obvious negative effects and can even lead to hard system hangs (see the linked Bugzilla).

Rather than just restoring this re-application, because we have also observed that it is not safe to just re-write all GT workarounds after engine resets (GPU might be live and weird hardware states can happen), we introduce a new class of per-engine workarounds and move only the affected GT workarounds over.

Using the framework introduced in the previous patch, we therefore after engine reset, re-apply only the workarounds living in the affected MMIO address ranges.

Signed-off-by Tvrtko Ursulin <[email protected]>

Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945

Fixes 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds")
Cc Mika Kuoppala <[email protected]>
Cc Ville Syrjälä <[email protected]>
Cc Chris Wilson <[email protected]>
Cc Jani Nikula <[email protected]>
Cc Joonas Lahtinen <[email protected]>
Cc Rodrigo Vivi <[email protected]>
Cc [email protected]
---
 drivers/gpu/drm/i915/intel_engine_cs.c   |   2 +
 drivers/gpu/drm/i915/intel_lrc.c         |   4 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +
 drivers/gpu/drm/i915/intel_workarounds.c | 249 +++++++++++++----------
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +
 5 files changed, 148 insertions(+), 112 deletions(-)
drivers/gpu/drm/i915/intel_engine_cs.c +2 -0
index 759c0fd58f8c..ef5d202e9d45 100644
@@ -723,6 +723,8 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 	__intel_context_unpin(i915->kernel_context, engine);
 
 	i915_timeline_fini(&engine->timeline);
+
+	intel_wa_list_free(&engine->wa_list);
 }
 
 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
drivers/gpu/drm/i915/intel_lrc.c +4 -0
index 11f4e6148557..dfafc3f710d6 100644
@@ -1617,6 +1617,8 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
 
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
 {
+	intel_engine_workarounds_apply(engine);
+
 	intel_mocs_init_engine(engine);
 
 	intel_engine_reset_breadcrumbs(engine);

@@ -2314,6 +2316,8 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
 			  ret);
 	}
 
+	intel_engine_workarounds_init(engine);
+
 	return 0;
 
 err_cleanup_common:
drivers/gpu/drm/i915/intel_ringbuffer.h +2 -0
index 8a2270b209b0..c5ff3d31cab7 100644
@@ -15,6 +15,7 @@
 #include "i915_selftest.h"
 #include "i915_timeline.h"
 #include "intel_gpu_commands.h"
+#include "intel_workarounds.h"
 
 struct drm_printer;
 struct i915_sched_attr;

@@ -451,6 +452,7 @@ struct intel_engine_cs {
 
 	struct intel_hw_status_page status_page;
 	struct i915_ctx_workarounds wa_ctx;
+	struct i915_wa_list wa_list;
 	struct i915_vma *scratch;
 
 	u32             irq_keep_mask; /* always keep these interrupts */
drivers/gpu/drm/i915/intel_workarounds.c +42 -112
index ff20ebf9e040..be63a2af3481 100644
@@ -653,17 +653,6 @@ static void gen9_gt_workarounds_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_wa_list *wal = &dev_priv->gt_wa_list;
 
-	/* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
-	wa_masked_en(wal,
-		     GEN9_CSFE_CHICKEN1_RCS,
-		     GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
-
-
-	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
-	wa_write_or(wal,
-		    BDW_SCRATCH1,
-		    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
-
 	/* WaDisableKillLogic:bxt,skl,kbl */
 	if (!IS_COFFEELAKE(dev_priv))
 		wa_write_or(wal,

@@ -685,24 +674,6 @@ static void gen9_gt_workarounds_init(struct drm_i915_private *dev_priv)
 	wa_write_or(wal,
 		    GAM_ECOCHK,
 		    BDW_DISABLE_HDC_INVALIDATION);
-
-	/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
-	if (IS_GEN9_LP(dev_priv))
-		wa_write_masked_or(wal,
-				   GEN8_L3SQCREG1,
-				   L3_PRIO_CREDITS_MASK,
-				   L3_GENERAL_PRIO_CREDITS(62) |
-				   L3_HIGH_PRIO_CREDITS(2));
-
-	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
-	wa_write_or(wal,
-		    GEN8_L3SQCREG4,
-		    GEN8_LQSC_FLUSH_COHERENT_LINES);
-
-	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
-	wa_masked_en(wal,
-		     GEN7_FF_SLICE_CS_CHICKEN1,
-		     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
 }
 
 static void skl_gt_workarounds_init(struct drm_i915_private *dev_priv)

@@ -711,11 +682,6 @@ static void skl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 
 	gen9_gt_workarounds_init(dev_priv);
 
-	/* WaEnableGapsTsvCreditFix:skl */
-	wa_write_or(wal,
-		    GEN8_GARBCNTL,
-		    GEN9_GAPS_TSV_CREDIT_DISABLE);
-
 	/* WaDisableGafsUnitClkGating:skl */
 	wa_write_or(wal,
 		    GEN7_UCGCTL4,

@@ -734,11 +700,6 @@ static void bxt_gt_workarounds_init(struct drm_i915_private *dev_priv)
 
 	gen9_gt_workarounds_init(dev_priv);
 
-	/* WaDisablePooledEuLoadBalancingFix:bxt */
-	wa_masked_en(wal,
-		     FF_SLICE_CS_CHICKEN2,
-		     GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
-
 	/* WaInPlaceDecompressionHang:bxt */
 	wa_write_or(wal,
 		    GEN9_GAMT_ECO_REG_RW_IA,

@@ -751,11 +712,6 @@ static void kbl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 
 	gen9_gt_workarounds_init(dev_priv);
 
-	/* WaEnableGapsTsvCreditFix:kbl */
-	wa_write_or(wal,
-		    GEN8_GARBCNTL,
-		    GEN9_GAPS_TSV_CREDIT_DISABLE);
-
 	/* WaDisableDynamicCreditSharing:kbl */
 	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
 		wa_write_or(wal,

@@ -771,21 +727,6 @@ static void kbl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 	wa_write_or(wal,
 		    GEN9_GAMT_ECO_REG_RW_IA,
 		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-
-	/* WaKBLVECSSemaphoreWaitPoll:kbl */
-	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_E0)) {
-		struct intel_engine_cs *engine;
-		unsigned int tmp;
-
-		for_each_engine(engine, dev_priv, tmp) {
-			if (engine->id == RCS)
-				continue;
-
-			wa_write(wal,
-				 RING_SEMA_WAIT_POLL(engine->mmio_base),
-				 1);
-		}
-	}
 }
 
 static void glk_gt_workarounds_init(struct drm_i915_private *dev_priv)

@@ -799,11 +740,6 @@ static void cfl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 
 	gen9_gt_workarounds_init(dev_priv);
 
-	/* WaEnableGapsTsvCreditFix:cfl */
-	wa_write_or(wal,
-		    GEN8_GARBCNTL,
-		    GEN9_GAPS_TSV_CREDIT_DISABLE);
-
 	/* WaDisableGafsUnitClkGating:cfl */
 	wa_write_or(wal,
 		    GEN7_UCGCTL4,

@@ -894,11 +830,6 @@ static void cnl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 	wa_write_or(wal,
 		    GEN9_GAMT_ECO_REG_RW_IA,
 		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-
-	/* WaEnablePreemptionGranularityControlByUMD:cnl */
-	wa_masked_en(wal,
-		     GEN7_FF_SLICE_CS_CHICKEN1,
-		     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
 }
 
 static void icl_gt_workarounds_init(struct drm_i915_private *dev_priv)

@@ -907,53 +838,17 @@ static void icl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 
 	wa_init_mcr(dev_priv);
 
-	/* This is not an Wa. Enable for better image quality */
-	wa_masked_en(wal,
-		    _3D_CHICKEN3,
-		    _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
-
 	/* WaInPlaceDecompressionHang:icl */
 	wa_write_or(wal,
 		    GEN9_GAMT_ECO_REG_RW_IA,
 		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 
-	/* WaPipelineFlushCoherentLines:icl */
-	wa_write_or(wal,
-		    GEN8_L3SQCREG4,
-		    GEN8_LQSC_FLUSH_COHERENT_LINES);
-
-	/* Wa_1405543622:icl
-	 * Formerly known as WaGAPZPriorityScheme
-	 */
-	wa_write_or(wal,
-		    GEN8_GARBCNTL,
-		    GEN11_ARBITRATION_PRIO_ORDER_MASK);
-
-	/* Wa_1604223664:icl
-	 * Formerly known as WaL3BankAddressHashing
-	 */
-	wa_write_masked_or(wal,
-			   GEN8_GARBCNTL,
-			   GEN11_HASH_CTRL_EXCL_MASK,
-			   GEN11_HASH_CTRL_EXCL_BIT0);
-	wa_write_masked_or(wal,
-			   GEN11_GLBLINVL,
-			   GEN11_BANK_HASH_ADDR_EXCL_MASK,
-			   GEN11_BANK_HASH_ADDR_EXCL_BIT0);
-
 	/* WaModifyGamTlbPartitioning:icl */
 	wa_write_masked_or(wal,
 			   GEN11_GACB_PERF_CTRL,
 			   GEN11_HASH_CTRL_MASK,
 			   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
 
-	/* Wa_1405733216:icl
-	 * Formerly known as WaDisableCleanEvicts
-	 */
-	wa_write_or(wal,
-		    GEN8_L3SQCREG4,
-		    GEN11_LQSC_CLEAN_EVICT_DISABLE);
-
 	/* Wa_1405766107:icl
 	 * Formerly known as WaCL2SFHalfMaxAlloc
 	 */

@@ -986,13 +881,6 @@ static void icl_gt_workarounds_init(struct drm_i915_private *dev_priv)
 			    INF_UNIT_LEVEL_CLKGATE,
 			    CGPSF_CLKGATE_DIS);
 
-	/* WaForwardProgressSoftReset:icl */
-	wa_write_or(wal,
-		    GEN10_SCRATCH_LNCF2,
-		    PMFLUSHDONE_LNICRSDROP |
-		    PMFLUSH_GAPL3UNBLOCK |
-		    PMFLUSHDONE_LNEBLK);
-
 	/* Wa_1406463099:icl
 	 * Formerly known as WaGamTlbPendError
 	 */

@@ -1242,6 +1130,143 @@ void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	whitelist_apply(engine, whitelist_build(engine, &w));
 }
 
+static void rcs_engine_wa_init(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *i915 = engine->i915;
+	struct i915_wa_list *wal = &engine->wa_list;
+
+	if (IS_GEN9(i915)) {
+		/* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
+		wa_masked_en(wal,
+			     GEN9_CSFE_CHICKEN1_RCS,
+			     GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
+
+		/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
+		wa_write_or(wal,
+			    BDW_SCRATCH1,
+			    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+
+		/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
+		if (IS_GEN9_LP(i915))
+			wa_write_masked_or(wal,
+					   GEN8_L3SQCREG1,
+					   L3_PRIO_CREDITS_MASK,
+					   L3_GENERAL_PRIO_CREDITS(62) |
+					   L3_HIGH_PRIO_CREDITS(2));
+
+		/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
+		wa_write_or(wal,
+			    GEN8_L3SQCREG4,
+			    GEN8_LQSC_FLUSH_COHERENT_LINES);
+	}
+
+	if (IS_BROXTON(i915)) {
+		/* WaDisablePooledEuLoadBalancingFix:bxt */
+		wa_masked_en(wal,
+			     FF_SLICE_CS_CHICKEN2,
+			     GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+	}
+
+	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+		/* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
+		wa_write_or(wal,
+			    GEN8_GARBCNTL,
+			    GEN9_GAPS_TSV_CREDIT_DISABLE);

drivers/gpu/drm/i915/intel_workarounds.c void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine) · line 1184

Quoted 10 lines
drivers/gpu/drm/i915/intel_workarounds.c +10 -0
+	}
+
+	if (IS_GEN9(i915) || IS_CANNONLAKE(i915)) {
+		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
+		wa_masked_en(wal,
+			     GEN7_FF_SLICE_CS_CHICKEN1,
+			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
+	}
+
+	if (IS_ICELAKE(i915)) {

Could we make newer platform coming first?

anyway:

Acked-by Rodrigo Vivi <[email protected]>
Quoted 103 lines
drivers/gpu/drm/i915/intel_workarounds.c +85 -0
+		/* This is not an Wa. Enable for better image quality */
+		wa_masked_en(wal,
+			     _3D_CHICKEN3,
+			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
+
+		/* WaPipelineFlushCoherentLines:icl */
+		wa_write_or(wal,
+			    GEN8_L3SQCREG4,
+			    GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+		/*
+		 * Wa_1405543622:icl
+		 * Formerly known as WaGAPZPriorityScheme
+		 */
+		wa_write_or(wal,
+			    GEN8_GARBCNTL,
+			    GEN11_ARBITRATION_PRIO_ORDER_MASK);
+
+		/*
+		 * Wa_1604223664:icl
+		 * Formerly known as WaL3BankAddressHashing
+		 */
+		wa_write_masked_or(wal,
+				   GEN8_GARBCNTL,
+				   GEN11_HASH_CTRL_EXCL_MASK,
+				   GEN11_HASH_CTRL_EXCL_BIT0);
+		wa_write_masked_or(wal,
+				   GEN11_GLBLINVL,
+				   GEN11_BANK_HASH_ADDR_EXCL_MASK,
+				   GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+
+		/*
+		 * Wa_1405733216:icl
+		 * Formerly known as WaDisableCleanEvicts
+		 */
+		wa_write_or(wal,
+			    GEN8_L3SQCREG4,
+			    GEN11_LQSC_CLEAN_EVICT_DISABLE);
+
+		/* WaForwardProgressSoftReset:icl */
+		wa_write_or(wal,
+			    GEN10_SCRATCH_LNCF2,
+			    PMFLUSHDONE_LNICRSDROP |
+			    PMFLUSH_GAPL3UNBLOCK |
+			    PMFLUSHDONE_LNEBLK);
+	}
+}
+
+static void xcs_engine_wa_init(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *i915 = engine->i915;
+	struct i915_wa_list *wal = &engine->wa_list;
+
+	if (IS_KABYLAKE(i915)) {
+		/* WaKBLVECSSemaphoreWaitPoll:kbl */
+		if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
+			wa_write(wal,
+				 RING_SEMA_WAIT_POLL(engine->mmio_base),
+				 1);
+		}
+	}
+}
+
+void intel_engine_workarounds_init(struct intel_engine_cs *engine)
+{
+	struct i915_wa_list *wal = &engine->wa_list;
+
+	if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
+		return;
+
+	wa_init_start(wal, engine->name);
+
+	if (engine->id == RCS)
+		rcs_engine_wa_init(engine);
+	else
+		xcs_engine_wa_init(engine);
+
+	wa_init_finish(wal);
+}
+
+void intel_engine_workarounds_apply(struct intel_engine_cs *engine)
+{
+	wa_list_apply(engine->i915, &engine->wa_list);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/intel_workarounds.c"
 #endif
drivers/gpu/drm/i915/intel_workarounds.h +3 -0
index 64aed9cf0200..2998767d51ca 100644
@@ -36,4 +36,7 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
 
 void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
 
+void intel_engine_workarounds_init(struct intel_engine_cs *engine);
+void intel_engine_workarounds_apply(struct intel_engine_cs *engine);
+
 #endif
Signature · 1 line
2.19.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#7 lore raw

PATCH 3/7 drm/i915: Verify GT workaround state after GPU init

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver.

Initially we only do this after GPU initialization.

v2:
Chris Wilson:
* Simplify verification by realizing it's a simple xor and and.
* Remove verification from engine reset path.
* Return bool straight away from the verify API.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.c          |  1 +
 drivers/gpu/drm/i915/i915_gem.c          |  3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 34 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_workarounds.h |  2 ++
 4 files changed, 40 insertions(+)
drivers/gpu/drm/i915/i915_drv.c +1 -0
index 2f3dc1cf83a6..4883a20ed9ff 100644
@@ -53,6 +53,7 @@
 #include "i915_vgpu.h"
 #include "intel_drv.h"
 #include "intel_uc.h"
+#include "intel_workarounds.h"
 
 static struct drm_driver driver;
drivers/gpu/drm/i915/i915_gem.c +3 -0
index 18adb3dd1fcd..1eff471d4366 100644
@@ -5334,7 +5334,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
+	/* Apply the GT workarounds... */
 	intel_gt_workarounds_apply(dev_priv);
+	/* ...and determine whether they are sticking. */
+	intel_gt_workarounds_verify(dev_priv, "init");
 
 	i915_gem_init_swizzling(dev_priv);
drivers/gpu/drm/i915/intel_workarounds.c +34 -0
index be63a2af3481..d80ea8172222 100644
@@ -981,6 +981,40 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
 }
 
+static bool
+wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
+{
+	if ((cur ^ wa->val) & wa->mask) {
+		DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
+			  name, from, i915_mmio_reg_offset(wa->reg), cur,
+			  cur & wa->mask, wa->val, wa->mask);
+
+		return false;
+	}
+
+	return true;
+}
+
+static bool wa_list_verify(struct drm_i915_private *dev_priv,
+			   const struct i915_wa_list *wal,
+			   const char *from)
+{
+	struct i915_wa *wa;
+	unsigned int i;
+	bool ok = true;
+
+	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
+		ok &= wa_verify(wa, I915_READ(wa->reg), wal->name, from);
+
+	return ok;
+}
+
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+				 const char *from)
+{
+	return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
+}
+
 struct whitelist {
 	i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
 	unsigned int count;
drivers/gpu/drm/i915/intel_workarounds.h +2 -0
index 2998767d51ca..f2a4e8c36027 100644
@@ -33,6 +33,8 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
 
 void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+				 const char *from);
 
 void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
Signature · 6 lines
2.19.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by on v1 3/7
#8 lore raw

Re: [PATCH 3/7] drm/i915: Verify GT workaround state after GPU init

Quoting Tvrtko Ursulin (2018-11-30 17:44:08)

Quoted 39 lines

From: Tvrtko Ursulin <[email protected]>

Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver.

Initially we only do this after GPU initialization.

v2:
Chris Wilson:
* Simplify verification by realizing it's a simple xor and and.
* Remove verification from engine reset path.
* Return bool straight away from the verify API.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.c          |  1 +
 drivers/gpu/drm/i915/i915_gem.c          |  3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 34 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_workarounds.h |  2 ++
 4 files changed, 40 insertions(+)
drivers/gpu/drm/i915/i915_drv.c +1 -0
index 2f3dc1cf83a6..4883a20ed9ff 100644
@@ -53,6 +53,7 @@
 #include "i915_vgpu.h"
 #include "intel_drv.h"
 #include "intel_uc.h"
+#include "intel_workarounds.h"
 
 static struct drm_driver driver;
drivers/gpu/drm/i915/i915_gem.c +0 -0
index 18adb3dd1fcd..1eff471d4366 100644

drivers/gpu/drm/i915/i915_gem.c int i915_gem_init_hw(struct drm_i915_private *dev_priv) · line 5335

Quoted 2 lines
drivers/gpu/drm/i915/i915_gem.c +0 -0
@@ -5334,7 +5334,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
                I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
                           LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);

What's that, a few more mmio that should be part of gt_wa? :)

Reviewed-by Chris Wilson <[email protected]>

-Chris
_______________________________________________
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author
#9 lore raw

PATCH 4/7 drm/i915/selftests: Add tests for GT and engine workaround verification

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones.

(Including checks that one engine reset is not affecting workarounds not belonging to itself.)

v2:
* Rebase for series refactoring.
* Add spinner for actual engine reset!
* Add idle reset test as well. (Chris Wilson)
* Share existing global_reset_lock. (Chris Wilson)

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/intel_workarounds.c      |   6 +
 drivers/gpu/drm/i915/selftests/igt_common.c   |  44 ++++++
 drivers/gpu/drm/i915/selftests/igt_common.h   |  15 ++
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  51 ++----
 .../drm/i915/selftests/intel_workarounds.c    | 147 +++++++++++++++++-
 6 files changed, 217 insertions(+), 47 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.c
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.h
drivers/gpu/drm/i915/Makefile +1 -0
index 50a8fa8fce64..ceeb21f8aa0c 100644
@@ -166,6 +166,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
 	selftests/i915_random.o \
 	selftests/i915_selftest.o \
 	selftests/igt_flush_test.o \
+	selftests/igt_common.o \
 	selftests/igt_spinner.o
 
 # virtual gpu code
drivers/gpu/drm/i915/intel_workarounds.c +6 -0
index d80ea8172222..5a4d70e02b63 100644
@@ -1303,4 +1303,10 @@ void intel_engine_workarounds_apply(struct intel_engine_cs *engine)
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/intel_workarounds.c"
+
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+				     const char *from)
+{
+	return wa_list_verify(engine->i915, &engine->wa_list, from);
+}
 #endif
drivers/gpu/drm/i915/selftests/igt_common.c new file +44 -0

44 lines not on this page · raw message

drivers/gpu/drm/i915/selftests/igt_common.h new file +15 -0
new file mode 100644
index 000000000000..3df12ed10200
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef __I915_SELFTESTS_IGT_COMMON_H__
+#define __I915_SELFTESTS_IGT_COMMON_H__
+
+#include "../i915_drv.h"
+
+void igt_global_reset_lock(struct drm_i915_private *i915);
+void igt_global_reset_unlock(struct drm_i915_private *i915);
+
+#endif
drivers/gpu/drm/i915/selftests/intel_hangcheck.c +9 -42

111 lines not on this page · raw message

drivers/gpu/drm/i915/selftests/intel_workarounds.c +142 -5

178 lines not on this page · raw message

Signature · 6 lines
2.19.1

_______________________________________________
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[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
#10 lore raw

Re: [PATCH 4/7] drm/i915/selftests: Add tests for GT and engine workaround verification

Quoting Tvrtko Ursulin (2018-11-30 17:44:09)

Quoted 31 lines

From: Tvrtko Ursulin <[email protected]>

Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones.

(Including checks that one engine reset is not affecting workarounds not belonging to itself.)

v2:
* Rebase for series refactoring.
* Add spinner for actual engine reset!
* Add idle reset test as well. (Chris Wilson)
* Share existing global_reset_lock. (Chris Wilson)

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/intel_workarounds.c      |   6 +
 drivers/gpu/drm/i915/selftests/igt_common.c   |  44 ++++++
 drivers/gpu/drm/i915/selftests/igt_common.h   |  15 ++
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  51 ++----
 .../drm/i915/selftests/intel_workarounds.c    | 147 +++++++++++++++++-
 6 files changed, 217 insertions(+), 47 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.c
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.h
drivers/gpu/drm/i915/Makefile +0 -0
index 50a8fa8fce64..ceeb21f8aa0c 100644

drivers/gpu/drm/i915/Makefile i915-$(CONFIG_DRM_I915_SELFTEST) += \ · line 169

Quoted 4 lines
drivers/gpu/drm/i915/Makefile +1 -0
@@ -166,6 +166,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
        selftests/i915_random.o \
        selftests/i915_selftest.o \
        selftests/igt_flush_test.o \
+       selftests/igt_common.o \

I was anticipating igt_reset.c.

Quoted 32 lines
drivers/gpu/drm/i915/selftests/intel_workarounds.c +3 -3
index 80396b3592f5..194a3c30554d 100644
@@ -6,6 +6,8 @@
 
 #include "../i915_selftest.h"
 
+#include "igt_common.h"
+#include "igt_flush_test.h"
 #include "igt_spinner.h"
 #include "igt_wedge_me.h"
 #include "mock_context.h"

@@ -290,7 +292,6 @@ static int live_reset_whitelist(void *arg)
 {
        struct drm_i915_private *i915 = arg;
        struct intel_engine_cs *engine = i915->engine[RCS];
-       struct i915_gpu_error *error = &i915->gpu_error;
        struct whitelist w;
        int err = 0;
 

@@ -302,8 +303,7 @@ static int live_reset_whitelist(void *arg)
        if (!whitelist_build(engine, &w))
                return 0;
 
-       set_bit(I915_RESET_BACKOFF, &error->flags);
-       set_bit(I915_RESET_ENGINE + engine->id, &error->flags);
+       igt_global_reset_lock(i915);
 
        if (intel_has_reset_engine(i915)) {
                err = check_whitelist_across_reset(engine,

drivers/gpu/drm/i915/selftests/intel_workarounds.c static int live_reset_whitelist(void *arg) · line 325

Quoted 6 lines
drivers/gpu/drm/i915/selftests/intel_workarounds.c +1 -2
@@ -322,15 +322,152 @@ static int live_reset_whitelist(void *arg)
        }
 
 out:
-       clear_bit(I915_RESET_ENGINE + engine->id, &error->flags);
-       clear_bit(I915_RESET_BACKOFF, &error->flags);
+       igt_global_reset_unlock(i915);

Yup, makes sense.

Quoted 21 lines
drivers/gpu/drm/i915/selftests/intel_workarounds.c +18 -0
        return err;
 }
 
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+                                    const char *from);
+
+static bool verify_gt_engine_wa(struct drm_i915_private *i915, const char *str)
+{
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
+       bool ok = true;
+
+       ok &= intel_gt_workarounds_verify(i915, str);
+
+       for_each_engine(engine, i915, id)
+               ok &= intel_engine_workarounds_verify(engine, str);
+
+       return ok;
+}
+
+static int

drivers/gpu/drm/i915/selftests/intel_workarounds.c static int live_reset_whitelist(void *arg) · line 356

Quoted 10 lines
drivers/gpu/drm/i915/selftests/intel_workarounds.c +10 -0
+live_gpu_reset_gt_engine_workarounds(void *arg)
+{
+       struct drm_i915_private *i915 = arg;
+       struct i915_gpu_error *error = &i915->gpu_error;
+       bool ok;
+
+       if (!intel_has_gpu_reset(i915))
+               return 0;
+
+       pr_info("Verifying after GPU reset...\n");

Such noise! ;)

Quoted 34 lines
drivers/gpu/drm/i915/selftests/intel_workarounds.c +34 -0
+
+       igt_global_reset_lock(i915);
+
+       ok = verify_gt_engine_wa(i915, "before reset");
+       if (!ok)
+               goto out;
+
+       intel_runtime_pm_get(i915);
+       set_bit(I915_RESET_HANDOFF, &error->flags);
+       i915_reset(i915, ALL_ENGINES, "live_workarounds");
+       intel_runtime_pm_put(i915);
+
+       ok = verify_gt_engine_wa(i915, "after reset");
+
+out:
+       igt_global_reset_unlock(i915);
+
+       return ok ? 0 : -ESRCH;
+}
+
+static int
+live_engine_reset_gt_engine_workarounds(void *arg)
+{
+       struct drm_i915_private *i915 = arg;
+       struct intel_engine_cs *engine;
+       struct i915_gem_context *ctx;
+       struct igt_spinner spin;
+       enum intel_engine_id id;
+       struct i915_request *rq;
+       int ret = 0;
+
+       if (!intel_has_reset_engine(i915))
+               return 0;
+

drivers/gpu/drm/i915/selftests/intel_workarounds.c static int live_reset_whitelist(void *arg) · line 400

Quoted 10 lines
drivers/gpu/drm/i915/selftests/intel_workarounds.c +10 -0
+       ctx = kernel_context(i915);
+       if (IS_ERR(ctx))
+               return PTR_ERR(ctx);
+
+       for_each_engine(engine, i915, id) {
+               bool ok;
+
+               pr_info("Verifying after %s reset...\n", engine->name);
+
+               igt_global_reset_lock(i915);

The key thing with it being global, is that you can take it globally :) -Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reviewed-by
#11 lore raw

Re: [PATCH 4/7] drm/i915/selftests: Add tests for GT and engine workaround verification

Quoting Chris Wilson (2018-11-30 21:04:46)

Quoted 15 lines

Quoting Tvrtko Ursulin (2018-11-30 17:44:09)

Quoted 14 lines

From: Tvrtko Ursulin <[email protected]>

Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones.

(Including checks that one engine reset is not affecting workarounds not belonging to itself.)

v2:
* Rebase for series refactoring.
* Add spinner for actual engine reset!
* Add idle reset test as well. (Chris Wilson)
* Share existing global_reset_lock. (Chris Wilson)

Quoted 10 lines

drivers/gpu/drm/i915/selftests/intel_workarounds.c static int live_reset_whitelist(void *arg) · line 400

Quoted 8 lines
Signed-off-by Tvrtko Ursulin <[email protected]>

---

drivers/gpu/drm/i915/selftests/intel_workarounds.c +6 -0
+       for_each_engine(engine, i915, id) {
+               bool ok;
+
+               pr_info("Verifying after %s reset...\n", engine->name);
+
+               igt_global_reset_lock(i915);

The key thing with it being global, is that you can take it globally :)

I think that tidies up the loop innards to make it worthwhile, so with that

Reviewed-by Chris Wilson <[email protected]>

-Chris
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author
#12 lore raw

PATCH 5/7 drm/i915: Move register white-listing to the common workaround framework

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

Instead of having a separate list of white-listed registers we can trivially move this to the common workarounds framework.

This brings us one step closer to the goal of driving all workaround classes using the same code.

v2:
* Use GEM_DEBUG_WARN_ON for the sanity check. (Chris Wilson)

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/intel_engine_cs.c        |  1 +
 drivers/gpu/drm/i915/intel_lrc.c              |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h       |  1 +
 drivers/gpu/drm/i915/intel_workarounds.c      | 83 ++++++++-----------
 drivers/gpu/drm/i915/intel_workarounds.h      |  1 +
 .../drm/i915/selftests/intel_workarounds.c    | 40 ++++-----
 6 files changed, 57 insertions(+), 70 deletions(-)
drivers/gpu/drm/i915/intel_engine_cs.c +1 -0
index ef5d202e9d45..496462d77ebc 100644
@@ -725,6 +725,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 	i915_timeline_fini(&engine->timeline);
 
 	intel_wa_list_free(&engine->wa_list);
+	intel_wa_list_free(&engine->whitelist);
 }
 
 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
drivers/gpu/drm/i915/intel_lrc.c +1 -0
index dfafc3f710d6..4eead104cd9c 100644
@@ -2316,6 +2316,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
 			  ret);
 	}
 
+	intel_whitelist_workarounds_init(engine);
 	intel_engine_workarounds_init(engine);
 
 	return 0;
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -0
index c5ff3d31cab7..91a750e90dc4 100644
@@ -453,6 +453,7 @@ struct intel_engine_cs {
 	struct intel_hw_status_page status_page;
 	struct i915_ctx_workarounds wa_ctx;
 	struct i915_wa_list wa_list;
+	struct i915_wa_list whitelist;
 	struct i915_vma *scratch;
 
 	u32             irq_keep_mask; /* always keep these interrupts */
drivers/gpu/drm/i915/intel_workarounds.c +33 -50

165 lines not on this page · raw message

drivers/gpu/drm/i915/intel_workarounds.h +1 -0
index f2a4e8c36027..e6da31f0ceb6 100644
@@ -36,6 +36,7 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
 bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
 				 const char *from);
 
+void intel_whitelist_workarounds_init(struct intel_engine_cs *engine);
 void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
 
 void intel_engine_workarounds_init(struct intel_engine_cs *engine);
drivers/gpu/drm/i915/selftests/intel_workarounds.c +20 -20
index 194a3c30554d..ab69cbb8869e 100644
@@ -94,17 +94,23 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
 	return ERR_PTR(err);
 }
 
-static u32 get_whitelist_reg(const struct whitelist *w, unsigned int i)
+static u32
+get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
 {
-	return i < w->count ? i915_mmio_reg_offset(w->reg[i]) : w->nopid;
+	i915_reg_t reg = i < engine->whitelist.count ?
+			 engine->whitelist.list[i].reg :
+			 RING_NOPID(engine->mmio_base);
+
+	return i915_mmio_reg_offset(reg);
 }
 
-static void print_results(const struct whitelist *w, const u32 *results)
+static void
+print_results(const struct intel_engine_cs *engine, const u32 *results)
 {
 	unsigned int i;
 
 	for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
-		u32 expected = get_whitelist_reg(w, i);
+		u32 expected = get_whitelist_reg(engine, i);
 		u32 actual = results[i];
 
 		pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",

@@ -112,8 +118,7 @@ static void print_results(const struct whitelist *w, const u32 *results)
 	}
 }
 
-static int check_whitelist(const struct whitelist *w,
-			   struct i915_gem_context *ctx,
+static int check_whitelist(struct i915_gem_context *ctx,
 			   struct intel_engine_cs *engine)
 {
 	struct drm_i915_gem_object *results;

@@ -141,11 +146,11 @@ static int check_whitelist(const struct whitelist *w,
 	}
 
 	for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
-		u32 expected = get_whitelist_reg(w, i);
+		u32 expected = get_whitelist_reg(engine, i);
 		u32 actual = vaddr[i];
 
 		if (expected != actual) {
-			print_results(w, vaddr);
+			print_results(engine, vaddr);
 			pr_err("Invalid RING_NONPRIV[%d], expected 0x%08x, found 0x%08x\n",
 			       i, expected, actual);
 

@@ -217,7 +222,6 @@ switch_to_scratch_context(struct intel_engine_cs *engine,
 
 static int check_whitelist_across_reset(struct intel_engine_cs *engine,
 					int (*reset)(struct intel_engine_cs *),
-					const struct whitelist *w,
 					const char *name)
 {
 	struct drm_i915_private *i915 = engine->i915;

@@ -227,7 +231,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
 	int err;
 
 	pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
-		w->count, name);
+		engine->whitelist.count, name);
 
 	if (want_spin) {
 		err = igt_spinner_init(&spin, i915);

@@ -239,7 +243,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
 	if (IS_ERR(ctx))
 		return PTR_ERR(ctx);
 
-	err = check_whitelist(w, ctx, engine);
+	err = check_whitelist(ctx, engine);
 	if (err) {
 		pr_err("Invalid whitelist *before* %s reset!\n", name);
 		goto out;

@@ -263,7 +267,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
 		goto out;
 	}
 
-	err = check_whitelist(w, ctx, engine);
+	err = check_whitelist(ctx, engine);
 	if (err) {
 		pr_err("Whitelist not preserved in context across %s reset!\n",
 		       name);

@@ -276,7 +280,7 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
 	if (IS_ERR(ctx))
 		return PTR_ERR(ctx);
 
-	err = check_whitelist(w, ctx, engine);
+	err = check_whitelist(ctx, engine);
 	if (err) {
 		pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
 		       name);

@@ -292,22 +296,18 @@ static int live_reset_whitelist(void *arg)
 {
 	struct drm_i915_private *i915 = arg;
 	struct intel_engine_cs *engine = i915->engine[RCS];
-	struct whitelist w;
 	int err = 0;
 
 	/* If we reset the gpu, we should not lose the RING_NONPRIV */
 
-	if (!engine)
-		return 0;
-
-	if (!whitelist_build(engine, &w))
+	if (!engine || engine->whitelist.count == 0)
 		return 0;
 
 	igt_global_reset_lock(i915);
 
 	if (intel_has_reset_engine(i915)) {
 		err = check_whitelist_across_reset(engine,
-						   do_engine_reset, &w,
+						   do_engine_reset,
 						   "engine");
 		if (err)
 			goto out;

@@ -315,7 +315,7 @@ static int live_reset_whitelist(void *arg)
 
 	if (intel_has_gpu_reset(i915)) {
 		err = check_whitelist_across_reset(engine,
-						   do_device_reset, &w,
+						   do_device_reset,
 						   "device");
 		if (err)
 			goto out;
Signature · 6 lines
2.19.1

_______________________________________________
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#13 lore raw

Re: [PATCH 5/7] drm/i915: Move register white-listing to the common workaround framework

Quoting Tvrtko Ursulin (2018-11-30 17:44:10)

drivers/gpu/drm/i915/intel_lrc.c int logical_render_ring_init(struct intel_engine_cs *engine) · line 2320

Quoted 11 lines

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)

drivers/gpu/drm/i915/intel_lrc.c +1 -0
index dfafc3f710d6..4eead104cd9c 100644
@@ -2316,6 +2316,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
                          ret);
        }
 
+       intel_whitelist_workarounds_init(engine);
        intel_engine_workarounds_init(engine);

So to play devil's advocate:

intel_engine_init_whitelist(engine);
intel_engine_init_workarounds(engine);

object_verb_subject
object = intel_engine
verb = init
subject / subcluase.

I guess there's one more to see how it fits into the pattern... -Chris
_______________________________________________
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Reviewed-by
#14 lore raw

Re: [PATCH 5/7] drm/i915: Move register white-listing to the common workaround framework

Quoting Chris Wilson (2018-11-30 21:08:08)

Quoted 18 lines

Quoting Tvrtko Ursulin (2018-11-30 17:44:10)

drivers/gpu/drm/i915/intel_lrc.c int logical_render_ring_init(struct intel_engine_cs *engine) · line 2320

Quoted 11 lines

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)

drivers/gpu/drm/i915/intel_lrc.c +1 -0
index dfafc3f710d6..4eead104cd9c 100644
@@ -2316,6 +2316,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
                          ret);
        }
 
+       intel_whitelist_workarounds_init(engine);
        intel_engine_workarounds_init(engine);

So to play devil's advocate:

intel_engine_init_whitelist(engine);
intel_engine_init_workarounds(engine);

Quoted 6 lines

object_verb_subject
object = intel_engine
verb = init
subject / subcluase.

I guess there's one more to see how it fits into the pattern...

The guts are fine though,

Reviewed-by Chris Wilson <[email protected]>

-Chris
_______________________________________________
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author
#15 lore raw

PATCH 6/7 drm/i915: Fuse per-context workaround handling with the common framework

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

Convert the per context workaround handling code to run against the newly introduced common workaround framework and fuse the two to use the existing smarter list add helper, the one which does the sorted insert and merges registers where possible.

This completes migration of all four classes of workarounds onto the common framework.

Existing macros are kept untouched for smaller code churn.

v2:
* Rename to list name ctx_wa_list and move from dev_priv to engine.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/i915_debugfs.c      |  12 +-
 drivers/gpu/drm/i915/i915_drv.h          |  15 --
 drivers/gpu/drm/i915/i915_gem_context.c  |   6 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   |   1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 267 ++++++++++-------------
 drivers/gpu/drm/i915/intel_workarounds.h |   3 +-
 7 files changed, 129 insertions(+), 176 deletions(-)
drivers/gpu/drm/i915/i915_debugfs.c +7 -5
index 129b9a6f8309..38dcee1ca062 100644
@@ -3375,13 +3375,15 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 
 static int i915_wa_registers(struct seq_file *m, void *unused)
 {
-	struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
-	int i;
+	struct drm_i915_private *i915 = node_to_i915(m->private);
+	const struct i915_wa_list *wal = &i915->engine[RCS]->ctx_wa_list;
+	struct i915_wa *wa;
+	unsigned int i;
 
-	seq_printf(m, "Workarounds applied: %d\n", wa->count);
-	for (i = 0; i < wa->count; ++i)
+	seq_printf(m, "Workarounds applied: %u\n", wal->count);
+	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
 		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
-			   wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
+			   i915_mmio_reg_offset(wa->reg), wa->val, wa->mask);
 
 	return 0;
 }
drivers/gpu/drm/i915/i915_drv.h +0 -15
index 9ddbcc1f3554..443e08f4736a 100644
@@ -1189,20 +1189,6 @@ struct i915_frontbuffer_tracking {
 	unsigned flip_bits;
 };
 
-struct i915_wa_reg {
-	u32 addr;
-	u32 value;
-	/* bitmask representing WA bits */
-	u32 mask;
-};
-
-#define I915_MAX_WA_REGS 16
-
-struct i915_workarounds {
-	struct i915_wa_reg reg[I915_MAX_WA_REGS];
-	u32 count;
-};
-
 struct i915_virtual_gpu {
 	bool active;
 	u32 caps;

@@ -1652,7 +1638,6 @@ struct drm_i915_private {
 
 	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
-	struct i915_workarounds workarounds;
 	struct i915_wa_list gt_wa_list;
 
 	struct i915_frontbuffer_tracking fb_tracking;
drivers/gpu/drm/i915/i915_gem_context.c +1 -5
index b97963db0287..aae7e13c7420 100644
@@ -535,16 +535,12 @@ static bool needs_preempt_context(struct drm_i915_private *i915)
 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_gem_context *ctx;
-	int ret;
 
 	/* Reassure ourselves we are only called once */
 	GEM_BUG_ON(dev_priv->kernel_context);
 	GEM_BUG_ON(dev_priv->preempt_context);
 
-	ret = intel_ctx_workarounds_init(dev_priv);
-	if (ret)
-		return ret;
-
+	intel_ctx_workarounds_init(dev_priv);
 	init_contexts(dev_priv);
 
 	/* lowest priority; idle task */
drivers/gpu/drm/i915/intel_engine_cs.c +1 -0
index 496462d77ebc..6b427bc52f78 100644
@@ -724,6 +724,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 
 	i915_timeline_fini(&engine->timeline);
 
+	intel_wa_list_free(&engine->ctx_wa_list);
 	intel_wa_list_free(&engine->wa_list);
 	intel_wa_list_free(&engine->whitelist);
 }
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -0
index 91a750e90dc4..8f985c35ec92 100644
@@ -452,6 +452,7 @@ struct intel_engine_cs {
 
 	struct intel_hw_status_page status_page;
 	struct i915_ctx_workarounds wa_ctx;
+	struct i915_wa_list ctx_wa_list;
 	struct i915_wa_list wa_list;
 	struct i915_wa_list whitelist;
 	struct i915_vma *scratch;
drivers/gpu/drm/i915/intel_workarounds.c +117 -150

471 lines not on this page · raw message

drivers/gpu/drm/i915/intel_workarounds.h +2 -1
index e6da31f0ceb6..2129d6e9fcc9 100644
@@ -18,6 +18,7 @@ struct i915_wa {
 struct i915_wa_list {
 	const char	*name;
 	unsigned int 	count;
+	unsigned int	wa_count;
 	struct i915_wa	*list;
 	unsigned int	__size;
 };

@@ -28,7 +29,7 @@ static inline void intel_wa_list_free(struct i915_wa_list *wal)
 	memset(wal, 0, sizeof(*wal));
 }
 
-int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv);
+void intel_ctx_workarounds_init(struct drm_i915_private *dev_priv);
 int intel_ctx_workarounds_emit(struct i915_request *rq);
 
 void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
Signature · 6 lines
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#16 lore raw

Re: [PATCH 6/7] drm/i915: Fuse per-context workaround handling with the common framework

Quoting Tvrtko Ursulin (2018-11-30 17:44:11)

drivers/gpu/drm/i915/intel_ringbuffer.h struct intel_engine_cs { · line 457

Quoted 11 lines
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -0
index 91a750e90dc4..8f985c35ec92 100644
@@ -452,6 +452,7 @@ struct intel_engine_cs {
 
        struct intel_hw_status_page status_page;
        struct i915_ctx_workarounds wa_ctx;
+       struct i915_wa_list ctx_wa_list;
        struct i915_wa_list wa_list;
        struct i915_wa_list whitelist;

Hmm. I think I would suggest we use

ctx_wa_list
mmio_wa_list ???
whitelist

drivers/gpu/drm/i915/intel_ringbuffer.h

Quoted 5 lines
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -1
-int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+void intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)

{

drivers/gpu/drm/i915/intel_ringbuffer.h +1 -1
-       int err = 0;
+       struct i915_wa_list *wal = &dev_priv->engine[RCS]->ctx_wa_list;

And here,

intel_engine_init_ctx_wa(intel_engine_cs *engine)

or something to match the other engine wa_list.
-Chris
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author
#17 lore raw

Re: [PATCH 6/7] drm/i915: Fuse per-context workaround handling with the common framework

Quoted 15 lines · Chris Wilson

Quoting Tvrtko Ursulin (2018-11-30 17:44:11)

drivers/gpu/drm/i915/intel_ringbuffer.h struct intel_engine_cs { · line 457

Quoted 11 lines
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -0
index 91a750e90dc4..8f985c35ec92 100644
@@ -452,6 +452,7 @@ struct intel_engine_cs {
 
         struct intel_hw_status_page status_page;
         struct i915_ctx_workarounds wa_ctx;
+       struct i915_wa_list ctx_wa_list;
         struct i915_wa_list wa_list;
         struct i915_wa_list whitelist;

Hmm. I think I would suggest we use

Quoted 3 lines

ctx_wa_list
mmio_wa_list ???
whitelist

It is implied workarounds are about mmio one way or the other via struct i915_wa itself so not sure.

Quoted 11 lines

drivers/gpu/drm/i915/intel_ringbuffer.h

Quoted 5 lines
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -1
-int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+void intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)

  {
drivers/gpu/drm/i915/intel_ringbuffer.h +1 -1
-       int err = 0;
+       struct i915_wa_list *wal = &dev_priv->engine[RCS]->ctx_wa_list;

And here,

intel_engine_init_ctx_wa(intel_engine_cs *engine)

or something to match the other engine wa_list.

I don't have any better ideas so shout quickly or else I am changing it to intel_engine_init_ctx_wa.

Regards,

Tvrtko
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author
#18 lore raw

PATCH 7/7 drm/i915: Trim unused workaround list entries

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab.

v2:
* Simplify with kmemdup. (Chris Wilson)

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
drivers/gpu/drm/i915/intel_workarounds.c +13 -0
index 3e6b388ea022..9d876d554e57 100644
@@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const char *name)
 
 static void wa_init_finish(struct i915_wa_list *wal)
 {
+	/* Trim unused entries. */
+	if (wal->count < wal->__size) {
+		struct i915_wa *list = kmemdup(wal->list,
+					       wal->count * sizeof(*list),
+					       GFP_KERNEL);
+
+		if (list) {
+			kfree(wal->list);
+			wal->list = list;
+			wal->__size = wal->count;
+		}
+	}
+
 	if (wal->count)
 		DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
 				 wal->wa_count, wal->name);
Signature · 6 lines
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Reviewed-by on v1 7/7
#19 lore raw

Re: [PATCH 7/7] drm/i915: Trim unused workaround list entries

Quoting Tvrtko Ursulin (2018-11-30 17:44:12)

Quoted 22 lines

From: Tvrtko Ursulin <[email protected]>

The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab.

v2:
* Simplify with kmemdup. (Chris Wilson)

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
drivers/gpu/drm/i915/intel_workarounds.c +0 -0
index 3e6b388ea022..9d876d554e57 100644
@@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const char *name)
 
 static void wa_init_finish(struct i915_wa_list *wal)
 {

drivers/gpu/drm/i915/intel_workarounds.c static void wa_init_start(struct i915_wa_list *wal, const char *name) · line 67

Quoted 10 lines
drivers/gpu/drm/i915/intel_workarounds.c +10 -0
+       /* Trim unused entries. */
+       if (wal->count < wal->__size) {
+               struct i915_wa *list = kmemdup(wal->list,
+                                              wal->count * sizeof(*list),
+                                              GFP_KERNEL);
+
+               if (list) {
+                       kfree(wal->list);
+                       wal->list = list;
+                       wal->__size = wal->count;

Hmm. We could kill __size entirely if you reallocated on is_power_of_two(wal->count).

Reviewed-by Chris Wilson <[email protected]>

-Chris
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author
#20 lore raw

Re: [PATCH 7/7] drm/i915: Trim unused workaround list entries

Quoted 21 lines · Chris Wilson

Quoting Tvrtko Ursulin (2018-11-30 17:44:12)

Quoted 20 lines

From: Tvrtko Ursulin <[email protected]>

The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab.

v2:
* Simplify with kmemdup. (Chris Wilson)

Signed-off-by Tvrtko Ursulin <[email protected]>
---
  drivers/gpu/drm/i915/intel_workarounds.c | 13 +++++++++++++
  1 file changed, 13 insertions(+)
drivers/gpu/drm/i915/intel_workarounds.c +0 -0
index 3e6b388ea022..9d876d554e57 100644
@@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const char *name)
Quoted 15 lines

drivers/gpu/drm/i915/intel_workarounds.c static void wa_init_start(struct i915_wa_list *wal, const char *name) · line 67

Quoted 12 lines
drivers/gpu/drm/i915/intel_workarounds.c +10 -0
  static void wa_init_finish(struct i915_wa_list *wal)
  {
+       /* Trim unused entries. */
+       if (wal->count < wal->__size) {
+               struct i915_wa *list = kmemdup(wal->list,
+                                              wal->count * sizeof(*list),
+                                              GFP_KERNEL);
+
+               if (list) {
+                       kfree(wal->list);
+                       wal->list = list;
+                       wal->__size = wal->count;

Hmm. We could kill __size entirely if you reallocated on is_power_of_two(wal->count).

You mean allocate to next power of two is is_power_of_two(wal->count) ? In that case I could also allocate to next ALIGN(wal->count, CHUNK_SIZE) if IS_ALIGNED which looks more appropriate for this particular use case.

Can't decide whether it is worth it though. Why not..

Regards,

Tvrtko

Quoted 3 lines
Reviewed-by Chris Wilson <[email protected]>

-Chris

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CI
#21 lore raw

✗ Fi.CI.CHECKPATCH: warning for Restore workarounds after engine reset and unify their handling (rev2)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1125245b3d4b drm/i915: Record GT workarounds in a list
-:460: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#460: FILE: drivers/gpu/drm/i915/intel_workarounds.c:912:
+	wa_masked_en(wal,
+		    _3D_CHICKEN3,

-:722: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #722: FILE: drivers/gpu/drm/i915/intel_workarounds.h:20:
+^Iunsigned int ^Icount;$

total: 0 errors, 1 warnings, 1 checks, 685 lines checked
42b374d1ba00 drm/i915: Introduce per-engine workarounds
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds")' #10:
59b449d5c82a ("drm/i915: Split out functions for different kinds of

total: 1 errors, 0 warnings, 0 checks, 371 lines checked
e9a04e2832a9 drm/i915: Verify GT workaround state after GPU init
6549917a0bd0 drm/i915/selftests: Add tests for GT and engine workaround verification -:49: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #49:
new file mode 100644

-:54: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #54: FILE: drivers/gpu/drm/i915/selftests/igt_common.c:1:
+/*

-:104: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #104: FILE: drivers/gpu/drm/i915/selftests/igt_common.h:1:
+/*

total: 0 errors, 3 warnings, 0 checks, 365 lines checked
a3beaa49924a drm/i915: Move register white-listing to the common workaround framework f4ea75c6a6cd drm/i915: Fuse per-context workaround handling with the common framework b7af01a81fb8 drm/i915: Trim unused workaround list entries

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CI
#22 lore raw

✗ Fi.CI.SPARSE: warning for Restore workarounds after engine reset and unify their handling (rev2)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)
+./include/linux/slab.h:665:13: error: undefined identifier '__builtin_mul_overflow'
+./include/linux/slab.h:665:13: warning: call with no type!

Commit: drm/i915: Introduce per-engine workarounds Okay!

Commit: drm/i915: Verify GT workaround state after GPU init Okay!

Commit: drm/i915/selftests: Add tests for GT and engine workaround verification +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915: Move register white-listing to the common workaround framework Okay!

Commit: drm/i915: Fuse per-context workaround handling with the common framework -drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3557:16: warning: expression using sizeof(void)

Commit: drm/i915: Trim unused workaround list entries Okay!

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CI
#23 lore raw

✓ Fi.CI.BAT: success for Restore workarounds after engine reset and unify their handling (rev2)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5235 -> Patchwork_10981
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/53313/revisions/2/mbox/

Known issues
------------

Here are the changes found in Patchwork_10981 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614]

* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#107362]

#### Possible fixes ####

* igt@gem_ctx_create@basic-files:
- fi-bsw-kefka: FAIL [fdo#108656] -> PASS

* igt@gem_exec_suspend@basic-s3:
- fi-byt-clapper: INCOMPLETE [fdo#102657] -> PASS

* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] -> PASS

* igt@i915_selftest@live_hangcheck:
- fi-kbl-7560u: INCOMPLETE [fdo#108044] -> PASS

[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656

Participating hosts (50 -> 44)
------------------------------

Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600

Build changes
-------------

* Linux: CI_DRM_5235 -> Patchwork_10981

CI_DRM_5235: 5e327aec3fa3fc277b40818e06785743cf16b1ad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10981: b7af01a81fb8c4c250ba60f24eb7b0272bcf7d3f @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

b7af01a81fb8 drm/i915: Trim unused workaround list entries
f4ea75c6a6cd drm/i915: Fuse per-context workaround handling with the common framework a3beaa49924a drm/i915: Move register white-listing to the common workaround framework 6549917a0bd0 drm/i915/selftests: Add tests for GT and engine workaround verification e9a04e2832a9 drm/i915: Verify GT workaround state after GPU init 42b374d1ba00 drm/i915: Introduce per-engine workarounds
1125245b3d4b drm/i915: Record GT workarounds in a list

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10981/
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CI
#24 lore raw

✗ Fi.CI.IGT: failure for Restore workarounds after engine reset and unify their handling (rev2)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5235_full -> Patchwork_10981_full
====================================================

Summary
-------

**FAILURE**

Serious unknown changes coming with Patchwork_10981_full absolutely need to be verified manually.

If you think the reported changes have nothing to do with the changes introduced in Patchwork_10981_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_10981_full:

### IGT changes ###

#### Possible regressions ####

* igt@i915_selftest@live_workarounds:
- {shard-iclb}: PASS -> DMESG-FAIL

* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled:
- shard-skl: PASS -> FAIL

#### Warnings ####

* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP

Known issues
------------

Here are the changes found in Patchwork_10981_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_reuse@contexts:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]

* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: PASS -> TIMEOUT [fdo#108039]

* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956]

* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]

* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- {shard-iclb}: NOTRUN -> FAIL [fdo#107725]

* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: PASS -> FAIL [fdo#104671]

* igt@kms_cursor_crc@cursor-256x256-offscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]

* igt@kms_cursor_crc@cursor-256x85-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]

* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1

* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- {shard-iclb}: PASS -> WARN [fdo#108336] +6

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167]

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1

* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167]

* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103167] / [fdo#105682]

* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +6

* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-skl: NOTRUN -> FAIL [fdo#105682] +1

* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- shard-skl: PASS -> FAIL [fdo#105682] +1

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1

* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-skl: PASS -> FAIL [fdo#103167] +1

* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]

* igt@kms_plane@plane-position-covered-pipe-b-planes:
- {shard-iclb}: PASS -> FAIL [fdo#103166]

* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3

* igt@kms_plane_lowres@pipe-c-tiling-y:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +21

* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166] +1

* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +1

* igt@kms_plane_scaling@pipe-b-plane-scaling:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +36

* igt@kms_rotation_crc@primary-rotation-180:
- shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815]

* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]

* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]

* igt@perf@short-reads:
- shard-skl: PASS -> FAIL [fdo#103183]

* igt@pm_rpm@pm-caching:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]

* igt@pm_rpm@system-suspend-modeset:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] / [fdo#107807]

* igt@pm_rps@waitboost:
- {shard-iclb}: NOTRUN -> FAIL [fdo#102250] / [fdo#108059]

#### Possible fixes ####

* igt@gem_userptr_blits@readonly-unsync:
- shard-kbl: TIMEOUT -> PASS

* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS

* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS

* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS

* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-kbl: FAIL [fdo#100368] -> PASS

* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-iclb}: DMESG-FAIL [fdo#107724] -> PASS +6

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: FAIL [fdo#103167] -> PASS +2

* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- {shard-iclb}: DMESG-FAIL [fdo#103166] / [fdo#107724] -> PASS

* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +1

* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS

* igt@kms_rmfb@rmfb-ioctl:
- {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS +9

* igt@pm_rpm@cursor:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS +1

* igt@pm_rpm@gem-execbuf-stress-pc8:
- {shard-iclb}: INCOMPLETE [fdo#107713] / [fdo#108840] -> SKIP

#### Warnings ####

* igt@kms_ccs@pipe-b-crc-primary-rotation-180:
- {shard-iclb}: FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]

* igt@kms_cursor_crc@cursor-128x128-sliding:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103232]

* igt@kms_cursor_crc@cursor-64x21-random:
- {shard-iclb}: FAIL [fdo#103232] -> DMESG-WARN [fdo#107724] / [fdo#108336] +1

* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: FAIL [fdo#103167] -> DMESG-FAIL [fdo#107724]

* igt@kms_plane@pixel-format-pipe-c-planes:
- {shard-iclb}: FAIL [fdo#103166] -> DMESG-WARN [fdo#107724] / [fdo#108336]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103925]: https://bugs.freedesktop.org/show_bug.cgi?id=103925
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912

Participating hosts (7 -> 7)
------------------------------

No changes in participating hosts

Build changes
-------------

* Linux: CI_DRM_5235 -> Patchwork_10981

CI_DRM_5235: 5e327aec3fa3fc277b40818e06785743cf16b1ad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10981: b7af01a81fb8c4c250ba60f24eb7b0272bcf7d3f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10981/
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