dmaengine: dw: Fix FIFO size for Intel Merrifield

PATCH New Andy Shevchenko 1 participant 1 message Nov 30, 2018

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Stable branch dmaengine Synopsys DesignWare DMAC driver

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Andy Shevchenko

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2018-11-30 20:36 UTC #0 lore raw

PATCH 1/5 dmaengine: dw: Fix FIFO size for Intel Merrifield

Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller, i.e. 512 bytes instead of 1024.

Fix this by partitioning it as 64 bytes per channel.

Note, in the future we might switch to 'fifo-size' property instead of hard coded value.

Fixes 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")

Signed-off-by Andy Shevchenko <[email protected]>

Cc [email protected]

---
 drivers/dma/dw/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/dma/dw/core.c +2 -2

index d0c3e50b39fb..e85b078fc207 100644
@@ -1059,12 +1059,12 @@ static void dwc_issue_pending(struct dma_chan *chan)
 /*
  * Program FIFO size of channels.
  *
- * By default full FIFO (1024 bytes) is assigned to channel 0. Here we
+ * By default full FIFO (512 bytes) is assigned to channel 0. Here we
  * slice FIFO on equal parts between channels.
  */
 static void idma32_fifo_partition(struct dw_dma *dw)
 {
-	u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
+	u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
 		    IDMA32C_FP_UPDATE;
 	u64 fifo_partition = 0;