dmaengine: dw: Split DW and iDMA 32-bit operations
Subsystems (2)
Andy Shevchenko
reviewerPATCH 3/5 dmaengine: dw: Split DW and iDMA 32-bit operations
Here is a kinda big refactoring that should have been done in the first place, when Intel iDMA 32-bit support appeared.
It splits operations which are different to Synopsys DesignWare and Intel iDMA 32-bit controllers.
No functional change intended.
Signed-off-by Andy Shevchenko <[email protected]>
--- drivers/dma/dw/Makefile | 2 +- drivers/dma/dw/core.c | 188 +++++---------------------- drivers/dma/dw/dw.c | 109 ++++++++++++++++ drivers/dma/dw/idma32.c | 137 +++++++++++++++++++ drivers/dma/dw/internal.h | 10 +- drivers/dma/dw/pci.c | 45 ++++--- drivers/dma/dw/platform.c | 8 +- drivers/dma/dw/regs.h | 13 ++ include/linux/dma/dw.h | 4 + include/linux/platform_data/dma-dw.h | 2 - 10 files changed, 339 insertions(+), 179 deletions(-) create mode 100644 drivers/dma/dw/dw.c create mode 100644 drivers/dma/dw/idma32.c
drivers/dma/dw/Makefile +1 -1
@@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DW_DMAC_CORE) += dw_dmac_core.o -dw_dmac_core-objs := core.o +dw_dmac_core-objs := core.o dw.o idma32.o obj-$(CONFIG_DW_DMAC) += dw_dmac.o dw_dmac-objs := platform.o
drivers/dma/dw/core.c +34 -154
348 lines not on this page · raw message
drivers/dma/dw/dw.c new file +109 -0
109 lines not on this page · raw message
drivers/dma/dw/idma32.c new file +137 -0
137 lines not on this page · raw message
drivers/dma/dw/internal.h +8 -2
@@ -15,8 +15,14 @@#include "regs.h" -int dw_dma_disable (struct dw_dma_chip *chip); -int dw_dma_enable (struct dw_dma_chip *chip); +int do_dma_probe (struct dw_dma_chip *chip); +int do_dma_remove (struct dw_dma_chip *chip); + +void do_dma_on (struct dw_dma *dw); +void do_dma_off (struct dw_dma *dw); + +int do_dw_dma_disable (struct dw_dma_chip *chip); +int do_dw_dma_enable (struct dw_dma_chip *chip);extern bool dw_dma_filter (struct dma_chan *chan,void *param);
drivers/dma/dw/pci.c +29 -16
96 lines not on this page · raw message
drivers/dma/dw/platform.c +4 -4
@@ -258,7 +258,7 @@ static void dw_shutdown(struct platform_device *pdev)struct dw_dma_chip *chip =platform_get_drvdata (pdev);/* -* We have to call dw_dma_disable() to stop any ongoing transfer. On +* We have to call do_dw_dma_disable() to stop any ongoing transfer. On * some platforms we can't do that since DMA device is powered off. * Moreover we have no possibility to check if the platform is affected * or not. That's why we call pm_runtime_get_sync() / pm_runtime_put()
@@ -267,7 +267,7 @@ static void dw_shutdown(struct platform_device *pdev)* used by the driver. */ pm_runtime_get_sync (chip->dev); -dw_dma_disable (chip); +do_dw_dma_disable (chip);pm_runtime_put_sync_suspend (chip->dev);clk_disable_unprepare (chip->clk);
@@ -297,7 +297,7 @@ static int dw_suspend_late(struct device *dev) {struct dw_dma_chip *chip =dev_get_drvdata (dev); -dw_dma_disable (chip); +do_dw_dma_disable (chip);clk_disable_unprepare (chip->clk);return 0 ;
@@ -312,7 +312,7 @@ static int dw_resume_early(struct device *dev)if (ret)return ret; - return dw_dma_enable(chip); + return do_dw_dma_enable(chip); }#endif /* CONFIG_PM_SLEEP */
drivers/dma/dw/regs.h +13 -0
@@ -308,6 +308,19 @@ struct dw_dma {u8 all_chan_mask;u8 in_use; +/* Channel operations */ +void (*initialize_chan)(struct dw_dma_chan *dwc); +void (*suspend_chan)(struct dw_dma_chan *dwc,bool drain); +void (*encode_maxburst)(struct dw_dma_chan *dwc,u32 *maxburst); +u32 (*bytes2block)(struct dw_dma_chan *dwc,size_t bytes, +unsigned int width,size_t *len); +size_t (*block2bytes)(struct dw_dma_chan *dwc,u32 block,u32 width); + +/* Device operations */ +void (*set_device_name)(struct dw_dma *dw,int id); +void (*disable)(struct dw_dma *dw); +void (*enable)(struct dw_dma *dw); +/* platform data */ struct dw_dma_platform_data *pdata; };
include/linux/dma/dw.h +4 -0
@@ -45,9 +45,13 @@ struct dw_dma_chip {#if IS_ENABLED (CONFIG_DW_DMAC_CORE )int dw_dma_probe (struct dw_dma_chip *chip);int dw_dma_remove (struct dw_dma_chip *chip); +int idma32_dma_probe (struct dw_dma_chip *chip); +int idma32_dma_remove (struct dw_dma_chip *chip);#else static inline int dw_dma_probe (struct dw_dma_chip *chip) {return -ENODEV ; }static inline int dw_dma_remove (struct dw_dma_chip *chip) {return 0 ; } +static inline int idma32_dma_probe (struct dw_dma_chip *chip) {return -ENODEV ; } +static inline int idma32_dma_remove (struct dw_dma_chip *chip) {return 0 ; }#endif /* CONFIG_DW_DMAC_CORE */ #endif /* _DMA_DW_H */
include/linux/platform_data/dma-dw.h +0 -2
@@ -41,7 +41,6 @@ struct dw_dma_slave {* @is_private: The device channels should be marked as private and not for * by the general purpose DMA channel allocator. * @is_memcpy: The device channels do support memory-to-memory transfers. -* @is_idma32: The type of the DMA controller is iDMA32 * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller
@@ -54,7 +53,6 @@ struct dw_dma_platform_data {unsigned int nr_channels;bool is_private;bool is_memcpy; -bool is_idma32;#define CHAN_ALLOCATION_ASCENDING 0/* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1/* seven to zero */ unsigned char chan_allocation_order;