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SPI-NOR add NPCM FIU controller driver

PATCH In review Tomer Maimon 4 participants 11 messages Dec 3, 2018 – Dec 21, 2018

Subsystems (4)
Device tree bindings Memory technology devices (MTD) SPI NOR Arm/nuvoton npcm architecture
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Tomer Maimon

author maintainer
#0 lore raw

cover SPI-NOR add NPCM FIU controller driver

This patch set adds Flash Interface Unit(FIU) SPI-NOR support for the Nuvoton NPCM Baseboard Management Controller (BMC).

The FIU supports single, dual or quad communication interface.

the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by using an indirect address/data mechanism.
- direct rd/wr mode: maps the flash memory into the core address space.
- SPI-X mode: used for an expansion bus to an ASIC or CPLD.

The NPCM750/730/715/710 supports up to three FIU devices:
- FIU0 supports two chip select.
- FIU3 supports four chip select.
- FIUX supports two chip select.

The NPCM FIU driver tested on NPCM750 evaluation board.

Tomer Maimon (2):
dt-binding: mtd: add NPCM FIU controller
mtd: spi-nor: add NPCM FIU controller driver

 Documentation/devicetree/bindings/mtd/npcm-fiu.txt |  64 ++
 drivers/mtd/spi-nor/Kconfig                        |   8 +
 drivers/mtd/spi-nor/Makefile                       |   1 +
 drivers/mtd/spi-nor/npcm-fiu.c                     | 930 +++++++++++++++++++++
 4 files changed, 1003 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
 create mode 100644 drivers/mtd/spi-nor/npcm-fiu.c
Signature · 6 lines
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author maintainer
#1 lore raw

PATCH 1/2 dt-binding: mtd: add NPCM FIU controller

Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI-NOR controller.

Signed-off-by Tomer Maimon <[email protected]>
---
 Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +64 -0
new file mode 100644
index 000000000000..9746cb5b1ced
@@ -0,0 +1,64 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+  - #address-cells : should be 1.
+  - #size-cells : should be 0.
+  - reg : the first contains the register location and length,
+          the second contains the memory mapping address and length
+  - reg-names: Should contain the reg names "control" and "memory"
+  - clocks : phandle of F reference clock.
+
+Required properties in case the pins can be muxed:
+  - pinctrl-names : a pinctrl state named "default" must be defined.
+  - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
+
+The SPI device must be a child of the FIU node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Required property:
+- reg: chip select number.
+
+Optional property:
+- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+  the following format 'fiu{n}' where n is a unique number for the alias.
+  In the NPCM7XX BMC:
+  		fiu0 represent fiu 0 controller
+  		fiu1 represent fiu 3 controller
+  		fiu2 represent fiu x controller
+
+Example:
+fiu3: fiu@c00000000 {
+	compatible = "nuvoton,npcm750-fiu";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
+	reg-names = "control", "memory";
+	clocks = <&clk NPCM7XX_CLK_AHB>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3_pins>;
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		partition@0 {
+			label = "flash_data";
+			reg = <0x0 0x800000>;
+		};
+	};
+};
+
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#2 lore raw

Re: [PATCH v1 1/2] dt-binding: mtd: add NPCM FIU controller

Quoted 28 lines · Tomer Maimon

Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI-NOR controller.

Signed-off-by Tomer Maimon <[email protected]>
---
 Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +13 -0
new file mode 100644
index 000000000000..9746cb5b1ced
@@ -0,0 +1,64 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+  - #address-cells : should be 1.
+  - #size-cells : should be 0.
+  - reg : the first contains the register location and length,

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 23

Quoted 10 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +10 -0
+          the second contains the memory mapping address and length
+  - reg-names: Should contain the reg names "control" and "memory"
+  - clocks : phandle of F reference clock.
+
+Required properties in case the pins can be muxed:
+  - pinctrl-names : a pinctrl state named "default" must be defined.
+  - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.

Needs a vendor prefix. Unless this is some standard SPI thing (which I've never heard of).

Quoted 7 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +7 -0
+
+The SPI device must be a child of the FIU node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Required property:
+- reg: chip select number.
+

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 40

Quoted 10 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +10 -0
+Optional property:
+- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+  the following format 'fiu{n}' where n is a unique number for the alias.
+  In the NPCM7XX BMC:
+  		fiu0 represent fiu 0 controller
+  		fiu1 represent fiu 3 controller
+  		fiu2 represent fiu x controller

Please don't make up your own aliases. Use 'spiX' if anything, but really, why do you need aliases in the first place?

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 43

Quoted 3 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +3 -0
+
+Example:
+fiu3: fiu@c00000000 {

spi@...

Quoted 24 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +21 -0
+	compatible = "nuvoton,npcm750-fiu";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
+	reg-names = "control", "memory";
+	clocks = <&clk NPCM7XX_CLK_AHB>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3_pins>;
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		partition@0 {
+			label = "flash_data";
+			reg = <0x0 0x800000>;
+		};
+	};
+};
+
Signature · 1 line
2.14.1
author maintainer
#3 lore raw

Re: [PATCH v1 1/2] dt-binding: mtd: add NPCM FIU controller

Hi Rob,

Thanks for your comments,

The spi-nor drivers are moving to spi (spi-mem), I will make sure to modify the new SPI dt-binding document according your comments once I finish the work on the new SPI driver.

https://lkml.org/lkml/2018/12/3/545

Happy new year!

Tomer

Quoted 99 lines · Rob Herring
Quoted 6 lines · Tomer Maimon

Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI-NOR controller.

Signed-off-by Tomer Maimon <[email protected]>
---
 Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64

++++++++++++++++++++++

Review

Quoted 4 lines
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
(quoted diff) +0 -0

b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt

Quoted 18 lines

new file mode 100644
index 000000000000..9746cb5b1ced

Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +13 -0
@@ -0,0 +1,64 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+  - #address-cells : should be 1.
+  - #size-cells : should be 0.
+  - reg : the first contains the register location and length,

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 23

Quoted 10 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +10 -0
+          the second contains the memory mapping address and length
+  - reg-names: Should contain the reg names "control" and "memory"
+  - clocks : phandle of F reference clock.
+
+Required properties in case the pins can be muxed:
+  - pinctrl-names : a pinctrl state named "default" must be defined.
+  - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.

Needs a vendor prefix. Unless this is some standard SPI thing (which I've never heard of).

Documentation/devicetree/bindings/mtd/npcm-fiu.txt

Quoted 12 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +12 -0
+
+The SPI device must be a child of the FIU node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Required property:
+- reg: chip select number.
+
+Optional property:
+- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases

node using

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 36

Quoted 1 line
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +1 -0
+  the following format 'fiu{n}' where n is a unique number for the

alias.

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 40

Quoted 4 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +4 -0
+  In the NPCM7XX BMC:
+             fiu0 represent fiu 0 controller
+             fiu1 represent fiu 3 controller
+             fiu2 represent fiu x controller

Please don't make up your own aliases. Use 'spiX' if anything, but really, why do you need aliases in the first place?

Documentation/devicetree/bindings/mtd/npcm-fiu.txt line 43

Quoted 3 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +3 -0
+
+Example:
+fiu3: fiu@c00000000 {

spi@...

Quoted 24 lines
Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file +21 -1
+     compatible = "nuvoton,npcm750-fiu";
+     #address-cells = <1>;
+     #size-cells = <0>;
+     reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
+     reg-names = "control", "memory";
+     clocks = <&clk NPCM7XX_CLK_AHB>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&spi3_pins>;
+     spi-nor@0 {
+             compatible = "jedec,spi-nor";
+             spi-rx-bus-width = <2>;
+             #address-cells = <1>;
+             #size-cells = <1>;
+             reg = <0>;
+             partition@0 {
+                     label = "flash_data";
+                     reg = <0x0 0x800000>;
+             };
+     };
+};
+
--

2.14.1

author maintainer
#4 lore raw

PATCH 2/2 mtd: spi-nor: add NPCM FIU controller driver

In reply to Tomer Maimon

Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver

The FIU supports single, dual or quad communication interface.

the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by using an indirect address/data mechanism.
- direct rd/wr mode: maps the flash memory into the core address space.
- SPI-X mode: used for an expansion bus to an ASIC or CPLD.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/mtd/spi-nor/Kconfig    |   8 +
 drivers/mtd/spi-nor/Makefile   |   1 +
 drivers/mtd/spi-nor/npcm-fiu.c | 930 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 939 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/npcm-fiu.c
drivers/mtd/spi-nor/Kconfig +8 -0
index 6cc9c929ff57..e3451637240a 100644
@@ -75,6 +75,14 @@ config SPI_HISI_SFC
 	help
 	  This enables support for hisilicon SPI-NOR flash controller.
 
+config SPI_NPCM_FIU
+	tristate "NPCM FLASH Interface unit(FIU) controller "
+	depends on ARCH_NPCM || COMPILE_TEST
+	help
+	  This enables support for the FLASH Interface unit(FIU) controller.
+	  This driver does not support generic SPI. The implementation only
+	  supports SPI NOR.
+
 config SPI_NXP_SPIFI
 	tristate "NXP SPI Flash Interface (SPIFI)"
 	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
drivers/mtd/spi-nor/Makefile +1 -0
index f4c61d282abd..fe0e2bdef9cd 100644
@@ -6,6 +6,7 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o
 obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
 obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
 obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
+obj-$(CONFIG_SPI_NPCM_FIU)	+= npcm-fiu.o
 obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
 obj-$(CONFIG_SPI_INTEL_SPI)	+= intel-spi.o
 obj-$(CONFIG_SPI_INTEL_SPI_PCI)	+= intel-spi-pci.o
drivers/mtd/spi-nor/npcm-fiu.c new file +930 -0

930 lines not on this page · raw message

Signature · 6 lines
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build bot
#5 lore raw

Re: [PATCH v1 2/2] mtd: spi-nor: add NPCM FIU controller driver

I love your patch! Yet something to improve:

Hi Tomer,

I love your patch! Yet something to improve:

[auto build test ERROR on mtd/spi-nor/next]
[also build test ERROR on v4.20-rc5 next-20181203]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Tomer-Maimon/dt-binding-mtd-add-NPCM-FIU-controller/20181203-201804
base:   git://git.infradead.org/linux-mtd.git spi-nor/next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386

All errors (new ones prefixed by >>):

>> drivers/mtd/spi-nor/npcm-fiu.c:25:10: fatal error: asm/sizes.h: No such file or directory
    #include <asm/sizes.h>
             ^~~~~~~~~~~~~

compilation terminated.

vim +25 drivers/mtd/spi-nor/npcm-fiu.c

    24	
  > 25	#include <asm/sizes.h>
    26	#include <mtd/mtd-abi.h>
    27

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

build bot
#6 lore raw

Re: [PATCH v1 2/2] mtd: spi-nor: add NPCM FIU controller driver

In reply to Tomer Maimon
I love your patch! Yet something to improve:

Hi Tomer,

I love your patch! Yet something to improve:

[auto build test ERROR on mtd/spi-nor/next]
[also build test ERROR on v4.20-rc6 next-20181212]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Tomer-Maimon/dt-binding-mtd-add-NPCM-FIU-controller/20181203-201804
base:   git://git.infradead.org/linux-mtd.git spi-nor/next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64

All errors (new ones prefixed by >>):

>> drivers/mtd/spi-nor/npcm-fiu.c:25:11: error: unable to open 'asm/sizes.h'

vim +25 drivers/mtd/spi-nor/npcm-fiu.c

    24	
  > 25	#include <asm/sizes.h>
    26	#include <mtd/mtd-abi.h>
    27

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

#7 lore raw
In reply to Tomer Maimon
Quoted 20 lines · On Mon, 3 Dec 2018 11:14:54 +0200 Tomer Maimon <[email protected]> wrote:

This patch set adds Flash Interface Unit(FIU) SPI-NOR support for the Nuvoton NPCM Baseboard Management Controller (BMC).

The FIU supports single, dual or quad communication interface.

the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by using an indirect address/data mechanism.
- direct rd/wr mode: maps the flash memory into the core address space.
- SPI-X mode: used for an expansion bus to an ASIC or CPLD.

The NPCM750/730/715/710 supports up to three FIU devices:
- FIU0 supports two chip select.
- FIU3 supports four chip select.
- FIUX supports two chip select.

The NPCM FIU driver tested on NPCM750 evaluation board.

Quoted 8 lines

Tomer Maimon (2):
dt-binding: mtd: add NPCM FIU controller
mtd: spi-nor: add NPCM FIU controller driver

 Documentation/devicetree/bindings/mtd/npcm-fiu.txt |  64 ++
 drivers/mtd/spi-nor/Kconfig                        |   8 +
 drivers/mtd/spi-nor/Makefile                       |   1 +
 drivers/mtd/spi-nor/npcm-fiu.c                     | 930 +++++++++++++++++++++

We are currently trying to move all SPI NOR controller drivers out of drivers/mtd/spi-nor. Can you try to implement the spi-mem interface [1] and place your driver in drivers/spi/.

[1]https://elixir.bootlin.com/linux/v4.20-rc5/source/include/linux/spi/spi-mem.h#L185

author maintainer
#8 lore raw

Hi Boris,

Thanks for getting back to me on this driver.

A few comments/input:

1. We have been working on this driver for quite a long time to port it to the latest Linux conventions, polish the code, run tests and reach high quality.
Our partners and customers are waiting to get this driver upstream so they can freely use it.
Since this driver is already in final stages and is in very good shape we will appreciate if you can review this specific driver/interface and help us to upstream it.
2. As for the new interface, we are open for any discussion and for porting the driver as required.
We are unsure what is this specific interface and weather it really fits a driver for a Flash Interface Controller module (rather than a SPI flash device).
Is it possible to get a sample driver from another Flash Interface Controller module that was ported to this new interface ? Based on this we can evaluate the required effort and assign it accordingly.

Regards,

Tomer

Quoted 40 lines · Boris Brezillon
Quoted 20 lines · On Mon, 3 Dec 2018 11:14:54 +0200 Tomer Maimon <[email protected]> wrote:

This patch set adds Flash Interface Unit(FIU) SPI-NOR support for the Nuvoton NPCM Baseboard Management Controller (BMC).

The FIU supports single, dual or quad communication interface.

the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by using an indirect address/data mechanism.
- direct rd/wr mode: maps the flash memory into the core address space.
- SPI-X mode: used for an expansion bus to an ASIC or CPLD.

The NPCM750/730/715/710 supports up to three FIU devices:
- FIU0 supports two chip select.
- FIU3 supports four chip select.
- FIUX supports two chip select.

The NPCM FIU driver tested on NPCM750 evaluation board.

Quoted 8 lines

Tomer Maimon (2):
dt-binding: mtd: add NPCM FIU controller
mtd: spi-nor: add NPCM FIU controller driver

 Documentation/devicetree/bindings/mtd/npcm-fiu.txt |  64 ++
 drivers/mtd/spi-nor/Kconfig                        |   8 +
 drivers/mtd/spi-nor/Makefile                       |   1 +
 drivers/mtd/spi-nor/npcm-fiu.c                     | 930

+++++++++++++++++++++

We are currently trying to move all SPI NOR controller drivers out of drivers/mtd/spi-nor. Can you try to implement the spi-mem interface [1] and place your driver in drivers/spi/.

[1]
https://elixir.bootlin.com/linux/v4.20-rc5/source/include/linux/spi/spi-mem.h#L185

#9 lore raw

Hi Tomer;

Quoted 8 lines · On Mon, 3 Dec 2018 16:09:19 +0200 Tomer Maimon <[email protected]> wrote:

A few comments/input:

1. We have been working on this driver for quite a long time to port it to the latest Linux conventions, polish the code, run tests and reach high quality.
Our partners and customers are waiting to get this driver upstream so they can freely use it.

Your patch prefix says "v1", so I'm assuming this is the first public version. I'm sure you spent a lot of time developing this driver internally, but no matter how long it took, it's a first version for us, and since we are moving away from the spi_nor controller interface, I'm not willing to accept new drivers using this interface.

If you want more background about the spi_nor controller interface deprecation, you can read [1].

Quoted 3 lines

Since this driver is already in final stages and is in very good shape we will appreciate if you can review this specific driver/interface and help us to upstream it.

Actually, I'd like to do it the other way around: let you rework the driver to implement the spi-mem interface and review this version. Otherwise I'll be reviewing things I don't intend to merge anyway.

Quoted 5 lines

2. As for the new interface, we are open for any discussion and for porting the driver as required.
We are unsure what is this specific interface and weather it really fits a driver for a Flash Interface Controller module (rather than a SPI flash device).

Didn't go through the code in details, but at first glance, it looks like it would fit pretty well.

Quoted 2 lines

Is it possible to get a sample driver from another Flash Interface Controller module that was ported to this new interface ?

We recently converted the atmel QSPI driver [2].

Regards,

Boris

[1]https://bootlin.com/blog/spi-mem-bringing-some-consistency-to-the-spi-memory-ecosystem/ [2]https://patchwork.kernel.org/project/spi-devel-general/list/?series=38347&state=*

author maintainer
#10 lore raw

Hi Boris,

Thanks for your prompt reply,

We will start to work on it soon.

Regards,

Tomer

Quoted 60 lines · Boris Brezillon

Hi Tomer;

Quoted 4 lines · On Mon, 3 Dec 2018 16:09:19 +0200 Tomer Maimon <[email protected]> wrote:

A few comments/input:

1. We have been working on this driver for quite a long time to port

it

Quoted 1 line

to the latest Linux conventions, polish the code, run tests and reach

high

Quoted 3 lines

quality.
Our partners and customers are waiting to get this driver upstream so they can freely use it.

Your patch prefix says "v1", so I'm assuming this is the first public version. I'm sure you spent a lot of time developing this driver internally, but no matter how long it took, it's a first version for us, and since we are moving away from the spi_nor controller interface, I'm not willing to accept new drivers using this interface.

If you want more background about the spi_nor controller interface deprecation, you can read [1].

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Since this driver is already in final stages and is in very good shape we will appreciate if you can review this specific driver/interface

and

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help us to upstream it.

Actually, I'd like to do it the other way around: let you rework the driver to implement the spi-mem interface and review this version. Otherwise I'll be reviewing things I don't intend to merge anyway.

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2. As for the new interface, we are open for any discussion and for porting the driver as required.
We are unsure what is this specific interface and weather it really

fits

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a driver for a Flash Interface Controller module (rather than a SPI

flash

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device).

Didn't go through the code in details, but at first glance, it looks like it would fit pretty well.

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Is it possible to get a sample driver from another Flash Interface Controller module that was ported to this new interface ?

We recently converted the atmel QSPI driver [2].

Regards,

Boris

[1]
https://bootlin.com/blog/spi-mem-bringing-some-consistency-to-the-spi-memory-ecosystem/
[2]
https://patchwork.kernel.org/project/spi-devel-general/list/?series=38347&state=*