soc: imx: gpcv2: prefix i.MX7 specific defines

PATCH Applied Lucas Stach 3 participants 6 messages Nov 16, 2018 – Dec 5, 2018

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Lucas Stach

author

2018-11-16 15:49 UTC #0 lore raw

PATCH 1/3 soc: imx: gpcv2: prefix i.MX7 specific defines

So we can add i.MX8M support without introducing name clashes.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/soc/imx/gpcv2.c | 56 ++++++++++++++++++++---------------------
 1 file changed, 28 insertions(+), 28 deletions(-)

drivers/soc/imx/gpcv2.c +28 ~~-28~~

index e7b5994fee9d..4183f7f830c8 100644
@@ -18,19 +18,19 @@
 #define GPC_LPCR_A_CORE_BSC			0x000
 
 #define GPC_PGC_CPU_MAPPING		0x0ec
-#define USB_HSIC_PHY_A_CORE_DOMAIN		BIT(6)
-#define USB_OTG2_PHY_A_CORE_DOMAIN		BIT(5)
-#define USB_OTG1_PHY_A_CORE_DOMAIN		BIT(4)
-#define PCIE_PHY_A_CORE_DOMAIN		BIT(3)
-#define MIPI_PHY_A_CORE_DOMAIN		BIT(2)
+#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN		BIT(6)
+#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN		BIT(5)
+#define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN		BIT(4)
+#define IMX7_PCIE_PHY_A_CORE_DOMAIN		BIT(3)
+#define IMX7_MIPI_PHY_A_CORE_DOMAIN		BIT(2)
 
 #define GPC_PU_PGC_SW_PUP_REQ		0x0f8
 #define GPC_PU_PGC_SW_PDN_REQ		0x104
-#define USB_HSIC_PHY_SW_Pxx_REQ		BIT(4)
-#define USB_OTG2_PHY_SW_Pxx_REQ		BIT(3)
-#define USB_OTG1_PHY_SW_Pxx_REQ		BIT(2)
-#define PCIE_PHY_SW_Pxx_REQ		BIT(1)
-#define MIPI_PHY_SW_Pxx_REQ		BIT(0)
+#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ		BIT(4)
+#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ		BIT(3)
+#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ		BIT(2)
+#define IMX7_PCIE_PHY_SW_Pxx_REQ		BIT(1)
+#define IMX7_MIPI_PHY_SW_Pxx_REQ		BIT(0)
 
 #define GPC_M4_PU_PDN_FLG		0x1bc

@@ -40,9 +40,9 @@
  * GPC_PGC memory map are incorrect, below offset
  * values are from design RTL.
  */
-#define PGC_MIPI			16
-#define PGC_PCIE			17
-#define PGC_USB_HSIC			20
+#define IMX7_PGC_MIPI			16
+#define IMX7_PGC_PCIE			17
+#define IMX7_PGC_USB_HSIC		20
 #define GPC_PGC_CTRL(n)			(0x800 + (n) * 0x40)
 #define GPC_PGC_SR(n)			(GPC_PGC_CTRL(n) + 0xc)

@@ -166,11 +166,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.name      = "mipi-phy",
 		},
 		.bits  = {
-			.pxx = MIPI_PHY_SW_Pxx_REQ,
-			.map = MIPI_PHY_A_CORE_DOMAIN,
+			.pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
+			.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = PGC_MIPI,
+		.pgc	   = IMX7_PGC_MIPI,
 	},
 
 	[IMX7_POWER_DOMAIN_PCIE_PHY] = {

@@ -178,11 +178,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.name      = "pcie-phy",
 		},
 		.bits  = {
-			.pxx = PCIE_PHY_SW_Pxx_REQ,
-			.map = PCIE_PHY_A_CORE_DOMAIN,
+			.pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
+			.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1000000,
-		.pgc	   = PGC_PCIE,
+		.pgc	   = IMX7_PGC_PCIE,
 	},
 
 	[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {

@@ -190,11 +190,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 			.name      = "usb-hsic-phy",
 		},
 		.bits  = {
-			.pxx = USB_HSIC_PHY_SW_Pxx_REQ,
-			.map = USB_HSIC_PHY_A_CORE_DOMAIN,
+			.pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
+			.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 		},
 		.voltage   = 1200000,
-		.pgc	   = PGC_USB_HSIC,
+		.pgc	   = IMX7_PGC_USB_HSIC,
 	},
 };

@@ -269,12 +269,12 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 	static const struct regmap_range yes_ranges[] = {
 		regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 				 GPC_M4_PU_PDN_FLG),
-		regmap_reg_range(GPC_PGC_CTRL(PGC_MIPI),
-				 GPC_PGC_SR(PGC_MIPI)),
-		regmap_reg_range(GPC_PGC_CTRL(PGC_PCIE),
-				 GPC_PGC_SR(PGC_PCIE)),
-		regmap_reg_range(GPC_PGC_CTRL(PGC_USB_HSIC),
-				 GPC_PGC_SR(PGC_USB_HSIC)),
+		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
+				 GPC_PGC_SR(IMX7_PGC_MIPI)),
+		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
+				 GPC_PGC_SR(IMX7_PGC_PCIE)),
+		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
+				 GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
 	};
 	static const struct regmap_access_table access_table = {
 		.yes_ranges	= yes_ranges,

Signature · 1 line

2.19.1

Lucas Stach

author

2018-11-16 15:49 UTC #1 lore raw

PATCH 2/3 soc: imx: gpcv2: move register access table to domain data

The valid register ranges are defined by the implemented power domains, which are different between the individual SoCs where the GPCv2 is used.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/soc/imx/gpcv2.c | 44 ++++++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 20 deletions(-)

drivers/soc/imx/gpcv2.c +24 ~~-20~~

index 4183f7f830c8..fe2cf6b61b05 100644
@@ -67,6 +67,7 @@ struct imx_pgc_domain {
 struct imx_pgc_domain_data {
 	const struct imx_pgc_domain *domains;
 	size_t domains_num;
+	const struct regmap_access_table *reg_access_table;
 };
 
 static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,

@@ -198,9 +199,26 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
 	},
 };
 
+static const struct regmap_range imx7_yes_ranges[] = {
+		regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+				 GPC_M4_PU_PDN_FLG),
+		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
+				 GPC_PGC_SR(IMX7_PGC_MIPI)),
+		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
+				 GPC_PGC_SR(IMX7_PGC_PCIE)),
+		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
+				 GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
+};
+
+static const struct regmap_access_table imx7_access_table = {
+	.yes_ranges	= imx7_yes_ranges,
+	.n_yes_ranges	= ARRAY_SIZE(imx7_yes_ranges),
+};
+
 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
 	.domains = imx7_pgc_domains,
 	.domains_num = ARRAY_SIZE(imx7_pgc_domains),
+	.reg_access_table = &imx7_access_table,
 };
 
 static int imx_pgc_domain_probe(struct platform_device *pdev)

@@ -265,27 +283,15 @@ builtin_platform_driver(imx_pgc_domain_driver)
 
 static int imx_gpcv2_probe(struct platform_device *pdev)
 {
-	static const struct imx_pgc_domain_data *domain_data;
-	static const struct regmap_range yes_ranges[] = {
-		regmap_reg_range(GPC_LPCR_A_CORE_BSC,
-				 GPC_M4_PU_PDN_FLG),
-		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
-				 GPC_PGC_SR(IMX7_PGC_MIPI)),
-		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
-				 GPC_PGC_SR(IMX7_PGC_PCIE)),
-		regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
-				 GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
-	};
-	static const struct regmap_access_table access_table = {
-		.yes_ranges	= yes_ranges,
-		.n_yes_ranges	= ARRAY_SIZE(yes_ranges),
-	};
-	static const struct regmap_config regmap_config = {
+	const struct imx_pgc_domain_data *domain_data =
+			of_device_get_match_data(&pdev->dev);
+
+	struct regmap_config regmap_config = {
 		.reg_bits	= 32,
 		.val_bits	= 32,
 		.reg_stride	= 4,
-		.rd_table	= &access_table,
-		.wr_table	= &access_table,
+		.rd_table	= domain_data->reg_access_table,
+		.wr_table	= domain_data->reg_access_table,
 		.max_register   = SZ_4K,
 	};
 	struct device *dev = &pdev->dev;

@@ -313,8 +319,6 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	domain_data = of_device_get_match_data(&pdev->dev);
-
 	for_each_child_of_node(pgc_np, np) {
 		struct platform_device *pd_pdev;
 		struct imx_pgc_domain *domain;

Signature · 1 line

2.19.1

Lucas Stach

author

2018-11-16 15:49 UTC #2 lore raw

PATCH 3/3 soc: imx: gpcv2: add support for i.MX8MQ SoC

In reply to Lucas Stach

The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping.

Signed-off-by Lucas Stach <[email protected]>

---
 .../bindings/power/fsl,imx-gpcv2.txt          |   7 +-
 drivers/soc/imx/Kconfig                       |   6 +-
 drivers/soc/imx/Makefile                      |   2 +-
 drivers/soc/imx/gpcv2.c                       | 208 +++++++++++++++++-
 include/dt-bindings/power/imx8mq-power.h      |  21 ++
 5 files changed, 237 insertions(+), 7 deletions(-)
 create mode 100644 include/dt-bindings/power/imx8mq-power.h

Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +5 -2

index 9acce75b29ab..7c947a996df1 100644
@@ -6,7 +6,9 @@ Control (PGC) for various power domains.
 
 Required properties:
 
-- compatible: Should be "fsl,imx7d-gpc"
+- compatible: Should be one of:
+	- "fsl,imx7d-gpc"
+	- "fsl,imx8mq-gpc"
 
 - reg: should be register base and length as documented in the
   datasheet

@@ -22,7 +24,8 @@ which, in turn, is expected to contain the following:
 Required properties:
 
 - reg: Power domain index. Valid values are defined in
-  include/dt-bindings/power/imx7-power.h
+  include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
+  include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
 
 - #power-domain-cells: Should be 0

drivers/soc/imx/Kconfig +3 -3

index a5b86a28f343..2112d18dbb7b 100644
@@ -1,8 +1,8 @@
 menu "i.MX SoC drivers"
 
-config IMX7_PM_DOMAINS
-	bool "i.MX7 PM domains"
-	depends on SOC_IMX7D || (COMPILE_TEST && OF)
+config IMX_GPCV2_PM_DOMAINS
+	bool "i.MX GPCv2 PM domains"
+	depends on SOC_IMX7D || SOC_IMX8MQ || (COMPILE_TEST && OF)
 	depends on PM
 	select PM_GENERIC_DOMAINS
 	default y if SOC_IMX7D

drivers/soc/imx/Makefile +1 -1

index aab41a5cc317..506a6f3c2b9b 100644
@@ -1,2 +1,2 @@
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
-obj-$(CONFIG_IMX7_PM_DOMAINS) += gpcv2.o
+obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o

drivers/soc/imx/gpcv2.c +207 -1

256 lines not on this page · raw message

include/dt-bindings/power/imx8mq-power.h new file +21 -0

new file mode 100644
index 000000000000..8a513bd9166e
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright (C) 2018 Pengutronix, Lucas Stach <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__
+#define __DT_BINDINGS_IMX8MQ_POWER_H__
+
+#define IMX8M_POWER_DOMAIN_MIPI		0
+#define IMX8M_POWER_DOMAIN_PCIE1	1
+#define IMX8M_POWER_DOMAIN_USB_OTG1	2
+#define IMX8M_POWER_DOMAIN_USB_OTG2	3
+#define IMX8M_POWER_DOMAIN_DDR1		4
+#define IMX8M_POWER_DOMAIN_GPU		5
+#define IMX8M_POWER_DOMAIN_VPU		6
+#define IMX8M_POWER_DOMAIN_DISP		7
+#define IMX8M_POWER_DOMAIN_MIPI_CSI1	8
+#define IMX8M_POWER_DOMAIN_MIPI_CSI2	9
+#define IMX8M_POWER_DOMAIN_PCIE2	10
+
+#endif

Signature · 1 line

2.19.1

Shawn Guo

2018-11-28 02:57 UTC #3 lore raw

PATCH 3/3 soc: imx: gpcv2: add support for i.MX8MQ SoC

Quoted 7 lines · Lucas Stach

The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping.
Signed-off-by Lucas Stach <[email protected]>
---
 .../bindings/power/fsl,imx-gpcv2.txt          |   7 +-

The series looks good to me.

@Rob, can you please ACK on the bindings change?

Shawn

Quoted 31 lines

 drivers/soc/imx/Kconfig                       |   6 +-
 drivers/soc/imx/Makefile                      |   2 +-
 drivers/soc/imx/gpcv2.c                       | 208 +++++++++++++++++-
 include/dt-bindings/power/imx8mq-power.h      |  21 ++
 5 files changed, 237 insertions(+), 7 deletions(-)
 create mode 100644 include/dt-bindings/power/imx8mq-power.h

Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +5 -2

index 9acce75b29ab..7c947a996df1 100644
@@ -6,7 +6,9 @@ Control (PGC) for various power domains.
 
 Required properties:
 
-- compatible: Should be "fsl,imx7d-gpc"
+- compatible: Should be one of:
+	- "fsl,imx7d-gpc"
+	- "fsl,imx8mq-gpc"
 
 - reg: should be register base and length as documented in the
   datasheet

@@ -22,7 +24,8 @@ which, in turn, is expected to contain the following:
 Required properties:
 
 - reg: Power domain index. Valid values are defined in
-  include/dt-bindings/power/imx7-power.h
+  include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
+  include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
 
 - #power-domain-cells: Should be 0

Rob Herring

maintainer Acked-by on v1 3/3

2018-12-04 22:00 UTC #4 lore raw

Re: [PATCH 3/3] soc: imx: gpcv2: add support for i.MX8MQ SoC

In reply to Lucas Stach

Quoted 7 lines · Lucas Stach

The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping.
Signed-off-by Lucas Stach <[email protected]>
---
 .../bindings/power/fsl,imx-gpcv2.txt          |   7 +-

Acked-by Rob Herring <[email protected]>

Quoted 6 lines

 drivers/soc/imx/Kconfig                       |   6 +-
 drivers/soc/imx/Makefile                      |   2 +-
 drivers/soc/imx/gpcv2.c                       | 208 +++++++++++++++++-
 include/dt-bindings/power/imx8mq-power.h      |  21 ++
 5 files changed, 237 insertions(+), 7 deletions(-)
 create mode 100644 include/dt-bindings/power/imx8mq-power.h

Shawn Guo

Applied

2018-12-05 00:51 UTC #5 lore raw

In reply to Lucas Stach

Quoted 3 lines · Lucas Stach

So we can add i.MX8M support without introducing name clashes.
Signed-off-by Lucas Stach <[email protected]>

Applied all, thanks.