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ARM: dts: sunxi: Fix PMU compatible strings

PATCH Applied Rob Herring 3 participants 3 messages Dec 6, 2018 – Dec 7, 2018

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Device tree bindings Arm/Allwinner sunXi SoC support
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Rob Herring

author maintainer
#0 lore raw

PATCH 1/1 ARM: dts: sunxi: Fix PMU compatible strings

"arm,cortex-a15-pmu" is not a valid fallback compatible string for an Cortex-A7 PMU, so drop it.

Cc Maxime Ripard <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Rob Herring <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
 arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/sun6i-a31.dtsi +1 -1
index a960b8ef7822..9e7931d5e42a 100644
@@ -202,7 +202,7 @@
 	};
 
 	pmu {
-		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
arch/arm/boot/dts/sun7i-a20.dtsi +1 -1
index 3c571dc599c3..5e413a5d9f6d 100644
@@ -199,7 +199,7 @@
 	};
 
 	pmu {
-		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 	};
Signature · 1 line
2.19.1
Acked-by on v1 1/1
#1 lore raw
Quoted 29 lines · Rob Herring

"arm,cortex-a15-pmu" is not a valid fallback compatible string for an Cortex-A7 PMU, so drop it.

Cc Maxime Ripard <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Rob Herring <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
 arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/sun6i-a31.dtsi +1 -1
index a960b8ef7822..9e7931d5e42a 100644
@@ -202,7 +202,7 @@
 	};
 
 	pmu {
-		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
arch/arm/boot/dts/sun7i-a20.dtsi +0 -0
index 3c571dc599c3..5e413a5d9f6d 100644

arch/arm/boot/dts/sun7i-a20.dtsi line 204

Quoted 7 lines
arch/arm/boot/dts/sun7i-a20.dtsi +1 -1
@@ -199,7 +199,7 @@
 	};
 
 	pmu {
-		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
Acked-by Will Deacon <[email protected]>

Will