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drm/amdgpu: update the vm invalidation engine layout V2

PATCH In review Evan Quan 2 participants 2 messages Dec 14, 2018 1 message not in the archive

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DRM drivers Radeon and amdgpu DRM drivers
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Evan Quan

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PATCH 1/1 drm/amdgpu: update the vm invalidation engine layout V2

We need new invalidation engine layout due to new SDMA page queues added.

V2: fix coding style and add correct return value

Change-Id I2f3861689bffb9828c9eae744a7a0de4963ac2b6
Signed-off-by Evan Quan <[email protected]>
Reviewed-by Christian König <[email protected]>
Reviewed-by Oak Zeng <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 53 ++++++++++++++++-----------
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 10 +++++
 2 files changed, 41 insertions(+), 22 deletions(-)
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +31 -22
index dc4dadc3575c..ce8d41514e0d 100644
@@ -719,37 +719,46 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 	}
 }
 
-static int gmc_v9_0_late_init(void *handle)
+static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 {
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	/*
-	 * The latest engine allocation on gfx9 is:
-	 * Engine 0, 1: idle
-	 * Engine 2, 3: firmware
-	 * Engine 4~13: amdgpu ring, subject to change when ring number changes
-	 * Engine 14~15: idle
-	 * Engine 16: kfd tlb invalidation
-	 * Engine 17: Gart flushes
-	 */
-	unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
+	struct amdgpu_ring *ring;
+	unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
+		{GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
 	unsigned i;
-	int r;
+	unsigned vmhub, inv_eng;
 
-	if (!gmc_v9_0_keep_stolen_memory(adev))
-		amdgpu_bo_late_init(adev);
+	for (i = 0; i < adev->num_rings; ++i) {
+		ring = adev->rings[i];
+		vmhub = ring->funcs->vmhub;
+
+		inv_eng = ffs(vm_inv_engs[vmhub]);
+		if (!inv_eng) {
+			dev_err(adev->dev, "no VM inv eng for ring %s\n",
+				ring->name);
+			return -EINVAL;
+		}
 
-	for(i = 0; i < adev->num_rings; ++i) {
-		struct amdgpu_ring *ring = adev->rings[i];
-		unsigned vmhub = ring->funcs->vmhub;
+		ring->vm_inv_eng = inv_eng - 1;
+		change_bit(inv_eng - 1, (unsigned long *)(&vm_inv_engs[vmhub]));
 
-		ring->vm_inv_eng = vm_inv_eng[vmhub]++;
 		dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 			 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 	}
 
-	/* Engine 16 is used for KFD and 17 for GART flushes */
-	for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
-		BUG_ON(vm_inv_eng[i] > 16);
+	return 0;
+}
+
+static int gmc_v9_0_late_init(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int r;
+
+	if (!gmc_v9_0_keep_stolen_memory(adev))
+		amdgpu_bo_late_init(adev);
+
+	r = gmc_v9_0_allocate_vm_inv_eng(adev);
+	if (r)
+		return r;
 
 	if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
 		r = gmc_v9_0_ecc_available(adev);
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h +10 -0
index b030ca5ea107..5c8deac65580 100644
@@ -24,6 +24,16 @@
 #ifndef __GMC_V9_0_H__
 #define __GMC_V9_0_H__
 
+	/*
+	 * The latest engine allocation on gfx9 is:
+	 * Engine 2, 3: firmware
+	 * Engine 0, 1, 4~16: amdgpu ring,
+	 *                    subject to change when ring number changes
+	 * Engine 17: Gart flushes
+	 */
+#define GFXHUB_FREE_VM_INV_ENGS_BITMAP		0x1FFF3
+#define MMHUB_FREE_VM_INV_ENGS_BITMAP		0x1FFF3
+
 extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
Signature · 6 lines
2.19.2

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A message that is not in the archive (sent off-list or not yet received): [email protected]

Reviewed-by Felix Kuehling Reviewed-by Christian König Reviewed-by Oak Zeng
#2 lore raw
Reviewed-by Felix Kuehling <[email protected]>

Thanks,
Felix

________________________________________
From: amd-gfx <[email protected]> on behalf of Evan Quan <[email protected]>
Sent: Thursday, December 13, 2018 9:59:30 PM
To: [email protected]
Cc: Kuehling, Felix; Quan, Evan
Subject: [PATCH] drm/amdgpu: update the vm invalidation engine layout V2

We need new invalidation engine layout due to new SDMA page queues added.

V2: fix coding style and add correct return value

Change-Id I2f3861689bffb9828c9eae744a7a0de4963ac2b6
Signed-off-by Evan Quan <[email protected]>
Reviewed-by Christian König <[email protected]>
Reviewed-by Oak Zeng <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 53 ++++++++++++++++-----------
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 10 +++++
 2 files changed, 41 insertions(+), 22 deletions(-)
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +31 -22
index dc4dadc3575c..ce8d41514e0d 100644
@@ -719,37 +719,46 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
        }
 }
 
-static int gmc_v9_0_late_init(void *handle)
+static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       /*
-        * The latest engine allocation on gfx9 is:
-        * Engine 0, 1: idle
-        * Engine 2, 3: firmware
-        * Engine 4~13: amdgpu ring, subject to change when ring number changes
-        * Engine 14~15: idle
-        * Engine 16: kfd tlb invalidation
-        * Engine 17: Gart flushes
-        */
-       unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
+       struct amdgpu_ring *ring;
+       unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
+               {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
        unsigned i;
-       int r;
+       unsigned vmhub, inv_eng;
 
-       if (!gmc_v9_0_keep_stolen_memory(adev))
-               amdgpu_bo_late_init(adev);
+       for (i = 0; i < adev->num_rings; ++i) {
+               ring = adev->rings[i];
+               vmhub = ring->funcs->vmhub;
+
+               inv_eng = ffs(vm_inv_engs[vmhub]);
+               if (!inv_eng) {
+                       dev_err(adev->dev, "no VM inv eng for ring %s\n",
+                               ring->name);
+                       return -EINVAL;
+               }
 
-       for(i = 0; i < adev->num_rings; ++i) {
-               struct amdgpu_ring *ring = adev->rings[i];
-               unsigned vmhub = ring->funcs->vmhub;
+               ring->vm_inv_eng = inv_eng - 1;
+               change_bit(inv_eng - 1, (unsigned long *)(&vm_inv_engs[vmhub]));
 
-               ring->vm_inv_eng = vm_inv_eng[vmhub]++;
                dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
                         ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
        }
 
-       /* Engine 16 is used for KFD and 17 for GART flushes */
-       for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
-               BUG_ON(vm_inv_eng[i] > 16);
+       return 0;
+}
+
+static int gmc_v9_0_late_init(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int r;
+
+       if (!gmc_v9_0_keep_stolen_memory(adev))
+               amdgpu_bo_late_init(adev);
+
+       r = gmc_v9_0_allocate_vm_inv_eng(adev);
+       if (r)
+               return r;
 
        if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
                r = gmc_v9_0_ecc_available(adev);
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h +10 -0
index b030ca5ea107..5c8deac65580 100644
@@ -24,6 +24,16 @@
 #ifndef __GMC_V9_0_H__
 #define __GMC_V9_0_H__
 
+       /*
+        * The latest engine allocation on gfx9 is:
+        * Engine 2, 3: firmware
+        * Engine 0, 1, 4~16: amdgpu ring,
+        *                    subject to change when ring number changes
+        * Engine 17: Gart flushes
+        */
+#define GFXHUB_FREE_VM_INV_ENGS_BITMAP         0x1FFF3
+#define MMHUB_FREE_VM_INV_ENGS_BITMAP          0x1FFF3
+
 extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;

--
2.19.2

_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx