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Add support for the SoCs found in Microsemi switches

PATCH New Gregory CLEMENT 2 participants 14 messages Dec 14, 2018 – Dec 17, 2018

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MIPS Arm/actions semi architecture
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Gregory CLEMENT

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#0 lore raw

v4 cover Add support for the SoCs found in Microsemi switches

Hello,

For the record this the fourth version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III.

We found them on various advanced switches product.

The support for Ocelot already have been submit to Linux, but not yet the Luton support.

The comments on v3 were fewer and quite easy to address, so I am able to send a new version right one (hopping it will be the final one :) ).

Gregory

Changelog:

v3 -> v4:

- add the support for the legacy kernel more generic and more related to the old bootloader: redboot
- removed useless test on CONFIG_ARCH_MSCC in arch/mips/mach-mscc/include/ioremap.h
- add an explanation about the cache instruction lock in hal_vcoreiii_ddr_failed()
- use __raw_read/write instead of directly use pointer dereferencing
- use rmb instead of asm volatile("" : : : "memory");
- remove remaining C++ style comment
- use __maybe_unused instead of __attribute__ ((unused))
- indent by an extra space the instructions in the delay slot

v2 -> v3:
- Added n entry in the MAINTAINER file for the SoCs
- Fixup the last errors from checkpatch, the remaining ones are only about volatile, long line and Kconfig, but each ones have good reason to be here.
- Add SPI NAND flash support in device tree and configuration files, the driver are already be merged in U-Boot.
- In order to improve boot time, setup the TLB to allow using cache in the memory mapped to the SPI NOR.
- Removed all the macro REG_CFG to only keep direct access to memory.
- Put back the setting of the interrupt map as it is needed by mainline kernel (without it the kernel doesn't finish to boot)
- During DDR training, prevent the compiler reordering the instruction.
- Add early debug support to Ocelot (it was already done for Luton)

v1 -> v2:
- a big clean-up for indentation and some style issue
- usage of the clrsetbits family functions where it was possible
- split the patches for Ocelot and Luton
- add a new patch to introduce the icache_lock function which was in the mscc directory in the first version
- remove more unused define in the platform header files
- use the automatic cache size detection instead of hard coding it
- reduce the tlb init to only two entries for the IO as needed by the kernel
- remove the interrupt disabling
- fix the ddr init for luton

Gregory CLEMENT (7):
MIPS: move create_tlb() in an proper header: mipsregs.h
MIPS: Allow to prefetch and lock instructions into cache
MSCC: add support for Ocelot SoCs
MSCC: add support for Luton SoCs
MSCC: add board support for the Ocelots based evaluation boards
MSCC: add board support for the Luton based evaluation board
MIPS: bootm: Add support for compatibility with redboot

 MAINTAINERS                                   |  13 +
 arch/mips/Kconfig                             |  10 +
 arch/mips/Makefile                            |   1 +
 arch/mips/cpu/cpu.c                           |  10 -
 arch/mips/dts/luton_pcb091.dts                |  36 +
 arch/mips/dts/mscc,luton.dtsi                 |  87 ++
 arch/mips/dts/mscc,ocelot.dtsi                | 152 ++++
 arch/mips/dts/mscc,ocelot_pcb.dtsi            |  42 +
 arch/mips/dts/ocelot_pcb120.dts               |  12 +
 arch/mips/dts/ocelot_pcb123.dts               |  12 +
 arch/mips/include/asm/cacheops.h              |  19 +
 arch/mips/include/asm/mipsregs.h              |  11 +
 arch/mips/lib/bootm.c                         |  76 +-
 arch/mips/mach-mscc/Kconfig                   |  86 ++
 arch/mips/mach-mscc/Makefile                  |   6 +
 arch/mips/mach-mscc/cpu.c                     | 102 +++
 arch/mips/mach-mscc/dram.c                    |  73 ++
 arch/mips/mach-mscc/include/ioremap.h         |  49 ++
 arch/mips/mach-mscc/include/mach/common.h     |  28 +
 arch/mips/mach-mscc/include/mach/ddr.h        | 814 ++++++++++++++++++
 .../mips/mach-mscc/include/mach/luton/luton.h |  24 +
 .../include/mach/luton/luton_devcpu_gcb.h     |  14 +
 .../include/mach/luton/luton_icpu_cfg.h       | 245 ++++++
 .../mach-mscc/include/mach/ocelot/ocelot.h    |  24 +
 .../include/mach/ocelot/ocelot_devcpu_gcb.h   |  21 +
 .../include/mach/ocelot/ocelot_icpu_cfg.h     | 274 ++++++
 arch/mips/mach-mscc/include/mach/tlb.h        |  55 ++
 arch/mips/mach-mscc/lowlevel_init.S           |  30 +
 arch/mips/mach-mscc/lowlevel_init_luton.S     |  62 ++
 arch/mips/mach-mscc/reset.c                   |  30 +
 board/mscc/luton/Kconfig                      |  14 +
 board/mscc/luton/Makefile                     |   3 +
 board/mscc/luton/luton.c                      |  28 +
 board/mscc/ocelot/Kconfig                     |  14 +
 board/mscc/ocelot/Makefile                    |   4 +
 board/mscc/ocelot/ocelot.c                    |  58 ++
 configs/mscc_luton_defconfig                  |  66 ++
 configs/mscc_ocelot_defconfig                 |  73 ++
 configs/mscc_ocelot_pcb120_defconfig          |  66 ++
 include/configs/vcoreiii.h                    |  82 ++
 40 files changed, 2796 insertions(+), 30 deletions(-)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
 create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
 create mode 100644 arch/mips/dts/ocelot_pcb120.dts
 create mode 100644 arch/mips/dts/ocelot_pcb123.dts
 create mode 100644 arch/mips/mach-mscc/Kconfig
 create mode 100644 arch/mips/mach-mscc/Makefile
 create mode 100644 arch/mips/mach-mscc/cpu.c
 create mode 100644 arch/mips/mach-mscc/dram.c
 create mode 100644 arch/mips/mach-mscc/include/ioremap.h
 create mode 100644 arch/mips/mach-mscc/include/mach/common.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
 create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
 create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
 create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
 create mode 100644 arch/mips/mach-mscc/reset.c
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 board/mscc/ocelot/Kconfig
 create mode 100644 board/mscc/ocelot/Makefile
 create mode 100644 board/mscc/ocelot/ocelot.c
 create mode 100644 configs/mscc_luton_defconfig
 create mode 100644 configs/mscc_ocelot_defconfig
 create mode 100644 configs/mscc_ocelot_pcb120_defconfig
 create mode 100644 include/configs/vcoreiii.h
Signature · 1 line
2.19.2
author
#1 lore raw

PATCH v4 1/7 MIPS: move create_tlb() in an proper header: mipsregs.h

Export create_tlb() as an inline function in mipsregs.h. It allows to remove the declaration of the function from the board files.

Then it will allow also to use this function very early in the boot when the stack is not usable.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/mips/cpu/cpu.c              | 10 ----------
 arch/mips/include/asm/mipsregs.h | 11 +++++++++++
 2 files changed, 11 insertions(+), 10 deletions(-)
arch/mips/cpu/cpu.c +0 -10
index 5c56ab0289..a403ff729b 100644
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 }
 #endif
 
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
-	write_c0_entrylo0(low0);
-	write_c0_pagemask(pagemask);
-	write_c0_entrylo1(low1);
-	write_c0_entryhi(hi);
-	write_c0_index(index);
-	tlb_write_indexed();
-}
-
 int arch_cpu_init(void)
 {
 	mips_cache_probe();
arch/mips/include/asm/mipsregs.h +11 -0
index 48fa1f1f7f..930562ebb2 100644
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
 	return read_c0_ebase() & 0x3ff;
 }
 
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+				 u32 low1)
+{
+	write_c0_entrylo0(low0);
+	write_c0_pagemask(pagemask);
+	write_c0_entrylo1(low1);
+	write_c0_entryhi(hi);
+	write_c0_index(index);
+	tlb_write_indexed();
+}
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_MIPSREGS_H */
Signature · 1 line
2.19.2
author
#2 lore raw

PATCH v4 2/7 MIPS: Allow to prefetch and lock instructions into cache

In reply to Gregory CLEMENT

This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/mips/include/asm/cacheops.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
arch/mips/include/asm/cacheops.h +19 -0
index 3161875441..98b67ccc8e 100644
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr)
 #endif
 }
 
+#define MIPS32_WHICH_ICACHE                    0x0
+#define MIPS32_FETCH_AND_LOCK                  0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+	int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+	for (i = 0; i < lines; i++) {
+		asm volatile (" cache %0, %1(%2)"
+			      : /* No Output */
+			      : "I" ICACHE_LOAD_LOCK,
+				"n" (i * ARCH_DMA_MINALIGN),
+				"r" (func)
+			      : /* No Clobbers */);
+	}
+}
 #endif /* !__ASSEMBLY__ */
 
 /*
Signature · 1 line
2.19.2
author
#3 lore raw

PATCH v4 3/7 MSCC: add support for Ocelot SoCs

In reply to Gregory CLEMENT

This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                                   |   7 +
 arch/mips/Kconfig                             |   6 +
 arch/mips/Makefile                            |   1 +
 arch/mips/mach-mscc/Kconfig                   |  69 ++
 arch/mips/mach-mscc/Makefile                  |   5 +
 arch/mips/mach-mscc/cpu.c                     |  90 +++
 arch/mips/mach-mscc/dram.c                    |  71 ++
 arch/mips/mach-mscc/include/ioremap.h         |  49 ++
 arch/mips/mach-mscc/include/mach/common.h     |  24 +
 arch/mips/mach-mscc/include/mach/ddr.h        | 708 ++++++++++++++++++
 .../mach-mscc/include/mach/ocelot/ocelot.h    |  24 +
 .../include/mach/ocelot/ocelot_devcpu_gcb.h   |  21 +
 .../include/mach/ocelot/ocelot_icpu_cfg.h     | 274 +++++++
 arch/mips/mach-mscc/include/mach/tlb.h        |  55 ++
 arch/mips/mach-mscc/lowlevel_init.S           |  23 +
 arch/mips/mach-mscc/reset.c                   |  30 +
 16 files changed, 1457 insertions(+)
 create mode 100644 arch/mips/mach-mscc/Kconfig
 create mode 100644 arch/mips/mach-mscc/Makefile
 create mode 100644 arch/mips/mach-mscc/cpu.c
 create mode 100644 arch/mips/mach-mscc/dram.c
 create mode 100644 arch/mips/mach-mscc/include/ioremap.h
 create mode 100644 arch/mips/mach-mscc/include/mach/common.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
 create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
 create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
 create mode 100644 arch/mips/mach-mscc/reset.c
MAINTAINERS +7 -0
index abdb6dcdb5..53a3c5bec6 100644
@@ -484,6 +484,13 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-mips.git
 F:	arch/mips/
 
+MIPS MSCC
+M:	Gregory CLEMENT <[email protected]>
+M:	Lars Povlsen <[email protected]>
+M:	Horatiu Vultur <[email protected]>
+S:	Maintained
+F:	arch/mips/mach-mscc/
+
 MMC
 M:	Jaehoon Chung <[email protected]>
 S:	Maintained
arch/mips/Kconfig +6 -0
index 6d646ef999..bfe9c11069 100644
@@ -59,6 +59,11 @@ config ARCH_ATH79
 	select OF_CONTROL
 	imply CMD_DM
 
+config ARCH_MSCC
+	bool "Support MSCC VCore-III"
+	select OF_CONTROL
+	select DM
+
 config ARCH_BMIPS
 	bool "Support BMIPS SoCs"
 	select CLK

@@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-mscc/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
arch/mips/Makefile +1 -0
index 802244a06e..124e93fa26 100644
@@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
+machine-$(CONFIG_ARCH_MSCC) += mscc
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
arch/mips/mach-mscc/Kconfig new file +69 -0

69 lines not on this page · raw message

arch/mips/mach-mscc/Makefile new file +5 -0
new file mode 100644
index 0000000000..d14ec33838
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+CFLAGS_cpu.o += -finline-limit=64000
+
+obj-y += cpu.o dram.o reset.o lowlevel_init.o
arch/mips/mach-mscc/cpu.c new file +90 -0

90 lines not on this page · raw message

arch/mips/mach-mscc/dram.c new file +71 -0

71 lines not on this page · raw message

arch/mips/mach-mscc/include/ioremap.h new file +49 -0

49 lines not on this page · raw message

arch/mips/mach-mscc/include/mach/common.h new file +24 -0
new file mode 100644
index 0000000000..842462aeed
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __ASM_MACH_COMMON_H
+#define __ASM_MACH_COMMON_H
+
+#if defined(CONFIG_SOC_OCELOT)
+#include <mach/ocelot/ocelot.h>
+#include <mach/ocelot/ocelot_devcpu_gcb.h>
+#include <mach/ocelot/ocelot_icpu_cfg.h>
+#else
+#error Unsupported platform
+#endif
+
+#define MSCC_DDR_TO	0x20000000	/* DDR RAM base offset */
+#define MSCC_MEMCTL1_TO	0x40000000	/* SPI/PI base offset */
+#define MSCC_MEMCTL2_TO	0x50000000	/* SPI/PI base offset */
+#define MSCC_FLASH_TO	MSCC_MEMCTL1_TO	/* Flash base offset */
+
+#define VCOREIII_TIMER_DIVIDER 25	/* Clock tick ~ 0.1 us */
+
+#endif				/* __ASM_MACH_COMMON_H */
arch/mips/mach-mscc/include/mach/ddr.h new file +708 -0

708 lines not on this page · raw message

arch/mips/mach-mscc/include/mach/ocelot/ocelot.h new file +24 -0
new file mode 100644
index 0000000000..2cb2135d37
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Ocelot Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_H_
+#define _MSCC_OCELOT_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN1_SIZE   0x00200000
+#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
+#define MSCC_IO_ORIGIN2_SIZE   0x01000000
+#define BASE_CFG        ((void __iomem *)0x70000000)
+#define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
+
+#endif
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h new file +21 -0
new file mode 100644
index 0000000000..f8aa97ba26
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
+#define _MSCC_OCELOT_DEVCPU_GCB_H_
+
+#define PERF_SOFT_RST                                     0x8
+
+#define PERF_SOFT_RST_SOFT_NON_CFG_RST                    BIT(2)
+#define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
+
+#define PERF_GPIO_OUT_SET                                 0x34
+
+#define PERF_GPIO_OUT_CLR                                 0x38
+
+#define PERF_GPIO_OE                                      0x44
+
+#endif
arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h new file +274 -0

274 lines not on this page · raw message

arch/mips/mach-mscc/include/mach/tlb.h new file +55 -0

55 lines not on this page · raw message

arch/mips/mach-mscc/lowlevel_init.S new file +23 -0
new file mode 100644
index 0000000000..f8f14adf61
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+    .set noreorder
+    .extern     vcoreiii_tlb_init
+
+LEAF(lowlevel_init)
+	/*
+	 * As we have no stack yet, we can assume the restricted
+	 * luxury of the sX-registers without saving them
+	 */
+	move	s0,ra
+
+	jal	vcoreiii_tlb_init
+	 nop
+	jr	s0
+	 nop
+	END(lowlevel_init)
arch/mips/mach-mscc/reset.c new file +30 -0
new file mode 100644
index 0000000000..390bbd086a
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#include <asm/sections.h>
+#include <asm/io.h>
+
+#include <asm/reboot.h>
+
+void _machine_restart(void)
+{
+	register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
+	(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+	/* Make sure VCore is NOT protected from reset */
+	clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
+
+	/* Change to SPI bitbang for SPI reset workaround... */
+	writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
+	       ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
+
+	/* Do the global reset */
+	writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+	while (1)
+		; /* NOP */
+}
Signature · 1 line
2.19.2
author
#4 lore raw

PATCH v4 4/7 MSCC: add support for Luton SoCs

In reply to Gregory CLEMENT

As the Ocelots SoCs, this family of SoCs are found in the Microsemi Switches solution.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/mips/mach-mscc/Kconfig                   |  13 +
 arch/mips/mach-mscc/Makefile                  |   1 +
 arch/mips/mach-mscc/cpu.c                     |  14 +-
 arch/mips/mach-mscc/dram.c                    |   2 +
 arch/mips/mach-mscc/include/mach/common.h     |   4 +
 arch/mips/mach-mscc/include/mach/ddr.h        | 112 +++++++-
 .../mips/mach-mscc/include/mach/luton/luton.h |  24 ++
 .../include/mach/luton/luton_devcpu_gcb.h     |  14 +
 .../include/mach/luton/luton_icpu_cfg.h       | 245 ++++++++++++++++++
 arch/mips/mach-mscc/lowlevel_init.S           |   7 +
 arch/mips/mach-mscc/lowlevel_init_luton.S     |  62 +++++
 11 files changed, 494 insertions(+), 4 deletions(-)
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
 create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
arch/mips/mach-mscc/Kconfig +13 -0
index 7f1b270207..a8cace0e79 100644
@@ -21,6 +21,12 @@ config SOC_OCELOT
 	help
 	  This supports MSCC Ocelot family of SOCs.
 
+config SOC_LUTON
+	bool
+	select SOC_VCOREIII
+	help
+	  This supports MSCC Luton family of SOCs.
+
 config SYS_CONFIG_NAME
 	default "vcoreiii"
 

@@ -41,6 +47,13 @@ config TARGET_OCELOT_PCB123
 	  When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
 	  ocelot_pcb123
 
+config TARGET_LUTON_PCB091
+	bool "MSCC PCB091 Reference Board"
+	select SOC_LUTON
+	select MSCC_BITBANG_SPI_GPIO
+	help
+	  When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+	  luton_pcb091
 endchoice
 
 choice
arch/mips/mach-mscc/Makefile +1 -0
index d14ec33838..6c60f26ca4 100644
@@ -3,3 +3,4 @@
 CFLAGS_cpu.o += -finline-limit=64000
 
 obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
arch/mips/mach-mscc/cpu.c +13 -1
index b503e1407b..5be8ff69d5 100644
@@ -48,6 +48,10 @@ void vcoreiii_tlb_init(void)
 	 */
 	create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
 		   MMU_REGIO_RW);
+#ifdef CONFIG_SOC_LUTON
+	create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
+		   MMU_REGIO_RW);
+#endif
 
 #if  CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
 	/*

@@ -75,6 +79,14 @@ void vcoreiii_tlb_init(void)
 int mach_cpu_init(void)
 {
 	/* Speed up NOR flash access */
+#ifdef CONFIG_SOC_LUTON
+	writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
+	       ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
+
+	writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+	       ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+	       ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
+#else
 	writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
 	       ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
 	/*

@@ -85,6 +97,6 @@ int mach_cpu_init(void)
 	writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
 	writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
 	writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
-
+#endif
 	return 0;
 }
arch/mips/mach-mscc/dram.c +2 -0
index 5acee6f918..309007c14e 100644
@@ -19,9 +19,11 @@ static inline int vcoreiii_train_bytelane(void)
 
 	ret = hal_vcoreiii_train_bytelane(0);
 
+#ifdef CONFIG_SOC_OCELOT
 	if (ret)
 		return ret;
 	ret = hal_vcoreiii_train_bytelane(1);
+#endif
 
 	return ret;
 }
arch/mips/mach-mscc/include/mach/common.h +4 -0
index 842462aeed..931ecd7985 100644
@@ -10,6 +10,10 @@
 #include <mach/ocelot/ocelot.h>
 #include <mach/ocelot/ocelot_devcpu_gcb.h>
 #include <mach/ocelot/ocelot_icpu_cfg.h>
+#elif defined(CONFIG_SOC_LUTON)
+#include <mach/luton/luton.h>
+#include <mach/luton/luton_devcpu_gcb.h>
+#include <mach/luton/luton_icpu_cfg.h>
 #else
 #error Unsupported platform
 #endif
arch/mips/mach-mscc/include/mach/ddr.h +109 -3

158 lines not on this page · raw message

arch/mips/mach-mscc/include/mach/luton/luton.h new file +24 -0
new file mode 100644
index 0000000000..19f02ede66
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Ocelot Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_H_
+#define _MSCC_OCELOT_H_
+
+#include <linux/bitops.h>
+#include <dm.h>
+
+/*
+ * Target offset base(s)
+ */
+#define MSCC_IO_ORIGIN1_OFFSET 0x60000000
+#define MSCC_IO_ORIGIN1_SIZE   0x01000000
+#define MSCC_IO_ORIGIN2_OFFSET 0x70000000
+#define MSCC_IO_ORIGIN2_SIZE   0x00200000
+#define BASE_CFG        ((void __iomem *)0x70000000)
+#define BASE_DEVCPU_GCB ((void __iomem *)0x60070000)
+
+#endif
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h new file +14 -0
new file mode 100644
index 0000000000..8c0b612325
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
+#define _MSCC_OCELOT_DEVCPU_GCB_H_
+
+#define PERF_SOFT_RST                                     0x90
+
+#define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
+#define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
+
+#endif
arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h new file +245 -0

245 lines not on this page · raw message

arch/mips/mach-mscc/lowlevel_init.S +7 -0
index f8f14adf61..dfbe06766c 100644
@@ -8,6 +8,9 @@
 
     .set noreorder
     .extern     vcoreiii_tlb_init
+#ifdef CONFIG_SOC_LUTON
+    .extern     pll_init
+#endif
 
 LEAF(lowlevel_init)
 	/*

@@ -18,6 +21,10 @@ LEAF(lowlevel_init)
 
 	jal	vcoreiii_tlb_init
 	 nop
+#ifdef CONFIG_SOC_LUTON
+	jal	pll_init
+	 nop
+#endif
 	jr	s0
 	 nop
 	END(lowlevel_init)
arch/mips/mach-mscc/lowlevel_init_luton.S new file +62 -0

62 lines not on this page · raw message

Signature · 1 line
2.19.2
author
#5 lore raw

PATCH v4 5/7 MSCC: add board support for the Ocelots based evaluation boards

In reply to Gregory CLEMENT

Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                          |   5 +
 arch/mips/dts/mscc,ocelot.dtsi       | 152 +++++++++++++++++++++++++++
 arch/mips/dts/mscc,ocelot_pcb.dtsi   |  42 ++++++++
 arch/mips/dts/ocelot_pcb120.dts      |  12 +++
 arch/mips/dts/ocelot_pcb123.dts      |  12 +++
 arch/mips/mach-mscc/Kconfig          |   2 +
 board/mscc/ocelot/Kconfig            |  14 +++
 board/mscc/ocelot/Makefile           |   4 +
 board/mscc/ocelot/ocelot.c           |  58 ++++++++++
 configs/mscc_ocelot_defconfig        |  73 +++++++++++++
 configs/mscc_ocelot_pcb120_defconfig |  66 ++++++++++++
 include/configs/vcoreiii.h           |  82 +++++++++++++++
 12 files changed, 522 insertions(+)
 create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
 create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
 create mode 100644 arch/mips/dts/ocelot_pcb120.dts
 create mode 100644 arch/mips/dts/ocelot_pcb123.dts
 create mode 100644 board/mscc/ocelot/Kconfig
 create mode 100644 board/mscc/ocelot/Makefile
 create mode 100644 board/mscc/ocelot/ocelot.c
 create mode 100644 configs/mscc_ocelot_defconfig
 create mode 100644 configs/mscc_ocelot_pcb120_defconfig
 create mode 100644 include/configs/vcoreiii.h
MAINTAINERS +5 -0
index 53a3c5bec6..c906ca006b 100644
@@ -490,6 +490,11 @@ M:	Lars Povlsen <[email protected]>
 M:	Horatiu Vultur <[email protected]>
 S:	Maintained
 F:	arch/mips/mach-mscc/
+F:	arch/mips/dts/mscc*
+F:	arch/mips/dts/ocelot*
+F:	board/mscc/
+F:	configs/mscc*
+F:	include/configs/vcoreiii.h
 
 MMC
 M:	Jaehoon Chung <[email protected]>
arch/mips/dts/mscc,ocelot.dtsi new file +152 -0

152 lines not on this page · raw message

arch/mips/dts/mscc,ocelot_pcb.dtsi new file +42 -0

42 lines not on this page · raw message

arch/mips/dts/ocelot_pcb120.dts new file +12 -0
new file mode 100644
index 0000000000..47d305a614
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,ocelot_pcb.dtsi"
+
+/ {
+	model = "Ocelot PCB120 Reference Board";
+	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+};
arch/mips/dts/ocelot_pcb123.dts new file +12 -0
new file mode 100644
index 0000000000..17d8d326ce
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,ocelot_pcb.dtsi"
+
+/ {
+	model = "Ocelot PCB123 Reference Board";
+	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+};
arch/mips/mach-mscc/Kconfig +2 -0
index a8cace0e79..fc806fc1f3 100644
@@ -79,4 +79,6 @@ config DDRTYPE_MT47H128M8HQ
 
 endchoice
 
+source "board/mscc/ocelot/Kconfig"
+
 endmenu
board/mscc/ocelot/Kconfig new file +14 -0
new file mode 100644
index 0000000000..9ddc0880b1
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_OCELOT
+
+config SYS_BOARD
+	default "ocelot"
+
+config SYS_CONFIG_NAME
+	default "ocelot"
+
+endif
board/mscc/ocelot/Makefile new file +4 -0
new file mode 100644
index 0000000000..9f28c81268
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_OCELOT)	:= ocelot.o
+
board/mscc/ocelot/ocelot.c new file +58 -0

58 lines not on this page · raw message

configs/mscc_ocelot_defconfig new file +73 -0

73 lines not on this page · raw message

configs/mscc_ocelot_pcb120_defconfig new file +66 -0

66 lines not on this page · raw message

include/configs/vcoreiii.h new file +82 -0

82 lines not on this page · raw message

Signature · 1 line
2.19.2
author
#6 lore raw

PATCH v4 6/7 MSCC: add board support for the Luton based evaluation board

In reply to Gregory CLEMENT

Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 87 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-mscc/Kconfig    |  2 +
 board/mscc/luton/Kconfig       | 14 ++++++
 board/mscc/luton/Makefile      |  3 ++
 board/mscc/luton/luton.c       | 28 +++++++++++
 configs/mscc_luton_defconfig   | 66 ++++++++++++++++++++++++++
 8 files changed, 237 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 configs/mscc_luton_defconfig
MAINTAINERS +1 -0
index c906ca006b..4ce19aef11 100644
@@ -490,6 +490,7 @@ M:	Lars Povlsen <[email protected]>
 M:	Horatiu Vultur <[email protected]>
 S:	Maintained
 F:	arch/mips/mach-mscc/
+F:	arch/mips/dts/luton*
 F:	arch/mips/dts/mscc*
 F:	arch/mips/dts/ocelot*
 F:	board/mscc/
arch/mips/dts/luton_pcb091.dts new file +36 -0
new file mode 100644
index 0000000000..74f9274c21
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+	model = "Luton10 PCB091 Reference Board";
+	compatible = "mscc,luton-pcb091", "mscc,luton";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	spi-flash at 0 {
+		compatible = "spi-flash";
+		spi-max-frequency = <18000000>; /* input clock */
+		reg = <0>; /* CS0 */
+		spi-cs-high;
+	};
+};
+
arch/mips/dts/mscc,luton.dtsi new file +87 -0

87 lines not on this page · raw message

arch/mips/mach-mscc/Kconfig +2 -0
index fc806fc1f3..0e35b77c9d 100644
@@ -81,4 +81,6 @@ endchoice
 
 source "board/mscc/ocelot/Kconfig"
 
+source "board/mscc/luton/Kconfig"
+
 endmenu
board/mscc/luton/Kconfig new file +14 -0
new file mode 100644
index 0000000000..e1199808d5
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+if SOC_LUTON
+
+config SYS_VENDOR
+	default "mscc"
+
+config SYS_BOARD
+	default "luton"
+
+config SYS_CONFIG_NAME
+	default "luton"
+
+endif
board/mscc/luton/Makefile new file +3 -0
new file mode 100644
index 0000000000..b27f7c7739
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_LUTON)	:= luton.o
board/mscc/luton/luton.c new file +28 -0
new file mode 100644
index 0000000000..41fc6d56a7
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MSCC_GPIO_ALT0		0x88
+#define MSCC_GPIO_ALT1		0x8C
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_debug_uart_init(void)
+{
+	/* too early for the pinctrl driver, so configure the UART pins here */
+	setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
+}
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	return 0;
+}
configs/mscc_luton_defconfig new file +66 -0

66 lines not on this page · raw message

Signature · 1 line
2.19.2
#7 lore raw

PATCH v4 6/7 MSCC: add board support for the Luton based evaluation board

Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:

Quoted 60 lines

Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 87 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-mscc/Kconfig    |  2 +
 board/mscc/luton/Kconfig       | 14 ++++++
 board/mscc/luton/Makefile      |  3 ++
 board/mscc/luton/luton.c       | 28 +++++++++++
 configs/mscc_luton_defconfig   | 66 ++++++++++++++++++++++++++
 8 files changed, 237 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 configs/mscc_luton_defconfig
configs/mscc_luton_defconfig new file +32 -0
new file mode 100644
index 0000000000..47fe12b6ee
@@ -0,0 +1,66 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y

configs/mscc_luton_defconfig line 42

Quoted 10 lines
configs/mscc_luton_defconfig new file +10 -0
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y

this gives now a build warning

===================== WARNING ====================== CONFIG_OF_EMBED is enabled. This option should only be used for debugging purposes. Please use CONFIG_OF_SEPARATE for boards in mainline. See doc/README.fdt-control for more info.
====================================================

Shall I change it when applying or do you want to test it first and send a follow-up patch?

Quoted 25 lines
configs/mscc_luton_defconfig new file +24 -0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
Signature · 1 line
- Daniel
author
#8 lore raw

PATCH v4 6/7 MSCC: add board support for the Luton based evaluation board

Hi Daniel,

Quoted 74 lines · Daniel Schwierzeck

Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:

Quoted 60 lines

Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 87 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-mscc/Kconfig    |  2 +
 board/mscc/luton/Kconfig       | 14 ++++++
 board/mscc/luton/Makefile      |  3 ++
 board/mscc/luton/luton.c       | 28 +++++++++++
 configs/mscc_luton_defconfig   | 66 ++++++++++++++++++++++++++
 8 files changed, 237 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 configs/mscc_luton_defconfig
configs/mscc_luton_defconfig new file +32 -0
new file mode 100644
index 0000000000..47fe12b6ee
@@ -0,0 +1,66 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y

configs/mscc_luton_defconfig line 42

Quoted 10 lines
configs/mscc_luton_defconfig new file +10 -0
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y

this gives now a build warning

Quoted 6 lines

===================== WARNING ====================== CONFIG_OF_EMBED is enabled. This option should only be used for debugging purposes. Please use CONFIG_OF_SEPARATE for boards in mainline. See doc/README.fdt-control for more info.
====================================================

I did not get this warning. For now I base my series on v2018.11, should I base it on v2019.01-rc1 (i didn't realized it was already released) ?

Quoted 4 lines

Shall I change it when applying or do you want to test it first and send a follow-up patch?

I'd like to test it to be sure it continue to work.

Thanks,

Gregory

Quoted 29 lines
Quoted 26 lines
configs/mscc_luton_defconfig new file +24 -0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
Signature · 1 line
- Daniel
Signature · 3 lines
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
author
#9 lore raw

PATCH v4 6/7 MSCC: add board support for the Luton based evaluation board

Hi Daniel,

Quoted 91 lines · Gregory CLEMENT

Hi Daniel,

Quoted 74 lines · Daniel Schwierzeck

Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:

Quoted 60 lines

Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 87 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-mscc/Kconfig    |  2 +
 board/mscc/luton/Kconfig       | 14 ++++++
 board/mscc/luton/Makefile      |  3 ++
 board/mscc/luton/luton.c       | 28 +++++++++++
 configs/mscc_luton_defconfig   | 66 ++++++++++++++++++++++++++
 8 files changed, 237 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 configs/mscc_luton_defconfig
configs/mscc_luton_defconfig new file +32 -0
new file mode 100644
index 0000000000..47fe12b6ee
@@ -0,0 +1,66 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y

configs/mscc_luton_defconfig line 42

Quoted 10 lines
configs/mscc_luton_defconfig new file +10 -0
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y

this gives now a build warning

Quoted 6 lines

===================== WARNING ====================== CONFIG_OF_EMBED is enabled. This option should only be used for debugging purposes. Please use CONFIG_OF_SEPARATE for boards in mainline. See doc/README.fdt-control for more info.
====================================================

I did not get this warning. For now I base my series on v2018.11, should I base it on v2019.01-rc1 (i didn't realized it was already released) ?

Quoted 2 lines
Quoted 4 lines
Quoted 2 lines

Shall I change it when applying or do you want to test it first and send a follow-up patch?

I'd like to test it to be sure it continue to work.

I had a closer look on this issue and actually we have already a patch series to apply which it is planned to be sent very soon. With this new series we will be able to support multiple boards with this series CONFIG_OF_SEPARATE will be used instead of CONFIG_OF_EMBED.

Would it be possible to keep this series as is ?

Thanks,

Gregory

Quoted 43 lines

Thanks,

Gregory

Quoted 29 lines
Quoted 26 lines
configs/mscc_luton_defconfig new file +24 -0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_LZMA=y
+CONFIG_XZ=y
Signature · 1 line
- Daniel
Signature · 7 lines
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot
Signature · 3 lines
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
#10 lore raw

PATCH v4 6/7 MSCC: add board support for the Luton based evaluation board

Am 17.12.18 um 10:55 schrieb Gregory CLEMENT:

Quoted 98 lines

Hi Daniel,

Quoted 94 lines · Gregory CLEMENT

Hi Daniel,

Quoted 74 lines · Daniel Schwierzeck

Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:

Quoted 60 lines

Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 87 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-mscc/Kconfig    |  2 +
 board/mscc/luton/Kconfig       | 14 ++++++
 board/mscc/luton/Makefile      |  3 ++
 board/mscc/luton/luton.c       | 28 +++++++++++
 configs/mscc_luton_defconfig   | 66 ++++++++++++++++++++++++++
 8 files changed, 237 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 configs/mscc_luton_defconfig
configs/mscc_luton_defconfig new file +32 -0
new file mode 100644
index 0000000000..47fe12b6ee
@@ -0,0 +1,66 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y

configs/mscc_luton_defconfig line 42

Quoted 10 lines
configs/mscc_luton_defconfig new file +10 -0
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y

this gives now a build warning

Quoted 6 lines

===================== WARNING ====================== CONFIG_OF_EMBED is enabled. This option should only be used for debugging purposes. Please use CONFIG_OF_SEPARATE for boards in mainline. See doc/README.fdt-control for more info.
====================================================

I did not get this warning. For now I base my series on v2018.11, should I base it on v2019.01-rc1 (i didn't realized it was already released) ?

Quoted 4 lines

Shall I change it when applying or do you want to test it first and send a follow-up patch?

Quoted 9 lines
Quoted 1 line

I'd like to test it to be sure it continue to work.

I had a closer look on this issue and actually we have already a patch series to apply which it is planned to be sent very soon. With this new series we will be able to support multiple boards with this series CONFIG_OF_SEPARATE will be used instead of CONFIG_OF_EMBED.

Would it be possible to keep this series as is ?

I asked because I had to fix some minor merge conflicts when applying and I had to re-sync the defconfig files due to various changes in mainline. Thus I need to update your patches anyway and a simply removing CONFIG_OF_EMBED=y would be a trivial fix.

You can review the current patch queue at u-boot-mips/microsemi which is based on u-boot-mips/next.

Signature · 1 line
- Daniel
author
#11 lore raw

PATCH v4 6/7 MSCC: add board support for the Luton based evaluation board

Hi Daniel,

Quoted 109 lines · Daniel Schwierzeck

Am 17.12.18 um 10:55 schrieb Gregory CLEMENT:

Quoted 98 lines

Hi Daniel,

Quoted 94 lines · Gregory CLEMENT

Hi Daniel,

Quoted 74 lines · Daniel Schwierzeck

Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:

Quoted 60 lines

Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/mips/dts/luton_pcb091.dts | 36 ++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 87 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-mscc/Kconfig    |  2 +
 board/mscc/luton/Kconfig       | 14 ++++++
 board/mscc/luton/Makefile      |  3 ++
 board/mscc/luton/luton.c       | 28 +++++++++++
 configs/mscc_luton_defconfig   | 66 ++++++++++++++++++++++++++
 8 files changed, 237 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 configs/mscc_luton_defconfig
configs/mscc_luton_defconfig new file +32 -0
new file mode 100644
index 0000000000..47fe12b6ee
@@ -0,0 +1,66 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y

configs/mscc_luton_defconfig line 42

Quoted 10 lines
configs/mscc_luton_defconfig new file +10 -0
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_EMBED=y

this gives now a build warning

Quoted 6 lines

===================== WARNING ====================== CONFIG_OF_EMBED is enabled. This option should only be used for debugging purposes. Please use CONFIG_OF_SEPARATE for boards in mainline. See doc/README.fdt-control for more info.
====================================================

I did not get this warning. For now I base my series on v2018.11, should I base it on v2019.01-rc1 (i didn't realized it was already released) ?

Quoted 4 lines

Shall I change it when applying or do you want to test it first and send a follow-up patch?

Quoted 9 lines
Quoted 1 line

I'd like to test it to be sure it continue to work.

I had a closer look on this issue and actually we have already a patch series to apply which it is planned to be sent very soon. With this new series we will be able to support multiple boards with this series CONFIG_OF_SEPARATE will be used instead of CONFIG_OF_EMBED.

Would it be possible to keep this series as is ?

Quoted 7 lines

I asked because I had to fix some minor merge conflicts when applying and I had to re-sync the defconfig files due to various changes in mainline. Thus I need to update your patches anyway and a simply removing CONFIG_OF_EMBED=y would be a trivial fix.

You can review the current patch queue at u-boot-mips/microsemi which is based on u-boot-mips/next.

I tested you branch and it worked on both Ocelot and Luton. So I'm fine with your changes.

Thanks !

Gregory

Quoted 3 lines
Signature · 2 lines
-- 
- Daniel
Signature · 3 lines
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
author
#12 lore raw

PATCH v4 7/7 MIPS: bootm: Add support for compatibility with redboot

In reply to Gregory CLEMENT

The kernels built to be launch by redboot (such as the Vcore III) have different expectation in the way the data were passed.

Unlike with yamon, the command line is expected to be a single string passed in argv[1]. An other expectation is that the arguments are located in the cached address space.

However, like yamon, they expect that rd_start and rd_size was passed by the bootloader in the command line of the kernel.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/mips/Kconfig     |  4 +++
 arch/mips/lib/bootm.c | 76 +++++++++++++++++++++++++++++++------------
 2 files changed, 60 insertions(+), 20 deletions(-)
arch/mips/Kconfig +4 -0
index bfe9c11069..eae5cb0f99 100644
@@ -63,6 +63,7 @@ config ARCH_MSCC
 	bool "Support MSCC VCore-III"
 	select OF_CONTROL
 	select DM
+	select MIPS_BOOT_CMDLINE_SINGLESTRING
 
 config ARCH_BMIPS
 	bool "Support BMIPS SoCs"

@@ -466,6 +467,9 @@ config MIPS_BOOT_CONFIG_WORD1
 	help
 	  Value which is inserted as boot config word 1.
 
+config MIPS_BOOT_CMDLINE_SINGLESTRING
+	bool
+
 endif
 
 endmenu
arch/mips/lib/bootm.c +56 -20

137 lines not on this page · raw message

Signature · 1 line
2.19.2
#13 lore raw

v4 cover Add support for the SoCs found in Microsemi switches

In reply to Gregory CLEMENT

Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:

Quoted 138 lines

Hello,

For the record this the fourth version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III.

We found them on various advanced switches product.

The support for Ocelot already have been submit to Linux, but not yet the Luton support.

The comments on v3 were fewer and quite easy to address, so I am able to send a new version right one (hopping it will be the final one :) ).

Gregory

Changelog:

v3 -> v4:

- add the support for the legacy kernel more generic and more related to the old bootloader: redboot
- removed useless test on CONFIG_ARCH_MSCC in arch/mips/mach-mscc/include/ioremap.h
- add an explanation about the cache instruction lock in hal_vcoreiii_ddr_failed()
- use __raw_read/write instead of directly use pointer dereferencing
- use rmb instead of asm volatile("" : : : "memory");
- remove remaining C++ style comment
- use __maybe_unused instead of __attribute__ ((unused))
- indent by an extra space the instructions in the delay slot

v2 -> v3:
- Added n entry in the MAINTAINER file for the SoCs
- Fixup the last errors from checkpatch, the remaining ones are only about volatile, long line and Kconfig, but each ones have good reason to be here.
- Add SPI NAND flash support in device tree and configuration files, the driver are already be merged in U-Boot.
- In order to improve boot time, setup the TLB to allow using cache in the memory mapped to the SPI NOR.
- Removed all the macro REG_CFG to only keep direct access to memory.
- Put back the setting of the interrupt map as it is needed by mainline kernel (without it the kernel doesn't finish to boot)
- During DDR training, prevent the compiler reordering the instruction.
- Add early debug support to Ocelot (it was already done for Luton)

v1 -> v2:
- a big clean-up for indentation and some style issue
- usage of the clrsetbits family functions where it was possible
- split the patches for Ocelot and Luton
- add a new patch to introduce the icache_lock function which was in the mscc directory in the first version
- remove more unused define in the platform header files
- use the automatic cache size detection instead of hard coding it
- reduce the tlb init to only two entries for the IO as needed by the kernel
- remove the interrupt disabling
- fix the ddr init for luton

Gregory CLEMENT (7):
MIPS: move create_tlb() in an proper header: mipsregs.h
MIPS: Allow to prefetch and lock instructions into cache
MSCC: add support for Ocelot SoCs
MSCC: add support for Luton SoCs
MSCC: add board support for the Ocelots based evaluation boards
MSCC: add board support for the Luton based evaluation board
MIPS: bootm: Add support for compatibility with redboot

 MAINTAINERS                                   |  13 +
 arch/mips/Kconfig                             |  10 +
 arch/mips/Makefile                            |   1 +
 arch/mips/cpu/cpu.c                           |  10 -
 arch/mips/dts/luton_pcb091.dts                |  36 +
 arch/mips/dts/mscc,luton.dtsi                 |  87 ++
 arch/mips/dts/mscc,ocelot.dtsi                | 152 ++++
 arch/mips/dts/mscc,ocelot_pcb.dtsi            |  42 +
 arch/mips/dts/ocelot_pcb120.dts               |  12 +
 arch/mips/dts/ocelot_pcb123.dts               |  12 +
 arch/mips/include/asm/cacheops.h              |  19 +
 arch/mips/include/asm/mipsregs.h              |  11 +
 arch/mips/lib/bootm.c                         |  76 +-
 arch/mips/mach-mscc/Kconfig                   |  86 ++
 arch/mips/mach-mscc/Makefile                  |   6 +
 arch/mips/mach-mscc/cpu.c                     | 102 +++
 arch/mips/mach-mscc/dram.c                    |  73 ++
 arch/mips/mach-mscc/include/ioremap.h         |  49 ++
 arch/mips/mach-mscc/include/mach/common.h     |  28 +
 arch/mips/mach-mscc/include/mach/ddr.h        | 814 ++++++++++++++++++
 .../mips/mach-mscc/include/mach/luton/luton.h |  24 +
 .../include/mach/luton/luton_devcpu_gcb.h     |  14 +
 .../include/mach/luton/luton_icpu_cfg.h       | 245 ++++++
 .../mach-mscc/include/mach/ocelot/ocelot.h    |  24 +
 .../include/mach/ocelot/ocelot_devcpu_gcb.h   |  21 +
 .../include/mach/ocelot/ocelot_icpu_cfg.h     | 274 ++++++
 arch/mips/mach-mscc/include/mach/tlb.h        |  55 ++
 arch/mips/mach-mscc/lowlevel_init.S           |  30 +
 arch/mips/mach-mscc/lowlevel_init_luton.S     |  62 ++
 arch/mips/mach-mscc/reset.c                   |  30 +
 board/mscc/luton/Kconfig                      |  14 +
 board/mscc/luton/Makefile                     |   3 +
 board/mscc/luton/luton.c                      |  28 +
 board/mscc/ocelot/Kconfig                     |  14 +
 board/mscc/ocelot/Makefile                    |   4 +
 board/mscc/ocelot/ocelot.c                    |  58 ++
 configs/mscc_luton_defconfig                  |  66 ++
 configs/mscc_ocelot_defconfig                 |  73 ++
 configs/mscc_ocelot_pcb120_defconfig          |  66 ++
 include/configs/vcoreiii.h                    |  82 ++
 40 files changed, 2796 insertions(+), 30 deletions(-)
 create mode 100644 arch/mips/dts/luton_pcb091.dts
 create mode 100644 arch/mips/dts/mscc,luton.dtsi
 create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
 create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
 create mode 100644 arch/mips/dts/ocelot_pcb120.dts
 create mode 100644 arch/mips/dts/ocelot_pcb123.dts
 create mode 100644 arch/mips/mach-mscc/Kconfig
 create mode 100644 arch/mips/mach-mscc/Makefile
 create mode 100644 arch/mips/mach-mscc/cpu.c
 create mode 100644 arch/mips/mach-mscc/dram.c
 create mode 100644 arch/mips/mach-mscc/include/ioremap.h
 create mode 100644 arch/mips/mach-mscc/include/mach/common.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
 create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
 create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
 create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
 create mode 100644 arch/mips/mach-mscc/reset.c
 create mode 100644 board/mscc/luton/Kconfig
 create mode 100644 board/mscc/luton/Makefile
Quoted 9 lines
 create mode 100644 board/mscc/luton/luton.c
 create mode 100644 board/mscc/ocelot/Kconfig
 create mode 100644 board/mscc/ocelot/Makefile
 create mode 100644 board/mscc/ocelot/ocelot.c
 create mode 100644 configs/mscc_luton_defconfig
 create mode 100644 configs/mscc_ocelot_defconfig
 create mode 100644 configs/mscc_ocelot_pcb120_defconfig
 create mode 100644 include/configs/vcoreiii.h

series applied to u-boot-mips, thanks.

I left out the last patch to avoid patching generic code at this point of the 2019.01 release cycle. Also I'm still not happy with it, some further comments will follow.

As discussed I did a resync of the defconfig files and removed CONFIG_OF_EMBED.

Signature · 1 line
- Daniel