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arm64: dts: fsl: use a generic node name for m25p80 flashes

PATCH RESEND Applied Alexandre Belloni 2 participants 6 messages Dec 18, 2018 – Jan 11, 2019

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Alexandre Belloni

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#0 lore raw

PATCH RESEND v2 1/3 arm64: dts: fsl: use a generic node name for m25p80 flashes

Use a generic node name for the m25p80 flashes on ls1043 and ls1046 boards.

Signed-off-by Alexandre Belloni <[email protected]>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +-
 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +1 -1
index dff3d648172e..8468e652a262 100644
@@ -138,7 +138,7 @@
 	bus-num = <0>;
 	status = "okay";
 
-	qflash0: s25fl128s@0 {
+	qflash0: flash@0 {
 		compatible = "spansion,m25p80";
 		#address-cells = <1>;
 		#size-cells = <1>;
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +1 -1
index e58a8ca1386c..51a518b64053 100644
@@ -167,7 +167,7 @@
 	bus-num = <0>;
 	status = "okay";
 
-	qflash0: s25fl128s@0 {
+	qflash0: flash@0 {
 		compatible = "spansion,m25p80";
 		#address-cells = <1>;
 		#size-cells = <1>;
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +2 -2
index a59b48203688..1e3d570412d2 100644
@@ -103,7 +103,7 @@
 	bus-num = <0>;
 	status = "okay";
 
-	qflash0: s25fs512s@0 {
+	qflash0: flash@0 {
 		compatible = "spansion,m25p80";
 		#address-cells = <1>;
 		#size-cells = <1>;

@@ -111,7 +111,7 @@
 		reg = <0>;
 	};
 
-	qflash1: s25fs512s@1 {
+	qflash1: flash@1 {
 		compatible = "spansion,m25p80";
 		#address-cells = <1>;
 		#size-cells = <1>;
Signature · 1 line
2.20.0
author
#1 lore raw

PATCH RESEND v2 2/3 arm64: dts: fsl: ls1046a: disable the flash controller by default

Set the Integrated Flash Controller status to disabled so each board has the option to enable it. All the existing users have status = "okay" so there is no functional change.

Signed-off-by Alexandre Belloni <[email protected]>
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +1 -0
index 51cbd50012d6..90dc3b616ea7 100644
@@ -200,6 +200,7 @@
 			compatible = "fsl,ifc", "simple-bus";
 			reg = <0x0 0x1530000 0x0 0x10000>;
 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
 		};
 
 		qspi: spi@1550000 {
Signature · 1 line
2.20.0
author
#2 lore raw

PATCH 3/3 arm64: dts: fsl: ls1046a: disable uarts by default

In reply to Alexandre Belloni

Disable the UARTs by defaultto avoid registering unused UARTs. This effectively change the number of registered UARTS for the RDB and QDS from 4 to 2 but this seems the right thing to do.

It is especially useful when connecting other 8250 uart on PCIe for example as the default maximum number of 8250 UARTs that can be registered is 4.

Signed-off-by Alexandre Belloni <[email protected]>
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +4 -0
index 90dc3b616ea7..4caf4df1c7b1 100644
@@ -423,6 +423,7 @@
 			reg = <0x00 0x21c0500 0x0 0x100>;
 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 1>;
+			status = "disabled";
 		};
 
 		duart1: serial@21c0600 {

@@ -430,6 +431,7 @@
 			reg = <0x00 0x21c0600 0x0 0x100>;
 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 1>;
+			status = "disabled";
 		};
 
 		duart2: serial@21d0500 {

@@ -437,6 +439,7 @@
 			reg = <0x0 0x21d0500 0x0 0x100>;
 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 1>;
+			status = "disabled";
 		};
 
 		duart3: serial@21d0600 {

@@ -444,6 +447,7 @@
 			reg = <0x0 0x21d0600 0x0 0x100>;
 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 1>;
+			status = "disabled";
 		};
 
 		gpio0: gpio@2300000 {
Signature · 1 line
2.20.0
author
#3 lore raw

PATCH RESEND v2 1/1 MAINTAINERS: Add a maintainer for MSCC MIPS SoCs

In reply to Alexandre Belloni

Microsemi has been bought by Microchip and Microchip is supporting those SoCs.

Signed-off-by Alexandre Belloni <[email protected]>
---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
MAINTAINERS +2 -1
index f4855974f325..50223cba6ddb 100644
@@ -9801,8 +9801,9 @@ F:	drivers/dma/at_xdmac.c
 
 MICROSEMI MIPS SOCS
 M:	Alexandre Belloni <[email protected]>
+M:	Microchip Linux Driver Support <[email protected]>
 L:	[email protected]
-S:	Maintained
+S:	Supported
 F:	arch/mips/generic/board-ocelot.c
 F:	arch/mips/configs/generic/board-ocelot.config
 F:	arch/mips/boot/dts/mscc/
Signature · 7 lines
2.20.0


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author
#4 lore raw

Re: [RESEND PATCH v2] MAINTAINERS: Add a maintainer for MSCC MIPS SoCs

Please ignore this, it was meant for the MIPS maintainers.

Quoted 26 lines · Alexandre Belloni

Microsemi has been bought by Microchip and Microchip is supporting those SoCs.

Signed-off-by Alexandre Belloni <[email protected]>
---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
MAINTAINERS +2 -1
index f4855974f325..50223cba6ddb 100644
@@ -9801,8 +9801,9 @@ F:	drivers/dma/at_xdmac.c
 
 MICROSEMI MIPS SOCS
 M:	Alexandre Belloni <[email protected]>
+M:	Microchip Linux Driver Support <[email protected]>
 L:	[email protected]
-S:	Maintained
+S:	Supported
 F:	arch/mips/generic/board-ocelot.c
 F:	arch/mips/configs/generic/board-ocelot.config
 F:	arch/mips/boot/dts/mscc/
Signature · 1 line
2.20.0
Signature · 3 lines
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com