arm64: dts: sdm845: Add sdm845 GPU interconnect

PATCH Superseded Jordan Crouse 5 participants 14 messages Dec 20, 2018 – Feb 21, 2019

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Device tree bindings DRM drivers DRM misc Arm Qualcomm mailing list +3 more subsystems

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Jordan Crouse

author

2018-12-20 17:30 UTC #0 lore raw

v3 cover arm64: dts: sdm845: Add sdm845 GPU interconnect

Add interconnect consumer definitions for the sdm845 GPU to device tree.

This patchset includes the a6xx gpu support for interconnect as previously seen here:

https://patchwork.kernel.org/patch/10718587/

It was pulled into this patchset because the interconnect-name was removed from the DT at the suggestion of Rob Herring and it was easier to combine all of these together into one set.

Everything is based on the base GPU DT changes:
https://patchwork.freedesktop.org/series/39308/

As well as the DT nodes from Georgi:
https://patchwork.kernel.org/patch/10719483/

v3: Remove hardcoded interconnect name from driver and bindings

Jordan Crouse (3):
drm/msm/a6xx: Add support for an interconnect path
dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU
arm64: dts: sdm845: Add interconnect for GPU

 .../devicetree/bindings/display/msm/gpu.txt   |  4 ++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |  2 ++
 drivers/gpu/drm/msm/Kconfig                   |  1 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c         | 20 +++++++++++++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c       |  9 +++++++++
 drivers/gpu/drm/msm/msm_gpu.h                 |  3 +++
 6 files changed, 39 insertions(+)

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Jordan Crouse

author

2018-12-20 17:30 UTC #1 lore raw

PATCH v3 1/3 drm/msm/a6xx: Add support for an interconnect path

Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist.

v5: Remove hardcoded interconnect name and just use the default
v4: Don't use a port string at all to skip the need for names in the DT
v3: Use macros and change port string per Georgi Djakov

Signed-off-by Jordan Crouse <[email protected]>

---

 drivers/gpu/drm/msm/Kconfig             |  1 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c   | 20 ++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  9 +++++++++
 drivers/gpu/drm/msm/msm_gpu.h           |  3 +++
 4 files changed, 33 insertions(+)

drivers/gpu/drm/msm/Kconfig +1 -0

index 843a9d40c05e..990c4350f0c4 100644
@@ -5,6 +5,7 @@ config DRM_MSM
 	depends on ARCH_QCOM || (ARM && COMPILE_TEST)
 	depends on OF && COMMON_CLK
 	depends on MMU
+	depends on INTERCONNECT || !INTERCONNECT
 	select QCOM_MDT_LOADER if ARCH_QCOM
 	select REGULATOR
 	select DRM_KMS_HELPER

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +20 -0

index 0fb4718ef0df..781b601c6045 100644
@@ -2,6 +2,7 @@
 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
 
 #include <linux/clk.h>
+#include <linux/interconnect.h>
 #include <linux/pm_opp.h>
 #include <soc/qcom/cmd-db.h>

@@ -63,6 +64,9 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
 
 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
 {
+	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+	struct msm_gpu *gpu = &adreno_gpu->base;
 	int ret;
 
 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);

@@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
 		dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
 	gmu->freq = gmu->gpu_freqs[index];
+
+	/*
+	 * Eventually we will want to scale the path vote with the frequency but
+	 * for now leave it at max so that the performance is nominal.
+	 */
+	icc_set(gpu->icc_path, 0, MBps_to_icc(7216));
 }
 
 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)

@@ -680,6 +690,8 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
 
 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 {
+	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+	struct msm_gpu *gpu = &adreno_gpu->base;
 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 	int status, ret;

@@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 	if (ret)
 		goto out;
 
+	/* Set the bus quota to a reasonable value for boot */
+	icc_set(gpu->icc_path, 0, MBps_to_icc(3072));
+
 	a6xx_gmu_irq_enable(gmu);
 
 	/* Check to see if we are doing a cold or warm boot */

@@ -735,6 +750,8 @@ bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
 
 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
 {
+	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+	struct msm_gpu *gpu = &adreno_gpu->base;
 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 	u32 val;

@@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
 	/* Tell RPMh to power off the GPU */
 	a6xx_rpmh_stop(gmu);
 
+	/* Remove the bus vote */
+	icc_set(gpu->icc_path, 0, 0);
+
 	clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
 
 	pm_runtime_put_sync(gmu->dev);

drivers/gpu/drm/msm/adreno/adreno_gpu.c +9 -0

index bfeea50fca8a..6629dc3506eb 100644
@@ -18,6 +18,7 @@
  */
 
 #include <linux/ascii85.h>
+#include <linux/interconnect.h>
 #include <linux/kernel.h>
 #include <linux/pm_opp.h>
 #include <linux/slab.h>

@@ -695,6 +696,11 @@ static int adreno_get_pwrlevels(struct device *dev,
 
 	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
 
+	/* Check for an interconnect path for the bus */
+	gpu->icc_path = of_icc_get(dev, NULL);
+	if (IS_ERR(gpu->icc_path))
+		gpu->icc_path = NULL;
+
 	return 0;
 }

@@ -732,10 +738,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 
 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
 {
+	struct msm_gpu *gpu = &adreno_gpu->base;
 	unsigned int i;
 
 	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
 		release_firmware(adreno_gpu->fw[i]);
 
+	icc_put(gpu->icc_path);
+
 	msm_gpu_cleanup(&adreno_gpu->base);
 }

drivers/gpu/drm/msm/msm_gpu.h +3 -0

index fc4040e24a6b..66e0f28dfed8 100644
@@ -19,6 +19,7 @@
 #define __MSM_GPU_H__
 
 #include <linux/clk.h>
+#include <linux/interconnect.h>
 #include <linux/regulator/consumer.h>
 
 #include "msm_drv.h"

@@ -118,6 +119,8 @@ struct msm_gpu {
 	struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
 	uint32_t fast_rate;
 
+	struct icc_path *icc_path;
+
 	/* Hang and Inactivity Detection:
 	 */
 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */

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Doug Anderson

2018-12-20 19:28 UTC #2 lore raw

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

Hi,

Quoted 11 lines · Jordan Crouse

Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist.
v5: Remove hardcoded interconnect name and just use the default
v4: Don't use a port string at all to skip the need for names in the DT
v3: Use macros and change port string per Georgi Djakov

Quoted 8 lines

Signed-off-by Jordan Crouse <[email protected]>

---

 drivers/gpu/drm/msm/Kconfig             |  1 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c   | 20 ++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  9 +++++++++
 drivers/gpu/drm/msm/msm_gpu.h           |  3 +++
 4 files changed, 33 insertions(+)

There is very little difference between this an the previous version [1]. Maybe could have kept Rob Clark's Acked-by? The only change was:

- gpu->icc_path = of_icc_get(dev, "gfx-mem");
+ gpu->icc_path = of_icc_get(dev, NULL);

Also: I assume that this is still intended to go through Georgi's tree?

[1] https://lkml.kernel.org/r/[email protected]

-Doug
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Doug Anderson

2019-01-18 18:06 UTC #3 lore raw

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

In reply to Jordan Crouse

Hi,

Quoted 8 lines · Jordan Crouse

Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist.
v5: Remove hardcoded interconnect name and just use the default

nit: ${SUBJECT} says v3, but this is v5.

I'll put in my usual plug for considering "patman" to help post patches. Even though it lives in the u-boot git repo it's still a gem for kernel work.
<http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README>

drivers/gpu/drm/msm/adreno/a6xx_gmu.c static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) · line 97

Quoted 10 lines

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +6 -0

@@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
                dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
        gmu->freq = gmu->gpu_freqs[index];
+
+       /*
+        * Eventually we will want to scale the path vote with the frequency but
+        * for now leave it at max so that the performance is nominal.
+        */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(7216));

You'll need to change icc_set() here to icc_set_bw() to match v13, AKA:

- https://patchwork.kernel.org/patch/10766335/
- https://lkml.kernel.org/r/[email protected]

drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) · line 711

Quoted 6 lines

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0

@@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
        if (ret)
                goto out;
 
+       /* Set the bus quota to a reasonable value for boot */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(3072));

This will also need to change to icc_set_bw()

drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) · line 802

Quoted 6 lines

drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0

@@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
        /* Tell RPMh to power off the GPU */
        a6xx_rpmh_stop(gmu);
 
+       /* Remove the bus vote */
+       icc_set(gpu->icc_path, 0, 0);

This will also need to change to icc_set_bw()

I have the same questions for this series that I had in response to the email ("[v5 2/3] drm/msm/dpu: Integrate interconnect API in MDSS")
<https://lkml.kernel.org/r/CAD=FV=XUeMTGH+CDwGs3PfK4igdQrCbwucw7_2ViBc4i7grvxg@mail.gmail.com>

Copy / pasting here (with minor name changes) so folks don't have to follow links / search email.

I'm curious what the plan is for landing this series. Rob / Gerogi:
do you have any preference? Options I'd imagine:

A) Wait until interconnect lands (in 5.1?) and land this through msm-next in the version after (5.2?)

B) Georgi provides an immutable branch for interconnect when his lands (assuming he's landing via pull request) and that gets pulled into the the relevant drm tree.

C) Rob Acks this series and indicates that it should go in through Gerogi's tree (probably only works if Georgi plans to send a pull request). If we're going this route then (IIUC) we'd want to land this in Gerogi's tree sooner rather than later so it can get some bake time? NOTE: as per my prior reply, I believe Rob has already Acked this patch.

Does anyone have a preference? It's be nice if whoever is planning to land this could indicate whether they'd prefer Jordan send a new version to handle the API change or if the relevant maintainer can just do the fixup when the patch lands.

Thanks!

-Doug
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Rob Clark

2019-01-18 19:16 UTC #4 lore raw

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

Quoted 78 lines · Doug Anderson

Hi,
Quoted 8 lines · Jordan Crouse
Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist.
v5: Remove hardcoded interconnect name and just use the default
nit: ${SUBJECT} says v3, but this is v5.
I'll put in my usual plug for considering "patman" to help post patches. Even though it lives in the u-boot git repo it's still a gem for kernel work.
<http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) · line 97
Quoted 10 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +6 -0
@@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
                dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
        gmu->freq = gmu->gpu_freqs[index];
+
+       /*
+        * Eventually we will want to scale the path vote with the frequency but
+        * for now leave it at max so that the performance is nominal.
+        */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(7216));
You'll need to change icc_set() here to icc_set_bw() to match v13, AKA:
- https://patchwork.kernel.org/patch/10766335/
- https://lkml.kernel.org/r/[email protected]
drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) · line 711
Quoted 6 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0
@@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
        if (ret)
                goto out;
 
+       /* Set the bus quota to a reasonable value for boot */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(3072));
This will also need to change to icc_set_bw()
drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) · line 802
Quoted 6 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0
@@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
        /* Tell RPMh to power off the GPU */
        a6xx_rpmh_stop(gmu);
 
+       /* Remove the bus vote */
+       icc_set(gpu->icc_path, 0, 0);
This will also need to change to icc_set_bw()
I have the same questions for this series that I had in response to the email ("[v5 2/3] drm/msm/dpu: Integrate interconnect API in MDSS")
<https://lkml.kernel.org/r/CAD=FV=XUeMTGH+CDwGs3PfK4igdQrCbwucw7_2ViBc4i7grvxg@mail.gmail.com>
Copy / pasting here (with minor name changes) so folks don't have to follow links / search email.
==
I'm curious what the plan is for landing this series. Rob / Gerogi:
do you have any preference? Options I'd imagine:
A) Wait until interconnect lands (in 5.1?) and land this through msm-next in the version after (5.2?)
B) Georgi provides an immutable branch for interconnect when his lands (assuming he's landing via pull request) and that gets pulled into the the relevant drm tree.

Quoted 7 lines

C) Rob Acks this series and indicates that it should go in through Gerogi's tree (probably only works if Georgi plans to send a pull request). If we're going this route then (IIUC) we'd want to land this in Gerogi's tree sooner rather than later so it can get some bake time? NOTE: as per my prior reply, I believe Rob has already Acked this patch.

I'm ok to ack and have it land via Georgi's tree, if Georgi wants to do that. Or otherwise, I could maybe coordinate w/ airlied to send a 2nd late msm-next pr including the gpu and display interconnect patches.

BR,
-R

Quoted 11 lines

Does anyone have a preference? It's be nice if whoever is planning to land this could indicate whether they'd prefer Jordan send a new version to handle the API change or if the relevant maintainer can just do the fixup when the patch lands.
Thanks!
-Doug

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[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Georgi Djakov

2019-01-21 17:13 UTC #5 lore raw

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

Hi Rob,

Quoted 87 lines · Rob Clark

Quoted 78 lines · Doug Anderson
Hi,
Quoted 8 lines · Jordan Crouse
Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist.
v5: Remove hardcoded interconnect name and just use the default
nit: ${SUBJECT} says v3, but this is v5.
I'll put in my usual plug for considering "patman" to help post patches. Even though it lives in the u-boot git repo it's still a gem for kernel work.
<http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) · line 97
Quoted 10 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +6 -0
@@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
                dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
        gmu->freq = gmu->gpu_freqs[index];
+
+       /*
+        * Eventually we will want to scale the path vote with the frequency but
+        * for now leave it at max so that the performance is nominal.
+        */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(7216));
You'll need to change icc_set() here to icc_set_bw() to match v13, AKA:
- https://patchwork.kernel.org/patch/10766335/
- https://lkml.kernel.org/r/[email protected]
drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) · line 711
Quoted 6 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0
@@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
        if (ret)
                goto out;
 
+       /* Set the bus quota to a reasonable value for boot */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(3072));
This will also need to change to icc_set_bw()
drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) · line 802
Quoted 6 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0
@@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
        /* Tell RPMh to power off the GPU */
        a6xx_rpmh_stop(gmu);
 
+       /* Remove the bus vote */
+       icc_set(gpu->icc_path, 0, 0);
This will also need to change to icc_set_bw()
I have the same questions for this series that I had in response to the email ("[v5 2/3] drm/msm/dpu: Integrate interconnect API in MDSS")
<https://lkml.kernel.org/r/CAD=FV=XUeMTGH+CDwGs3PfK4igdQrCbwucw7_2ViBc4i7grvxg@mail.gmail.com>
Copy / pasting here (with minor name changes) so folks don't have to follow links / search email.
==
I'm curious what the plan is for landing this series. Rob / Gerogi:
do you have any preference? Options I'd imagine:
A) Wait until interconnect lands (in 5.1?) and land this through msm-next in the version after (5.2?)
B) Georgi provides an immutable branch for interconnect when his lands (assuming he's landing via pull request) and that gets pulled into the the relevant drm tree.
Quoted 7 lines
C) Rob Acks this series and indicates that it should go in through Gerogi's tree (probably only works if Georgi plans to send a pull request). If we're going this route then (IIUC) we'd want to land this in Gerogi's tree sooner rather than later so it can get some bake time? NOTE: as per my prior reply, I believe Rob has already Acked this patch.

Quoted 4 lines

I'm ok to ack and have it land via Georgi's tree, if Georgi wants to do that. Or otherwise, I could maybe coordinate w/ airlied to send a 2nd late msm-next pr including the gpu and display interconnect patches.

I'm fine either way. But it would be nice if both patches (this one and the dt-bindings go together. The v6 of this patch applies cleanly to my tree, but the next one (2/3) with the dt-bindings doesn't.

Thanks,
Georgi
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Doug Anderson

2019-01-22 21:17 UTC #6 lore raw

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

Hi,

Quoted 91 lines · Georgi Djakov

Hi Rob,
Quoted 87 lines · Rob Clark
Quoted 85 lines · Doug Anderson
Hi,
Quoted 8 lines · Jordan Crouse
Try to get the interconnect path for the GPU and vote for the maximum bandwidth to support all frequencies. This is needed for performance. Later we will want to scale the bandwidth based on the frequency to also optimize for power but that will require some device tree infrastructure that does not yet exist.
v5: Remove hardcoded interconnect name and just use the default
nit: ${SUBJECT} says v3, but this is v5.
I'll put in my usual plug for considering "patman" to help post patches. Even though it lives in the u-boot git repo it's still a gem for kernel work.
<http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) · line 97
Quoted 10 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +6 -0
@@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
                dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 
        gmu->freq = gmu->gpu_freqs[index];
+
+       /*
+        * Eventually we will want to scale the path vote with the frequency but
+        * for now leave it at max so that the performance is nominal.
+        */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(7216));
You'll need to change icc_set() here to icc_set_bw() to match v13, AKA:
- https://patchwork.kernel.org/patch/10766335/
- https://lkml.kernel.org/r/[email protected]
drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) · line 711
Quoted 6 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0
@@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
        if (ret)
                goto out;
 
+       /* Set the bus quota to a reasonable value for boot */
+       icc_set(gpu->icc_path, 0, MBps_to_icc(3072));
This will also need to change to icc_set_bw()
drivers/gpu/drm/msm/adreno/a6xx_gmu.c int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) · line 802
Quoted 6 lines
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +2 -0
@@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
        /* Tell RPMh to power off the GPU */
        a6xx_rpmh_stop(gmu);
 
+       /* Remove the bus vote */
+       icc_set(gpu->icc_path, 0, 0);
This will also need to change to icc_set_bw()
I have the same questions for this series that I had in response to the email ("[v5 2/3] drm/msm/dpu: Integrate interconnect API in MDSS")
<https://lkml.kernel.org/r/CAD=FV=XUeMTGH+CDwGs3PfK4igdQrCbwucw7_2ViBc4i7grvxg@mail.gmail.com>
Copy / pasting here (with minor name changes) so folks don't have to follow links / search email.
==
I'm curious what the plan is for landing this series. Rob / Gerogi:
do you have any preference? Options I'd imagine:
A) Wait until interconnect lands (in 5.1?) and land this through msm-next in the version after (5.2?)
B) Georgi provides an immutable branch for interconnect when his lands (assuming he's landing via pull request) and that gets pulled into the the relevant drm tree.
C) Rob Acks this series and indicates that it should go in through Gerogi's tree (probably only works if Georgi plans to send a pull request). If we're going this route then (IIUC) we'd want to land this in Gerogi's tree sooner rather than later so it can get some bake time? NOTE: as per my prior reply, I believe Rob has already Acked this patch.

Quoted 8 lines

Quoted 4 lines
I'm ok to ack and have it land via Georgi's tree, if Georgi wants to do that. Or otherwise, I could maybe coordinate w/ airlied to send a 2nd late msm-next pr including the gpu and display interconnect patches.
I'm fine either way. But it would be nice if both patches (this one and the dt-bindings go together. The v6 of this patch applies cleanly to my tree, but the next one (2/3) with the dt-bindings doesn't.

Ah, right. You need to be based upon commit 85437cddf4e5 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings") from Rob Clark's msm-next AKA
<git://people.freedesktop.org/~robclark/linux>

...so I guess the easiest is to have the bindings could go through Rob Clark's tree and the code through you tree if that's what people want to do?

-Doug
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Doug Anderson

2019-01-18 21:54 UTC #7 lore raw

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

In reply to Doug Anderson

Hi,

Quoted 4 lines · Doug Anderson

It's be nice if whoever is planning to
land this could indicate whether they'd prefer Jordan send a new version to handle the API change or if the relevant maintainer can just do the fixup when the patch lands.

Breadcrumbs: Jordan went ahead and posted a new version ("[PATCH v6] drm/msm/a6xx: Add support for an interconnect path"):

https://patchwork.kernel.org/patch/10771501/

-Doug
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Jordan Crouse

author

2018-12-20 17:30 UTC #8 lore raw

PATCH v3 2/3 dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

In reply to Jordan Crouse

Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt.

Signed-off-by Jordan Crouse <[email protected]>

---

 Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/display/msm/gpu.txt +4 -0

index 9c89f4fdb8ca..5b04393dcb15 100644
@@ -20,6 +20,8 @@ Required properties:
    - qcom,adreno-630.2
 - iommus: optional phandle to an adreno iommu instance
 - operating-points-v2: optional phandle to the OPP operating points
+- interconnect: optional phandle to a interconnect provider.  See
+  ../interconnect/interconnect.txt for details.
 - qcom,gmu: For GMU attached devices a phandle to the GMU device that will
   control the power for the GPU. Applicable targets:
     - qcom,adreno-630.2

@@ -68,6 +70,8 @@ Example a6xx (with GMU):
 
 		operating-points-v2 = <&gpu_opp_table>;
 
+		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
+
 		qcom,gmu = <&gmu>;
 	};
 };

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Doug Anderson

Reviewed-by on v3 2/3

2018-12-20 19:30 UTC #9 lore raw

Re: [PATCH v3 2/3] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

Hi,

Quoted 9 lines · Jordan Crouse

Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by Jordan Crouse <[email protected]>
---
 Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++
 1 file changed, 4 insertions(+)

I would have been fine if you had kept my tag (even though 50% of the patch changed!). ...but here it is again:

Reviewed-by Douglas Anderson <[email protected]>

I assume this will be going through Georgi's tree w/ the previous patch.

-Doug

Rob Herring

maintainer Reviewed-by on v3 2/3

2018-12-21 18:28 UTC #10 lore raw

Re: [PATCH v3 2/3] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

In reply to Jordan Crouse

Quoted 9 lines · Jordan Crouse

Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by Jordan Crouse <[email protected]>
---
 Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++
 1 file changed, 4 insertions(+)

Reviewed-by Rob Herring <[email protected]>

Georgi Djakov

Acked-by on v3 2/3

2019-02-21 12:06 UTC #11 lore raw

Re: [PATCH v3 2/3] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

In reply to Jordan Crouse

Hi,

Quoted 14 lines · Jordan Crouse

Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by Jordan Crouse <[email protected]>
---
 Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++
 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/display/msm/gpu.txt +0 -0
index 9c89f4fdb8ca..5b04393dcb15 100644

Documentation/devicetree/bindings/display/msm/gpu.txt Required properties: · line 23

Quoted 4 lines

Documentation/devicetree/bindings/display/msm/gpu.txt +1 -0

@@ -20,6 +20,8 @@ Required properties:
    - qcom,adreno-630.2
 - iommus: optional phandle to an adreno iommu instance
 - operating-points-v2: optional phandle to the OPP operating points
+- interconnect: optional phandle to a interconnect provider.  See

Nit: s/interconnect:/interconnects:/
Nit: s/a interconnect/an interconnect/

Quoted 6 lines

Documentation/devicetree/bindings/display/msm/gpu.txt +1 -0

+  ../interconnect/interconnect.txt for details.
 - qcom,gmu: For GMU attached devices a phandle to the GMU device that will
   control the power for the GPU. Applicable targets:
     - qcom,adreno-630.2

Documentation/devicetree/bindings/display/msm/gpu.txt Example a6xx (with GMU): · line 77

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/gpu.txt +2 -0

@@ -68,6 +70,8 @@ Example a6xx (with GMU):
 
 		operating-points-v2 = <&gpu_opp_table>;
 
+		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
+
 		qcom,gmu = <&gmu>;
 	};
 };

Acked-by Georgi Djakov <[email protected]>

Thanks,
Georgi
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Jordan Crouse

author

2018-12-20 17:30 UTC #12 lore raw

PATCH v3 3/3 arm64: dts: sdm845: Add interconnect for GPU

In reply to Jordan Crouse

Define an interconnect port for the GPU to set bus capabilities.

Signed-off-by Jordan Crouse <[email protected]>

---

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/arm64/boot/dts/qcom/sdm845.dtsi +2 -0

index 1005f1eb1920..155e4ba74c96 100644
@@ -1369,6 +1369,8 @@
 
 			operating-points-v2 = <&gpu_opp_table>;
 
+			interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
+
 			qcom,gmu = <&gmu>;
 
 			gpu_opp_table: opp-table {

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Doug Anderson

Reviewed-by on v3 3/3

2018-12-20 19:31 UTC #13 lore raw

Re: [PATCH v3 3/3] arm64: dts: sdm845: Add interconnect for GPU

Hi,

Quoted 9 lines · Jordan Crouse

Define an interconnect port for the GPU to set bus capabilities.
Signed-off-by Jordan Crouse <[email protected]>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
 1 file changed, 2 insertions(+)

For going through Andy's tree once the bindings land (presumably in Georgi's tree).

Reviewed-by Douglas Anderson <[email protected]>

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