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i386: Enable NPT and NRIPSAVE for Epyc CPUs

RFC PATCH In review Vitaly Kuznetsov 2 participants 3 messages Dec 21, 2018 – Jan 18, 2019

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Vitaly Kuznetsov

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RFC PATCH 1/1 i386: Enable NPT and NRIPSAVE for Epyc CPUs

Epyc CPUs support NPT and NRIPSAVE features and KVM exposes these when present. Add them to EPYC and EPYC-IBPB cpu models.

Signed-off-by Vitaly Kuznetsov <[email protected]>

---
- RFC part: I'm not sure when these features first appeared, we may want to modify some Opteron_* models too.

---
 target/i386/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)
target/i386/cpu.c +4 -0
index 677a3bd5fb..0a10fbeccc 100644
@@ -2843,6 +2843,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_XSAVE_XGETBV1,
         .features[FEAT_6_EAX] =
             CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC Processor",
         .cache_info = &epyc_cache_info,

@@ -2891,6 +2893,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_XSAVE_XGETBV1,
         .features[FEAT_6_EAX] =
             CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC Processor (with IBPB)",
         .cache_info = &epyc_cache_info,
Signature · 1 line
2.19.2
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#1 lore raw
Quoted 7 lines · Vitaly Kuznetsov

Epyc CPUs support NPT and NRIPSAVE features and KVM exposes these when present. Add them to EPYC and EPYC-IBPB cpu models.

Signed-off-by Vitaly Kuznetsov <[email protected]>

---
- RFC part: I'm not sure when these features first appeared, we may want to modify some Opteron_* models too.

According to http://instlatx64.atw.hu/ data (thanks to Radim!) NRIPSAVE apeared somewhere in Opteron_G3 lifetime (e.g. QuadCore AMD Opteron 2378 has is, QuadCore AMD Opteron HE 2344 doesn't), NPT was introduced a bit earlier.

To be on the safe side we can probably add NPT and NRIPSAVE to Opteron_G4 and Opteron_G5 too and leave Opteron_G3 as it is.

Signature · 1 line
Vitaly
#2 lore raw
In reply to Vitaly Kuznetsov
Quoted 4 lines · Vitaly Kuznetsov

Epyc CPUs support NPT and NRIPSAVE features and KVM exposes these when present. Add them to EPYC and EPYC-IBPB cpu models.

Signed-off-by Vitaly Kuznetsov <[email protected]>

Sorry for taking so long to reply:

Quoted 12 lines

---
- RFC part: I'm not sure when these features first appeared, we may want to modify some Opteron_* models too.

---
 target/i386/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)
target/i386/cpu.c +0 -0
index 677a3bd5fb..0a10fbeccc 100644

target/i386/cpu.c static X86CPUDefinition builtin_x86_defs[] = { · line 2847

Quoted 5 lines
target/i386/cpu.c +2 -0
@@ -2843,6 +2843,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_XSAVE_XGETBV1,
         .features[FEAT_6_EAX] =
             CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,

You'll need to add EPYC*.ntp=off and EPYC*.nripsave=off to pc_compat_3_1.

Quoted 15 lines
target/i386/cpu.c +2 -0
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC Processor",
         .cache_info = &epyc_cache_info,

@@ -2891,6 +2893,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_XSAVE_XGETBV1,
         .features[FEAT_6_EAX] =
             CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC Processor (with IBPB)",
         .cache_info = &epyc_cache_info,
Signature · 1 line
2.19.2
Signature · 1 line
Eduardo