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mmc: sdhci-esdhc-imx: fix HS400 timing issue

PATCH In review BOUGH CHEN 3 participants 3 messages Dec 27, 2018 – Jan 14, 2019

Subsystems (5)
Stable branch Arm i.MX and Layerscape MMC, SD and SDIO Secure digital host controller interface (SDHCI) driver +1 more subsystems
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BOUGH CHEN

author maintainer
#0 lore raw

PATCH 1/1 mmc: sdhci-esdhc-imx: fix HS400 timing issue

Now tuning reset will be done when the timing is MMC_TIMING_LEGACY/ MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. But for timing MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400 timing is not right.

Here is the process of init HS400, first finish tuning in HS200 mode, then switch to HS mode and 8 bit DDR mode, finally switch to HS400 mode. If we do tuning reset in HS mode, this will cause HS400 mode lost the tuning setting, which will cause CRC error.

This fix commit d9370424c948 ("mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card").

Signed-off-by Haibo Chen <[email protected]>
Cc [email protected] # v4.12+
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
 1 file changed, 1 insertion(+)
drivers/mmc/host/sdhci-esdhc-imx.c +1 -0
index d0d319398a54..984cc1a788cb 100644
@@ -979,6 +979,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 	case MMC_TIMING_UHS_SDR25:
 	case MMC_TIMING_UHS_SDR50:
 	case MMC_TIMING_UHS_SDR104:
+	case MMC_TIMING_MMC_HS:
 	case MMC_TIMING_MMC_HS200:
 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 		break;
Signature · 1 line
2.17.1
maintainer Acked-by on v1 1/1
#1 lore raw
Quoted 9 lines · BOUGH CHEN

Now tuning reset will be done when the timing is MMC_TIMING_LEGACY/ MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. But for timing MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400 timing is not right.

Here is the process of init HS400, first finish tuning in HS200 mode, then switch to HS mode and 8 bit DDR mode, finally switch to HS400 mode. If we do tuning reset in HS mode, this will cause HS400 mode lost the tuning setting, which will cause CRC error.

Quoted 5 lines

This fix commit d9370424c948 ("mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card").

Signed-off-by Haibo Chen <[email protected]>
Cc [email protected] # v4.12+
Acked-by Adrian Hunter <[email protected]>
Quoted 17 lines
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
 1 file changed, 1 insertion(+)
drivers/mmc/host/sdhci-esdhc-imx.c +1 -0
index d0d319398a54..984cc1a788cb 100644
@@ -979,6 +979,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 	case MMC_TIMING_UHS_SDR25:
 	case MMC_TIMING_UHS_SDR50:
 	case MMC_TIMING_UHS_SDR104:
+	case MMC_TIMING_MMC_HS:
 	case MMC_TIMING_MMC_HS200:
 		writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 		break;
#2 lore raw
In reply to BOUGH CHEN
Quoted 10 lines · BOUGH CHEN

Now tuning reset will be done when the timing is MMC_TIMING_LEGACY/ MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. But for timing MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400 timing is not right.

Here is the process of init HS400, first finish tuning in HS200 mode, then switch to HS mode and 8 bit DDR mode, finally switch to HS400 mode. If we do tuning reset in HS mode, this will cause HS400 mode lost the tuning setting, which will cause CRC error.

Quoted 5 lines

This fix commit d9370424c948 ("mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card").

Signed-off-by Haibo Chen <[email protected]>
Cc [email protected] # v4.12+

Applied for next, thanks!

Kind regards
Uffe

Quoted 19 lines
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
 1 file changed, 1 insertion(+)
drivers/mmc/host/sdhci-esdhc-imx.c +1 -1
index d0d319398a54..984cc1a788cb 100644
@@ -979,6 +979,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
        case MMC_TIMING_UHS_SDR25:
        case MMC_TIMING_UHS_SDR50:
        case MMC_TIMING_UHS_SDR104:
+       case MMC_TIMING_MMC_HS:
        case MMC_TIMING_MMC_HS200:
                writel(m, host->ioaddr + ESDHC_MIX_CTRL);
                break;
--

2.17.1